Agis Zisimatos
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74dad42969
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Fixes in FPGA power schematic
- Add ferrite bead part number
- Fixes ERC error in PG of 1.1V pin
- Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-03-29 18:20:43 +03:00 |
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Agis Zisimatos
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e73022566e
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Select ferrite bead for TRX
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-03-23 17:24:58 +02:00 |
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Agis Zisimatos
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f03aa75813
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Select I limit resistor
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-03-23 16:53:05 +02:00 |
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Ilias Daradimos
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b8ad60e557
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Reanotate sheets
Update symbol and port direction
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-03-22 12:29:50 +02:00 |
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Agis Zisimatos
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0c57d0fecc
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Add ferrite bead in 3V3 supply voltage
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-03-22 11:19:06 +02:00 |
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Agis Zisimatos
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334406da80
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Add initial transceiver schematic
Fixes #https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/5
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-03-17 21:17:23 +02:00 |
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Papadeas Pierros
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046229765a
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Add interfaces between modules (closes #1)
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
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2022-03-16 20:03:26 +02:00 |