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25 Commits (c3122ab59c6379e3e8a2c7d776283b2630a6b7e8)

Author SHA1 Message Date
Agis Zisimatos c3122ab59c Add oscillator in FPGA 
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 11:06:18 +03:00
Agis Zisimatos fb9e050bc9 Add test points for GPIOs 
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 11:06:18 +03:00
Agis Zisimatos 8b5c631826 Add MSPI as default boot mode and NOR flash 
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 11:06:18 +03:00
Agis Zisimatos 0e86bb6f49 Add LED indicators for DONE and INITN 
Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 11:06:18 +03:00
Agis Zisimatos 84e1cc8608 Implement FPGA JTAG 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 11:01:35 +03:00
Agis Zisimatos e749327cc2 Place I/Q and SPI of FPGA 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 11:01:35 +03:00
aris12 51240ee009 add antenna deployment 2022-04-04 17:54:24 +03:00
Papadeas Pierros bd4ef8fe52 Expose PV as top level sheet 
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
 2022-04-01 10:46:44 +03:00
Papadeas Pierros 929c19d30a Fix PWR flag 
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
 2022-03-30 16:37:00 +03:00
Agis Zisimatos f524588635 Fix footprints that changed by previous commit 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-03-30 11:38:37 +03:00
Agis Zisimatos 420d3a0f91 Update symbols and footprints in power schematic 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-03-30 10:36:34 +03:00
Agis Zisimatos fef6cc6ec3 Add pull-down resistor in load switch ON pin 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-03-29 19:48:29 +03:00
Agis Zisimatos 6654506502 Add transceiver TCXO 
Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/17

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-03-29 19:23:07 +03:00
Agis Zisimatos 95c29a28e7 Add current limit resistor value 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-03-29 19:05:22 +03:00
Agis Zisimatos 74dad42969 Fixes in FPGA power schematic 
- Add ferrite bead part number
- Fixes ERC error in PG of 1.1V pin
- Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-03-29 18:20:43 +03:00
Agis Zisimatos e73022566e Select ferrite bead for TRX 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-03-23 17:24:58 +02:00
Agis Zisimatos f03aa75813 Select I limit resistor 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-03-23 16:53:05 +02:00
Ilias Daradimos 055c01d8fa Move GND power flag to top sheet 
Update symbols

Signed-off-by: Ilias Daradimos <ilias@libre.space>
 2022-03-22 13:23:56 +02:00
Ilias Daradimos b8ad60e557 Reanotate sheets 
Update symbol and port direction

Signed-off-by: Ilias Daradimos <ilias@libre.space>
 2022-03-22 12:29:50 +02:00
Agis Zisimatos 0c57d0fecc Add ferrite bead in 3V3 supply voltage 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-03-22 11:19:06 +02:00
Agis Zisimatos 334406da80 Add initial transceiver schematic 
Fixes #https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/5

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-03-17 21:17:23 +02:00
Papadeas Pierros 046229765a Add interfaces between modules (closes #1) 
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
 2022-03-16 20:03:26 +02:00
Ilias Daradimos 5af3e504fc Add PV charging 
Added bus charging

Signed-off-by: Ilias Daradimos <ilias@libre.space>
 2022-03-16 15:26:59 +02:00
Papadeas Pierros d98f5d08a7 Add MCU module schematic 
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
 2022-03-15 19:25:35 +02:00
Vasilis Tsiligiannis 3c07252fae Add initial KiCad project 
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
 2022-02-21 13:11:33 +02:00