Define stack-up and manufacturer rules

* Define also net classes and pre-define traces and vias
* Fixes #2

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
merge-requests/7/head
Agis Zisimatos 2022-04-12 16:02:42 +03:00
parent bbb8da9459
commit 12dd47cf35
3 changed files with 293 additions and 168 deletions

@ -1 +1 @@
Subproject commit 892b8d7188ebc81fd6dd7fa2f54b974cd2a5a430
Subproject commit 427ce69151eae2cb11805eb1ea140d3b9ef543bd

View File

@ -1,13 +1,15 @@
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View File

@ -48,7 +48,18 @@
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [],
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
},
{
"gap": 0.2,
"via_gap": 0.5,
"width": 0.12
}
],
"drc_exclusions": [],
"meta": {
"filename": "board_design_settings.json",
@ -98,22 +109,37 @@
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_copper_edge_clearance": 0.075,
"min_hole_clearance": 0.25,
"min_clearance": 0.09999999999999999,
"min_copper_edge_clearance": 0.19999999999999998,
"min_hole_clearance": 0.19999999999999998,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_microvia_diameter": 0.0,
"min_microvia_drill": 0.0,
"min_silk_clearance": 0.0,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.09999999999999999,
"min_via_annular_width": 0.13,
"min_via_diameter": 0.39999999999999997,
"use_height_for_length_calcs": true
},
"track_widths": [],
"via_dimensions": [],
"zones_allow_external_fillets": false,
"track_widths": [
0.0,
0.14,
0.2,
0.6,
1.0
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
},
{
"diameter": 0.5,
"drill": 0.2
}
],
"zones_allow_external_fillets": true,
"zones_use_no_outline": true
},
"layer_presets": []
@ -339,19 +365,43 @@
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"clearance": 0.1,
"diff_pair_gap": 0.2,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"diff_pair_width": 0.12,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.6,
"via_drill": 0.4,
"track_width": 0.2,
"via_diameter": 0.5,
"via_drill": 0.2,
"wire_width": 6.0
},
{
"bus_width": 12.0,
"clearance": 0.1,
"diff_pair_gap": 0.1,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.35,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "50-Ohm",
"nets": [
"/fpga/CFG_CLK",
"/transceiver/RF09CAP_N",
"/transceiver/RF09CAP_P",
"/transceiver/RF09N",
"/transceiver/RF09P"
],
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.14,
"via_diameter": 0.5,
"via_drill": 0.2,
"wire_width": 6.0
}
],