Fix clock-in in FPGA pins
Fixes #28 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>merge-requests/14/head
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@ -1 +1 @@
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Subproject commit 9d9a499b545e560bf781fa553c03414ac32dade2
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Subproject commit b07c5fff9895e3924d95ec917824a95a593327ef
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File diff suppressed because it is too large
Load Diff
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@ -33,9 +33,9 @@
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"other_text_thickness": 0.15,
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"other_text_upright": false,
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"pads": {
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"drill": 2.5,
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"height": 5.0,
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"width": 5.0
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"drill": 0.0,
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"height": 0.4,
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"width": 0.375
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},
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"silk_line_width": 0.15,
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"silk_text_italic": false,
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@ -392,6 +392,11 @@
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"name": "50-Ohm",
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"nets": [
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"/fpga/CFG_CLK",
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"/fpga/CFG_IO0",
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"/fpga/CFG_IO1",
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"/fpga/CFG_IO2",
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"/fpga/CFG_IO3",
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"/fpga/~{CFG_CS}",
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"/transceiver/RF09CAP_N",
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"/transceiver/RF09CAP_P",
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"/transceiver/RF09N",
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