2015-03-02 14:01:12 -07:00
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/*
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* Copyright (C) 2015 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/**
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* DOC: VC4 CRTC module
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*
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* In VC4, the Pixel Valve is what most closely corresponds to the
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* DRM's concept of a CRTC. The PV generates video timings from the
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* output's clock plus its configuration. It pulls scaled pixels from
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* the HVS at that timing, and feeds it to the encoder.
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*
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* However, the DRM CRTC also collects the configuration of all the
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* DRM planes attached to it. As a result, this file also manages
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* setup of the VC4 HVS's display elements on the CRTC.
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*
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* The 2835 has 3 different pixel valves. pv0 in the audio power
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* domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
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* image domain can feed either HDMI or the SDTV controller. The
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* pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
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* SDTV, etc.) according to which output type is chosen in the mux.
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*
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* For power management, the pixel valve's registers are all clocked
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* by the AXI clock, while the timings and FIFOs make use of the
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* output-specific clock. Since the encoders also directly consume
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* the CPRMAN clocks, and know what timings they need, they are the
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* ones that set the clock.
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*/
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#include "drm_atomic.h"
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#include "drm_atomic_helper.h"
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#include "drm_crtc_helper.h"
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#include "linux/clk.h"
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2015-11-30 13:34:01 -07:00
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#include "drm_fb_cma_helper.h"
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2015-03-02 14:01:12 -07:00
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#include "linux/component.h"
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#include "linux/of_device.h"
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#include "vc4_drv.h"
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#include "vc4_regs.h"
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struct vc4_crtc {
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struct drm_crtc base;
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const struct vc4_crtc_data *data;
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void __iomem *regs;
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drm/vc4: Implement precise vblank timestamping.
Precise vblank timestamping is implemented via the
usual scanout position based method. On VC4 the
pixelvalves PV do not have a scanout position
register. Only the hardware video scaler HVS has a
similar register which describes which scanline for
the output is currently composited and stored in the
HVS fifo for later consumption by the PV.
This causes a problem in that the HVS runs at a much
faster clock (system clock / audio gate) than the PV
which runs at video mode dot clock, so the unless the
fifo between HVS and PV is full, the HVS will progress
faster in its observable read line position than video
scan rate, so the HVS position reading can't be directly
translated into a scanout position for timestamp correction.
Additionally when the PV is in vblank, it doesn't consume
from the fifo, so the fifo gets full very quickly and then
the HVS stops compositing until the PV enters active scanout
and starts consuming scanlines from the fifo again, making
new space for the HVS to composite.
Therefore a simple translation of HVS read position into
elapsed time since (or to) start of active scanout does
not work, but for the most interesting cases we can still
get useful and sufficiently accurate results:
1. The PV enters active scanout of a new frame with the
fifo of the HVS completely full, and the HVS can refill
any fifo line which gets consumed and thereby freed up by
the PV during active scanout very quickly. Therefore the
PV and HVS work effectively in lock-step during active
scanout with the fifo never having more than 1 scanline
freed up by the PV before it gets refilled. The PV's
real scanout position is therefore trailing the HVS
compositing position as scanoutpos = hvspos - fifosize
and we can get the true scanoutpos as HVS readpos minus
fifo size, so precise timestamping works while in active
scanout, except for the last few scanlines of the frame,
when the HVS reaches end of frame, stops compositing and
the PV catches up and drains the fifo. This special case
would only introduce minor errors though.
2. If we are in vblank, then we can only guess something
reasonable. If called from vblank irq, we assume the irq is
usually dispatched with minimum delay, so we can take a
timestamp taken at entry into the vblank irq handler as a
baseline and then add a full vblank duration until the
guessed start of active scanout. As irq dispatch is usually
pretty low latency this works with relatively low jitter and
good results.
If we aren't called from vblank then we could be anywhere
within the vblank interval, so we return a neutral result,
simply the current system timestamp, and hope for the best.
Measurement shows the generated timestamps to be rather precise,
and at least never off more than 1 vblank duration worst-case.
Limitations: Doesn't work well yet for interlaced video modes,
therefore disabled in interlaced mode for now.
v2: Use the DISPBASE registers to determine the FIFO size (changes
by anholt)
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2)
2016-06-23 00:17:50 -06:00
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/* Timestamp at start of vblank irq - unaffected by lock delays. */
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ktime_t t_vblank;
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2015-03-02 14:01:12 -07:00
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/* Which HVS channel we're using for our CRTC. */
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int channel;
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2016-03-31 19:38:20 -06:00
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u8 lut_r[256];
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u8 lut_g[256];
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u8 lut_b[256];
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drm/vc4: Implement precise vblank timestamping.
Precise vblank timestamping is implemented via the
usual scanout position based method. On VC4 the
pixelvalves PV do not have a scanout position
register. Only the hardware video scaler HVS has a
similar register which describes which scanline for
the output is currently composited and stored in the
HVS fifo for later consumption by the PV.
This causes a problem in that the HVS runs at a much
faster clock (system clock / audio gate) than the PV
which runs at video mode dot clock, so the unless the
fifo between HVS and PV is full, the HVS will progress
faster in its observable read line position than video
scan rate, so the HVS position reading can't be directly
translated into a scanout position for timestamp correction.
Additionally when the PV is in vblank, it doesn't consume
from the fifo, so the fifo gets full very quickly and then
the HVS stops compositing until the PV enters active scanout
and starts consuming scanlines from the fifo again, making
new space for the HVS to composite.
Therefore a simple translation of HVS read position into
elapsed time since (or to) start of active scanout does
not work, but for the most interesting cases we can still
get useful and sufficiently accurate results:
1. The PV enters active scanout of a new frame with the
fifo of the HVS completely full, and the HVS can refill
any fifo line which gets consumed and thereby freed up by
the PV during active scanout very quickly. Therefore the
PV and HVS work effectively in lock-step during active
scanout with the fifo never having more than 1 scanline
freed up by the PV before it gets refilled. The PV's
real scanout position is therefore trailing the HVS
compositing position as scanoutpos = hvspos - fifosize
and we can get the true scanoutpos as HVS readpos minus
fifo size, so precise timestamping works while in active
scanout, except for the last few scanlines of the frame,
when the HVS reaches end of frame, stops compositing and
the PV catches up and drains the fifo. This special case
would only introduce minor errors though.
2. If we are in vblank, then we can only guess something
reasonable. If called from vblank irq, we assume the irq is
usually dispatched with minimum delay, so we can take a
timestamp taken at entry into the vblank irq handler as a
baseline and then add a full vblank duration until the
guessed start of active scanout. As irq dispatch is usually
pretty low latency this works with relatively low jitter and
good results.
If we aren't called from vblank then we could be anywhere
within the vblank interval, so we return a neutral result,
simply the current system timestamp, and hope for the best.
Measurement shows the generated timestamps to be rather precise,
and at least never off more than 1 vblank duration worst-case.
Limitations: Doesn't work well yet for interlaced video modes,
therefore disabled in interlaced mode for now.
v2: Use the DISPBASE registers to determine the FIFO size (changes
by anholt)
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2)
2016-06-23 00:17:50 -06:00
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/* Size in pixels of the COB memory allocated to this CRTC. */
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u32 cob_size;
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2016-03-31 19:38:20 -06:00
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2015-03-02 14:01:12 -07:00
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struct drm_pending_vblank_event *event;
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};
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2015-12-28 14:25:41 -07:00
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struct vc4_crtc_state {
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struct drm_crtc_state base;
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/* Dlist area for this CRTC configuration. */
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struct drm_mm_node mm;
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};
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2015-03-02 14:01:12 -07:00
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static inline struct vc4_crtc *
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to_vc4_crtc(struct drm_crtc *crtc)
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{
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return (struct vc4_crtc *)crtc;
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}
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2015-12-28 14:25:41 -07:00
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static inline struct vc4_crtc_state *
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to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
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{
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return (struct vc4_crtc_state *)crtc_state;
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}
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2015-03-02 14:01:12 -07:00
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struct vc4_crtc_data {
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/* Which channel of the HVS this pixelvalve sources from. */
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int hvs_channel;
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2016-12-02 06:48:07 -07:00
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enum vc4_encoder_type encoder_types[4];
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2015-03-02 14:01:12 -07:00
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};
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#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
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#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
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#define CRTC_REG(reg) { reg, #reg }
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static const struct {
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u32 reg;
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const char *name;
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} crtc_regs[] = {
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CRTC_REG(PV_CONTROL),
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CRTC_REG(PV_V_CONTROL),
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2016-02-15 18:06:02 -07:00
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CRTC_REG(PV_VSYNCD_EVEN),
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2015-03-02 14:01:12 -07:00
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CRTC_REG(PV_HORZA),
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CRTC_REG(PV_HORZB),
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CRTC_REG(PV_VERTA),
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CRTC_REG(PV_VERTB),
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CRTC_REG(PV_VERTA_EVEN),
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CRTC_REG(PV_VERTB_EVEN),
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CRTC_REG(PV_INTEN),
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CRTC_REG(PV_INTSTAT),
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CRTC_REG(PV_STAT),
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CRTC_REG(PV_HACT_ACT),
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};
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static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
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DRM_INFO("0x%04x (%s): 0x%08x\n",
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crtc_regs[i].reg, crtc_regs[i].name,
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CRTC_READ(crtc_regs[i].reg));
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}
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}
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#ifdef CONFIG_DEBUG_FS
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int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
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{
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struct drm_info_node *node = (struct drm_info_node *)m->private;
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struct drm_device *dev = node->minor->dev;
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int crtc_index = (uintptr_t)node->info_ent->data;
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struct drm_crtc *crtc;
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struct vc4_crtc *vc4_crtc;
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int i;
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i = 0;
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list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
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if (i == crtc_index)
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break;
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i++;
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}
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if (!crtc)
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return 0;
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vc4_crtc = to_vc4_crtc(crtc);
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for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
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seq_printf(m, "%s (0x%04x): 0x%08x\n",
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crtc_regs[i].name, crtc_regs[i].reg,
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CRTC_READ(crtc_regs[i].reg));
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}
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return 0;
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}
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#endif
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drm/vc4: Implement precise vblank timestamping.
Precise vblank timestamping is implemented via the
usual scanout position based method. On VC4 the
pixelvalves PV do not have a scanout position
register. Only the hardware video scaler HVS has a
similar register which describes which scanline for
the output is currently composited and stored in the
HVS fifo for later consumption by the PV.
This causes a problem in that the HVS runs at a much
faster clock (system clock / audio gate) than the PV
which runs at video mode dot clock, so the unless the
fifo between HVS and PV is full, the HVS will progress
faster in its observable read line position than video
scan rate, so the HVS position reading can't be directly
translated into a scanout position for timestamp correction.
Additionally when the PV is in vblank, it doesn't consume
from the fifo, so the fifo gets full very quickly and then
the HVS stops compositing until the PV enters active scanout
and starts consuming scanlines from the fifo again, making
new space for the HVS to composite.
Therefore a simple translation of HVS read position into
elapsed time since (or to) start of active scanout does
not work, but for the most interesting cases we can still
get useful and sufficiently accurate results:
1. The PV enters active scanout of a new frame with the
fifo of the HVS completely full, and the HVS can refill
any fifo line which gets consumed and thereby freed up by
the PV during active scanout very quickly. Therefore the
PV and HVS work effectively in lock-step during active
scanout with the fifo never having more than 1 scanline
freed up by the PV before it gets refilled. The PV's
real scanout position is therefore trailing the HVS
compositing position as scanoutpos = hvspos - fifosize
and we can get the true scanoutpos as HVS readpos minus
fifo size, so precise timestamping works while in active
scanout, except for the last few scanlines of the frame,
when the HVS reaches end of frame, stops compositing and
the PV catches up and drains the fifo. This special case
would only introduce minor errors though.
2. If we are in vblank, then we can only guess something
reasonable. If called from vblank irq, we assume the irq is
usually dispatched with minimum delay, so we can take a
timestamp taken at entry into the vblank irq handler as a
baseline and then add a full vblank duration until the
guessed start of active scanout. As irq dispatch is usually
pretty low latency this works with relatively low jitter and
good results.
If we aren't called from vblank then we could be anywhere
within the vblank interval, so we return a neutral result,
simply the current system timestamp, and hope for the best.
Measurement shows the generated timestamps to be rather precise,
and at least never off more than 1 vblank duration worst-case.
Limitations: Doesn't work well yet for interlaced video modes,
therefore disabled in interlaced mode for now.
v2: Use the DISPBASE registers to determine the FIFO size (changes
by anholt)
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2)
2016-06-23 00:17:50 -06:00
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int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
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unsigned int flags, int *vpos, int *hpos,
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ktime_t *stime, ktime_t *etime,
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const struct drm_display_mode *mode)
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{
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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2017-01-09 04:25:45 -07:00
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struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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drm/vc4: Implement precise vblank timestamping.
Precise vblank timestamping is implemented via the
usual scanout position based method. On VC4 the
pixelvalves PV do not have a scanout position
register. Only the hardware video scaler HVS has a
similar register which describes which scanline for
the output is currently composited and stored in the
HVS fifo for later consumption by the PV.
This causes a problem in that the HVS runs at a much
faster clock (system clock / audio gate) than the PV
which runs at video mode dot clock, so the unless the
fifo between HVS and PV is full, the HVS will progress
faster in its observable read line position than video
scan rate, so the HVS position reading can't be directly
translated into a scanout position for timestamp correction.
Additionally when the PV is in vblank, it doesn't consume
from the fifo, so the fifo gets full very quickly and then
the HVS stops compositing until the PV enters active scanout
and starts consuming scanlines from the fifo again, making
new space for the HVS to composite.
Therefore a simple translation of HVS read position into
elapsed time since (or to) start of active scanout does
not work, but for the most interesting cases we can still
get useful and sufficiently accurate results:
1. The PV enters active scanout of a new frame with the
fifo of the HVS completely full, and the HVS can refill
any fifo line which gets consumed and thereby freed up by
the PV during active scanout very quickly. Therefore the
PV and HVS work effectively in lock-step during active
scanout with the fifo never having more than 1 scanline
freed up by the PV before it gets refilled. The PV's
real scanout position is therefore trailing the HVS
compositing position as scanoutpos = hvspos - fifosize
and we can get the true scanoutpos as HVS readpos minus
fifo size, so precise timestamping works while in active
scanout, except for the last few scanlines of the frame,
when the HVS reaches end of frame, stops compositing and
the PV catches up and drains the fifo. This special case
would only introduce minor errors though.
2. If we are in vblank, then we can only guess something
reasonable. If called from vblank irq, we assume the irq is
usually dispatched with minimum delay, so we can take a
timestamp taken at entry into the vblank irq handler as a
baseline and then add a full vblank duration until the
guessed start of active scanout. As irq dispatch is usually
pretty low latency this works with relatively low jitter and
good results.
If we aren't called from vblank then we could be anywhere
within the vblank interval, so we return a neutral result,
simply the current system timestamp, and hope for the best.
Measurement shows the generated timestamps to be rather precise,
and at least never off more than 1 vblank duration worst-case.
Limitations: Doesn't work well yet for interlaced video modes,
therefore disabled in interlaced mode for now.
v2: Use the DISPBASE registers to determine the FIFO size (changes
by anholt)
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2)
2016-06-23 00:17:50 -06:00
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u32 val;
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int fifo_lines;
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int vblank_lines;
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int ret = 0;
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/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
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/* Get optional system timestamp before query. */
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if (stime)
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*stime = ktime_get();
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/*
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|
|
* Read vertical scanline which is currently composed for our
|
|
|
|
|
* pixelvalve by the HVS, and also the scaler status.
|
|
|
|
|
*/
|
|
|
|
|
val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
|
|
|
|
|
|
|
|
|
|
/* Get optional system timestamp after query. */
|
|
|
|
|
if (etime)
|
|
|
|
|
*etime = ktime_get();
|
|
|
|
|
|
|
|
|
|
/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
|
|
|
|
|
|
|
|
|
|
/* Vertical position of hvs composed scanline. */
|
|
|
|
|
*vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
|
2016-07-19 12:59:00 -06:00
|
|
|
*hpos = 0;
|
|
|
|
|
|
|
|
|
|
if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
|
|
|
|
|
*vpos /= 2;
|
drm/vc4: Implement precise vblank timestamping.
Precise vblank timestamping is implemented via the
usual scanout position based method. On VC4 the
pixelvalves PV do not have a scanout position
register. Only the hardware video scaler HVS has a
similar register which describes which scanline for
the output is currently composited and stored in the
HVS fifo for later consumption by the PV.
This causes a problem in that the HVS runs at a much
faster clock (system clock / audio gate) than the PV
which runs at video mode dot clock, so the unless the
fifo between HVS and PV is full, the HVS will progress
faster in its observable read line position than video
scan rate, so the HVS position reading can't be directly
translated into a scanout position for timestamp correction.
Additionally when the PV is in vblank, it doesn't consume
from the fifo, so the fifo gets full very quickly and then
the HVS stops compositing until the PV enters active scanout
and starts consuming scanlines from the fifo again, making
new space for the HVS to composite.
Therefore a simple translation of HVS read position into
elapsed time since (or to) start of active scanout does
not work, but for the most interesting cases we can still
get useful and sufficiently accurate results:
1. The PV enters active scanout of a new frame with the
fifo of the HVS completely full, and the HVS can refill
any fifo line which gets consumed and thereby freed up by
the PV during active scanout very quickly. Therefore the
PV and HVS work effectively in lock-step during active
scanout with the fifo never having more than 1 scanline
freed up by the PV before it gets refilled. The PV's
real scanout position is therefore trailing the HVS
compositing position as scanoutpos = hvspos - fifosize
and we can get the true scanoutpos as HVS readpos minus
fifo size, so precise timestamping works while in active
scanout, except for the last few scanlines of the frame,
when the HVS reaches end of frame, stops compositing and
the PV catches up and drains the fifo. This special case
would only introduce minor errors though.
2. If we are in vblank, then we can only guess something
reasonable. If called from vblank irq, we assume the irq is
usually dispatched with minimum delay, so we can take a
timestamp taken at entry into the vblank irq handler as a
baseline and then add a full vblank duration until the
guessed start of active scanout. As irq dispatch is usually
pretty low latency this works with relatively low jitter and
good results.
If we aren't called from vblank then we could be anywhere
within the vblank interval, so we return a neutral result,
simply the current system timestamp, and hope for the best.
Measurement shows the generated timestamps to be rather precise,
and at least never off more than 1 vblank duration worst-case.
Limitations: Doesn't work well yet for interlaced video modes,
therefore disabled in interlaced mode for now.
v2: Use the DISPBASE registers to determine the FIFO size (changes
by anholt)
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2)
2016-06-23 00:17:50 -06:00
|
|
|
|
2016-07-19 12:59:00 -06:00
|
|
|
/* Use hpos to correct for field offset in interlaced mode. */
|
|
|
|
|
if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
|
|
|
|
|
*hpos += mode->crtc_htotal / 2;
|
|
|
|
|
}
|
drm/vc4: Implement precise vblank timestamping.
Precise vblank timestamping is implemented via the
usual scanout position based method. On VC4 the
pixelvalves PV do not have a scanout position
register. Only the hardware video scaler HVS has a
similar register which describes which scanline for
the output is currently composited and stored in the
HVS fifo for later consumption by the PV.
This causes a problem in that the HVS runs at a much
faster clock (system clock / audio gate) than the PV
which runs at video mode dot clock, so the unless the
fifo between HVS and PV is full, the HVS will progress
faster in its observable read line position than video
scan rate, so the HVS position reading can't be directly
translated into a scanout position for timestamp correction.
Additionally when the PV is in vblank, it doesn't consume
from the fifo, so the fifo gets full very quickly and then
the HVS stops compositing until the PV enters active scanout
and starts consuming scanlines from the fifo again, making
new space for the HVS to composite.
Therefore a simple translation of HVS read position into
elapsed time since (or to) start of active scanout does
not work, but for the most interesting cases we can still
get useful and sufficiently accurate results:
1. The PV enters active scanout of a new frame with the
fifo of the HVS completely full, and the HVS can refill
any fifo line which gets consumed and thereby freed up by
the PV during active scanout very quickly. Therefore the
PV and HVS work effectively in lock-step during active
scanout with the fifo never having more than 1 scanline
freed up by the PV before it gets refilled. The PV's
real scanout position is therefore trailing the HVS
compositing position as scanoutpos = hvspos - fifosize
and we can get the true scanoutpos as HVS readpos minus
fifo size, so precise timestamping works while in active
scanout, except for the last few scanlines of the frame,
when the HVS reaches end of frame, stops compositing and
the PV catches up and drains the fifo. This special case
would only introduce minor errors though.
2. If we are in vblank, then we can only guess something
reasonable. If called from vblank irq, we assume the irq is
usually dispatched with minimum delay, so we can take a
timestamp taken at entry into the vblank irq handler as a
baseline and then add a full vblank duration until the
guessed start of active scanout. As irq dispatch is usually
pretty low latency this works with relatively low jitter and
good results.
If we aren't called from vblank then we could be anywhere
within the vblank interval, so we return a neutral result,
simply the current system timestamp, and hope for the best.
Measurement shows the generated timestamps to be rather precise,
and at least never off more than 1 vblank duration worst-case.
Limitations: Doesn't work well yet for interlaced video modes,
therefore disabled in interlaced mode for now.
v2: Use the DISPBASE registers to determine the FIFO size (changes
by anholt)
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2)
2016-06-23 00:17:50 -06:00
|
|
|
|
|
|
|
|
/* This is the offset we need for translating hvs -> pv scanout pos. */
|
|
|
|
|
fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
|
|
|
|
|
|
|
|
|
|
if (fifo_lines > 0)
|
|
|
|
|
ret |= DRM_SCANOUTPOS_VALID;
|
|
|
|
|
|
|
|
|
|
/* HVS more than fifo_lines into frame for compositing? */
|
|
|
|
|
if (*vpos > fifo_lines) {
|
|
|
|
|
/*
|
|
|
|
|
* We are in active scanout and can get some meaningful results
|
|
|
|
|
* from HVS. The actual PV scanout can not trail behind more
|
|
|
|
|
* than fifo_lines as that is the fifo's capacity. Assume that
|
|
|
|
|
* in active scanout the HVS and PV work in lockstep wrt. HVS
|
|
|
|
|
* refilling the fifo and PV consuming from the fifo, ie.
|
|
|
|
|
* whenever the PV consumes and frees up a scanline in the
|
|
|
|
|
* fifo, the HVS will immediately refill it, therefore
|
|
|
|
|
* incrementing vpos. Therefore we choose HVS read position -
|
|
|
|
|
* fifo size in scanlines as a estimate of the real scanout
|
|
|
|
|
* position of the PV.
|
|
|
|
|
*/
|
|
|
|
|
*vpos -= fifo_lines + 1;
|
|
|
|
|
|
|
|
|
|
ret |= DRM_SCANOUTPOS_ACCURATE;
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Less: This happens when we are in vblank and the HVS, after getting
|
|
|
|
|
* the VSTART restart signal from the PV, just started refilling its
|
|
|
|
|
* fifo with new lines from the top-most lines of the new framebuffers.
|
|
|
|
|
* The PV does not scan out in vblank, so does not remove lines from
|
|
|
|
|
* the fifo, so the fifo will be full quickly and the HVS has to pause.
|
|
|
|
|
* We can't get meaningful readings wrt. scanline position of the PV
|
|
|
|
|
* and need to make things up in a approximative but consistent way.
|
|
|
|
|
*/
|
|
|
|
|
ret |= DRM_SCANOUTPOS_IN_VBLANK;
|
2016-09-28 18:30:25 -06:00
|
|
|
vblank_lines = mode->vtotal - mode->vdisplay;
|
drm/vc4: Implement precise vblank timestamping.
Precise vblank timestamping is implemented via the
usual scanout position based method. On VC4 the
pixelvalves PV do not have a scanout position
register. Only the hardware video scaler HVS has a
similar register which describes which scanline for
the output is currently composited and stored in the
HVS fifo for later consumption by the PV.
This causes a problem in that the HVS runs at a much
faster clock (system clock / audio gate) than the PV
which runs at video mode dot clock, so the unless the
fifo between HVS and PV is full, the HVS will progress
faster in its observable read line position than video
scan rate, so the HVS position reading can't be directly
translated into a scanout position for timestamp correction.
Additionally when the PV is in vblank, it doesn't consume
from the fifo, so the fifo gets full very quickly and then
the HVS stops compositing until the PV enters active scanout
and starts consuming scanlines from the fifo again, making
new space for the HVS to composite.
Therefore a simple translation of HVS read position into
elapsed time since (or to) start of active scanout does
not work, but for the most interesting cases we can still
get useful and sufficiently accurate results:
1. The PV enters active scanout of a new frame with the
fifo of the HVS completely full, and the HVS can refill
any fifo line which gets consumed and thereby freed up by
the PV during active scanout very quickly. Therefore the
PV and HVS work effectively in lock-step during active
scanout with the fifo never having more than 1 scanline
freed up by the PV before it gets refilled. The PV's
real scanout position is therefore trailing the HVS
compositing position as scanoutpos = hvspos - fifosize
and we can get the true scanoutpos as HVS readpos minus
fifo size, so precise timestamping works while in active
scanout, except for the last few scanlines of the frame,
when the HVS reaches end of frame, stops compositing and
the PV catches up and drains the fifo. This special case
would only introduce minor errors though.
2. If we are in vblank, then we can only guess something
reasonable. If called from vblank irq, we assume the irq is
usually dispatched with minimum delay, so we can take a
timestamp taken at entry into the vblank irq handler as a
baseline and then add a full vblank duration until the
guessed start of active scanout. As irq dispatch is usually
pretty low latency this works with relatively low jitter and
good results.
If we aren't called from vblank then we could be anywhere
within the vblank interval, so we return a neutral result,
simply the current system timestamp, and hope for the best.
Measurement shows the generated timestamps to be rather precise,
and at least never off more than 1 vblank duration worst-case.
Limitations: Doesn't work well yet for interlaced video modes,
therefore disabled in interlaced mode for now.
v2: Use the DISPBASE registers to determine the FIFO size (changes
by anholt)
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2)
2016-06-23 00:17:50 -06:00
|
|
|
|
|
|
|
|
if (flags & DRM_CALLED_FROM_VBLIRQ) {
|
|
|
|
|
/*
|
|
|
|
|
* Assume the irq handler got called close to first
|
|
|
|
|
* line of vblank, so PV has about a full vblank
|
|
|
|
|
* scanlines to go, and as a base timestamp use the
|
|
|
|
|
* one taken at entry into vblank irq handler, so it
|
|
|
|
|
* is not affected by random delays due to lock
|
|
|
|
|
* contention on event_lock or vblank_time lock in
|
|
|
|
|
* the core.
|
|
|
|
|
*/
|
|
|
|
|
*vpos = -vblank_lines;
|
|
|
|
|
|
|
|
|
|
if (stime)
|
|
|
|
|
*stime = vc4_crtc->t_vblank;
|
|
|
|
|
if (etime)
|
|
|
|
|
*etime = vc4_crtc->t_vblank;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* If the HVS fifo is not yet full then we know for certain
|
|
|
|
|
* we are at the very beginning of vblank, as the hvs just
|
|
|
|
|
* started refilling, and the stime and etime timestamps
|
|
|
|
|
* truly correspond to start of vblank.
|
|
|
|
|
*/
|
|
|
|
|
if ((val & SCALER_DISPSTATX_FULL) != SCALER_DISPSTATX_FULL)
|
|
|
|
|
ret |= DRM_SCANOUTPOS_ACCURATE;
|
|
|
|
|
} else {
|
|
|
|
|
/*
|
|
|
|
|
* No clue where we are inside vblank. Return a vpos of zero,
|
|
|
|
|
* which will cause calling code to just return the etime
|
|
|
|
|
* timestamp uncorrected. At least this is no worse than the
|
|
|
|
|
* standard fallback.
|
|
|
|
|
*/
|
|
|
|
|
*vpos = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
|
|
|
|
|
int *max_error, struct timeval *vblank_time,
|
|
|
|
|
unsigned flags)
|
|
|
|
|
{
|
2017-01-09 04:25:45 -07:00
|
|
|
struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
|
drm/vc4: Implement precise vblank timestamping.
Precise vblank timestamping is implemented via the
usual scanout position based method. On VC4 the
pixelvalves PV do not have a scanout position
register. Only the hardware video scaler HVS has a
similar register which describes which scanline for
the output is currently composited and stored in the
HVS fifo for later consumption by the PV.
This causes a problem in that the HVS runs at a much
faster clock (system clock / audio gate) than the PV
which runs at video mode dot clock, so the unless the
fifo between HVS and PV is full, the HVS will progress
faster in its observable read line position than video
scan rate, so the HVS position reading can't be directly
translated into a scanout position for timestamp correction.
Additionally when the PV is in vblank, it doesn't consume
from the fifo, so the fifo gets full very quickly and then
the HVS stops compositing until the PV enters active scanout
and starts consuming scanlines from the fifo again, making
new space for the HVS to composite.
Therefore a simple translation of HVS read position into
elapsed time since (or to) start of active scanout does
not work, but for the most interesting cases we can still
get useful and sufficiently accurate results:
1. The PV enters active scanout of a new frame with the
fifo of the HVS completely full, and the HVS can refill
any fifo line which gets consumed and thereby freed up by
the PV during active scanout very quickly. Therefore the
PV and HVS work effectively in lock-step during active
scanout with the fifo never having more than 1 scanline
freed up by the PV before it gets refilled. The PV's
real scanout position is therefore trailing the HVS
compositing position as scanoutpos = hvspos - fifosize
and we can get the true scanoutpos as HVS readpos minus
fifo size, so precise timestamping works while in active
scanout, except for the last few scanlines of the frame,
when the HVS reaches end of frame, stops compositing and
the PV catches up and drains the fifo. This special case
would only introduce minor errors though.
2. If we are in vblank, then we can only guess something
reasonable. If called from vblank irq, we assume the irq is
usually dispatched with minimum delay, so we can take a
timestamp taken at entry into the vblank irq handler as a
baseline and then add a full vblank duration until the
guessed start of active scanout. As irq dispatch is usually
pretty low latency this works with relatively low jitter and
good results.
If we aren't called from vblank then we could be anywhere
within the vblank interval, so we return a neutral result,
simply the current system timestamp, and hope for the best.
Measurement shows the generated timestamps to be rather precise,
and at least never off more than 1 vblank duration worst-case.
Limitations: Doesn't work well yet for interlaced video modes,
therefore disabled in interlaced mode for now.
v2: Use the DISPBASE registers to determine the FIFO size (changes
by anholt)
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2)
2016-06-23 00:17:50 -06:00
|
|
|
struct drm_crtc_state *state = crtc->state;
|
|
|
|
|
|
|
|
|
|
/* Helper routine in DRM core does all the work: */
|
|
|
|
|
return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc_id, max_error,
|
|
|
|
|
vblank_time, flags,
|
|
|
|
|
&state->adjusted_mode);
|
|
|
|
|
}
|
|
|
|
|
|
2015-03-02 14:01:12 -07:00
|
|
|
static void vc4_crtc_destroy(struct drm_crtc *crtc)
|
|
|
|
|
{
|
|
|
|
|
drm_crtc_cleanup(crtc);
|
|
|
|
|
}
|
|
|
|
|
|
2016-03-31 19:38:20 -06:00
|
|
|
static void
|
|
|
|
|
vc4_crtc_lut_load(struct drm_crtc *crtc)
|
|
|
|
|
{
|
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
|
|
|
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
|
|
|
|
|
u32 i;
|
|
|
|
|
|
|
|
|
|
/* The LUT memory is laid out with each HVS channel in order,
|
|
|
|
|
* each of which takes 256 writes for R, 256 for G, then 256
|
|
|
|
|
* for B.
|
|
|
|
|
*/
|
|
|
|
|
HVS_WRITE(SCALER_GAMADDR,
|
|
|
|
|
SCALER_GAMADDR_AUTOINC |
|
|
|
|
|
(vc4_crtc->channel * 3 * crtc->gamma_size));
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < crtc->gamma_size; i++)
|
|
|
|
|
HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
|
|
|
|
|
for (i = 0; i < crtc->gamma_size; i++)
|
|
|
|
|
HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
|
|
|
|
|
for (i = 0; i < crtc->gamma_size; i++)
|
|
|
|
|
HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
|
|
|
|
|
}
|
|
|
|
|
|
2016-06-07 04:49:30 -06:00
|
|
|
static int
|
2016-03-31 19:38:20 -06:00
|
|
|
vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
|
2016-06-07 04:49:30 -06:00
|
|
|
uint32_t size)
|
2016-03-31 19:38:20 -06:00
|
|
|
{
|
|
|
|
|
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
|
|
|
|
|
u32 i;
|
|
|
|
|
|
2016-06-07 04:49:30 -06:00
|
|
|
for (i = 0; i < size; i++) {
|
2016-03-31 19:38:20 -06:00
|
|
|
vc4_crtc->lut_r[i] = r[i] >> 8;
|
|
|
|
|
vc4_crtc->lut_g[i] = g[i] >> 8;
|
|
|
|
|
vc4_crtc->lut_b[i] = b[i] >> 8;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
vc4_crtc_lut_load(crtc);
|
2016-06-07 04:49:30 -06:00
|
|
|
|
|
|
|
|
return 0;
|
2016-03-31 19:38:20 -06:00
|
|
|
}
|
|
|
|
|
|
2015-03-02 14:01:12 -07:00
|
|
|
static u32 vc4_get_fifo_full_level(u32 format)
|
|
|
|
|
{
|
|
|
|
|
static const u32 fifo_len_bytes = 64;
|
|
|
|
|
static const u32 hvs_latency_pix = 6;
|
|
|
|
|
|
|
|
|
|
switch (format) {
|
|
|
|
|
case PV_CONTROL_FORMAT_DSIV_16:
|
|
|
|
|
case PV_CONTROL_FORMAT_DSIC_16:
|
|
|
|
|
return fifo_len_bytes - 2 * hvs_latency_pix;
|
|
|
|
|
case PV_CONTROL_FORMAT_DSIV_18:
|
|
|
|
|
return fifo_len_bytes - 14;
|
|
|
|
|
case PV_CONTROL_FORMAT_24:
|
|
|
|
|
case PV_CONTROL_FORMAT_DSIV_24:
|
|
|
|
|
default:
|
|
|
|
|
return fifo_len_bytes - 3 * hvs_latency_pix;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Returns the clock select bit for the connector attached to the
|
|
|
|
|
* CRTC.
|
|
|
|
|
*/
|
|
|
|
|
static int vc4_get_clock_select(struct drm_crtc *crtc)
|
|
|
|
|
{
|
|
|
|
|
struct drm_connector *connector;
|
|
|
|
|
|
|
|
|
|
drm_for_each_connector(connector, crtc->dev) {
|
2015-10-22 23:38:00 -06:00
|
|
|
if (connector->state->crtc == crtc) {
|
2015-03-02 14:01:12 -07:00
|
|
|
struct drm_encoder *encoder = connector->encoder;
|
|
|
|
|
struct vc4_encoder *vc4_encoder =
|
|
|
|
|
to_vc4_encoder(encoder);
|
|
|
|
|
|
|
|
|
|
return vc4_encoder->clock_select;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
|
|
|
|
|
{
|
2016-02-16 11:24:08 -07:00
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
2015-03-02 14:01:12 -07:00
|
|
|
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
|
|
|
|
|
struct drm_crtc_state *state = crtc->state;
|
|
|
|
|
struct drm_display_mode *mode = &state->adjusted_mode;
|
|
|
|
|
bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
|
2016-09-29 16:34:44 -06:00
|
|
|
u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
|
2015-03-02 14:01:12 -07:00
|
|
|
u32 format = PV_CONTROL_FORMAT_24;
|
|
|
|
|
bool debug_dump_regs = false;
|
|
|
|
|
int clock_select = vc4_get_clock_select(crtc);
|
|
|
|
|
|
|
|
|
|
if (debug_dump_regs) {
|
|
|
|
|
DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
|
|
|
|
|
vc4_crtc_dump_regs(vc4_crtc);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Reset the PV fifo. */
|
|
|
|
|
CRTC_WRITE(PV_CONTROL, 0);
|
|
|
|
|
CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
|
|
|
|
|
CRTC_WRITE(PV_CONTROL, 0);
|
|
|
|
|
|
|
|
|
|
CRTC_WRITE(PV_HORZA,
|
2016-09-29 16:34:44 -06:00
|
|
|
VC4_SET_FIELD((mode->htotal -
|
|
|
|
|
mode->hsync_end) * pixel_rep,
|
2015-03-02 14:01:12 -07:00
|
|
|
PV_HORZA_HBP) |
|
2016-09-29 16:34:44 -06:00
|
|
|
VC4_SET_FIELD((mode->hsync_end -
|
|
|
|
|
mode->hsync_start) * pixel_rep,
|
2015-03-02 14:01:12 -07:00
|
|
|
PV_HORZA_HSYNC));
|
|
|
|
|
CRTC_WRITE(PV_HORZB,
|
2016-09-29 16:34:44 -06:00
|
|
|
VC4_SET_FIELD((mode->hsync_start -
|
|
|
|
|
mode->hdisplay) * pixel_rep,
|
2015-03-02 14:01:12 -07:00
|
|
|
PV_HORZB_HFP) |
|
2016-09-29 16:34:44 -06:00
|
|
|
VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
|
2015-03-02 14:01:12 -07:00
|
|
|
|
2016-02-15 18:31:41 -07:00
|
|
|
CRTC_WRITE(PV_VERTA,
|
2016-09-28 18:30:25 -06:00
|
|
|
VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
|
2016-02-15 18:31:41 -07:00
|
|
|
PV_VERTA_VBP) |
|
2016-09-28 18:30:25 -06:00
|
|
|
VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
|
2016-02-15 18:31:41 -07:00
|
|
|
PV_VERTA_VSYNC));
|
|
|
|
|
CRTC_WRITE(PV_VERTB,
|
2016-09-28 18:30:25 -06:00
|
|
|
VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
|
2016-02-15 18:31:41 -07:00
|
|
|
PV_VERTB_VFP) |
|
2016-09-28 18:30:25 -06:00
|
|
|
VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
|
2016-02-15 18:31:41 -07:00
|
|
|
|
2015-03-02 14:01:12 -07:00
|
|
|
if (interlace) {
|
|
|
|
|
CRTC_WRITE(PV_VERTA_EVEN,
|
2016-09-28 18:30:25 -06:00
|
|
|
VC4_SET_FIELD(mode->crtc_vtotal -
|
|
|
|
|
mode->crtc_vsync_end - 1,
|
2015-03-02 14:01:12 -07:00
|
|
|
PV_VERTA_VBP) |
|
2016-09-28 18:30:25 -06:00
|
|
|
VC4_SET_FIELD(mode->crtc_vsync_end -
|
|
|
|
|
mode->crtc_vsync_start,
|
2015-03-02 14:01:12 -07:00
|
|
|
PV_VERTA_VSYNC));
|
|
|
|
|
CRTC_WRITE(PV_VERTB_EVEN,
|
2016-09-28 18:30:25 -06:00
|
|
|
VC4_SET_FIELD(mode->crtc_vsync_start -
|
|
|
|
|
mode->crtc_vdisplay,
|
2015-03-02 14:01:12 -07:00
|
|
|
PV_VERTB_VFP) |
|
2016-09-28 18:30:25 -06:00
|
|
|
VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
|
|
|
|
|
|
|
|
|
|
/* We set up first field even mode for HDMI. VEC's
|
|
|
|
|
* NTSC mode would want first field odd instead, once
|
|
|
|
|
* we support it (to do so, set ODD_FIRST and put the
|
|
|
|
|
* delay in VSYNCD_EVEN instead).
|
|
|
|
|
*/
|
|
|
|
|
CRTC_WRITE(PV_V_CONTROL,
|
|
|
|
|
PV_VCONTROL_CONTINUOUS |
|
|
|
|
|
PV_VCONTROL_INTERLACE |
|
2016-09-29 16:34:44 -06:00
|
|
|
VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
|
2016-09-28 18:30:25 -06:00
|
|
|
PV_VCONTROL_ODD_DELAY));
|
|
|
|
|
CRTC_WRITE(PV_VSYNCD_EVEN, 0);
|
|
|
|
|
} else {
|
|
|
|
|
CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS);
|
2015-03-02 14:01:12 -07:00
|
|
|
}
|
|
|
|
|
|
2016-09-29 16:34:44 -06:00
|
|
|
CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
|
2015-03-02 14:01:12 -07:00
|
|
|
|
|
|
|
|
|
|
|
|
|
CRTC_WRITE(PV_CONTROL,
|
|
|
|
|
VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
|
|
|
|
|
VC4_SET_FIELD(vc4_get_fifo_full_level(format),
|
|
|
|
|
PV_CONTROL_FIFO_LEVEL) |
|
2016-09-29 16:34:44 -06:00
|
|
|
VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
|
2015-03-02 14:01:12 -07:00
|
|
|
PV_CONTROL_CLR_AT_START |
|
|
|
|
|
PV_CONTROL_TRIGGER_UNDERFLOW |
|
|
|
|
|
PV_CONTROL_WAIT_HSTART |
|
|
|
|
|
VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) |
|
|
|
|
|
PV_CONTROL_FIFO_CLR |
|
|
|
|
|
PV_CONTROL_EN);
|
|
|
|
|
|
2016-02-16 11:24:08 -07:00
|
|
|
HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
|
|
|
|
|
SCALER_DISPBKGND_AUTOHS |
|
2016-03-31 19:38:20 -06:00
|
|
|
SCALER_DISPBKGND_GAMMA |
|
2016-02-16 11:24:08 -07:00
|
|
|
(interlace ? SCALER_DISPBKGND_INTERLACE : 0));
|
|
|
|
|
|
2016-03-31 19:38:20 -06:00
|
|
|
/* Reload the LUT, since the SRAMs would have been disabled if
|
|
|
|
|
* all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
|
|
|
|
|
*/
|
|
|
|
|
vc4_crtc_lut_load(crtc);
|
|
|
|
|
|
2015-03-02 14:01:12 -07:00
|
|
|
if (debug_dump_regs) {
|
|
|
|
|
DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
|
|
|
|
|
vc4_crtc_dump_regs(vc4_crtc);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void require_hvs_enabled(struct drm_device *dev)
|
|
|
|
|
{
|
|
|
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
|
|
|
|
|
|
|
|
WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
|
|
|
|
|
SCALER_DISPCTRL_ENABLE);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void vc4_crtc_disable(struct drm_crtc *crtc)
|
|
|
|
|
{
|
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
|
|
|
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
|
|
|
|
|
u32 chan = vc4_crtc->channel;
|
|
|
|
|
int ret;
|
|
|
|
|
require_hvs_enabled(dev);
|
|
|
|
|
|
2016-07-19 12:59:01 -06:00
|
|
|
/* Disable vblank irq handling before crtc is disabled. */
|
|
|
|
|
drm_crtc_vblank_off(crtc);
|
|
|
|
|
|
2015-03-02 14:01:12 -07:00
|
|
|
CRTC_WRITE(PV_V_CONTROL,
|
|
|
|
|
CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
|
|
|
|
|
ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
|
|
|
|
|
WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
|
|
|
|
|
|
|
|
|
|
if (HVS_READ(SCALER_DISPCTRLX(chan)) &
|
|
|
|
|
SCALER_DISPCTRLX_ENABLE) {
|
|
|
|
|
HVS_WRITE(SCALER_DISPCTRLX(chan),
|
|
|
|
|
SCALER_DISPCTRLX_RESET);
|
|
|
|
|
|
|
|
|
|
/* While the docs say that reset is self-clearing, it
|
|
|
|
|
* seems it doesn't actually.
|
|
|
|
|
*/
|
|
|
|
|
HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Once we leave, the scaler should be disabled and its fifo empty. */
|
|
|
|
|
|
|
|
|
|
WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
|
|
|
|
|
|
|
|
|
|
WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
|
|
|
|
|
SCALER_DISPSTATX_MODE) !=
|
|
|
|
|
SCALER_DISPSTATX_MODE_DISABLED);
|
|
|
|
|
|
|
|
|
|
WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
|
|
|
|
|
(SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
|
|
|
|
|
SCALER_DISPSTATX_EMPTY);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void vc4_crtc_enable(struct drm_crtc *crtc)
|
|
|
|
|
{
|
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
|
|
|
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
|
|
|
|
|
struct drm_crtc_state *state = crtc->state;
|
|
|
|
|
struct drm_display_mode *mode = &state->adjusted_mode;
|
|
|
|
|
|
|
|
|
|
require_hvs_enabled(dev);
|
|
|
|
|
|
|
|
|
|
/* Turn on the scaler, which will wait for vstart to start
|
|
|
|
|
* compositing.
|
|
|
|
|
*/
|
|
|
|
|
HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
|
|
|
|
|
VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
|
|
|
|
|
VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
|
|
|
|
|
SCALER_DISPCTRLX_ENABLE);
|
|
|
|
|
|
|
|
|
|
/* Turn on the pixel valve, which will emit the vstart signal. */
|
|
|
|
|
CRTC_WRITE(PV_V_CONTROL,
|
|
|
|
|
CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
|
2016-07-19 12:59:01 -06:00
|
|
|
|
|
|
|
|
/* Enable vblank irq handling after crtc is started. */
|
|
|
|
|
drm_crtc_vblank_on(crtc);
|
2015-03-02 14:01:12 -07:00
|
|
|
}
|
|
|
|
|
|
2016-07-19 12:58:58 -06:00
|
|
|
static bool vc4_crtc_mode_fixup(struct drm_crtc *crtc,
|
|
|
|
|
const struct drm_display_mode *mode,
|
|
|
|
|
struct drm_display_mode *adjusted_mode)
|
|
|
|
|
{
|
2016-07-19 12:58:59 -06:00
|
|
|
/* Do not allow doublescan modes from user space */
|
|
|
|
|
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
|
|
|
|
|
DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
|
|
|
|
|
crtc->base.id);
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2016-07-19 12:58:58 -06:00
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2015-03-02 14:01:12 -07:00
|
|
|
static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
|
|
|
|
|
struct drm_crtc_state *state)
|
|
|
|
|
{
|
2015-12-28 14:25:41 -07:00
|
|
|
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
|
2015-03-02 14:01:12 -07:00
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
|
|
|
struct drm_plane *plane;
|
2015-12-28 14:25:41 -07:00
|
|
|
unsigned long flags;
|
2016-06-02 08:21:44 -06:00
|
|
|
const struct drm_plane_state *plane_state;
|
2015-03-02 14:01:12 -07:00
|
|
|
u32 dlist_count = 0;
|
2015-12-28 14:25:41 -07:00
|
|
|
int ret;
|
2015-03-02 14:01:12 -07:00
|
|
|
|
|
|
|
|
/* The pixelvalve can only feed one encoder (and encoders are
|
|
|
|
|
* 1:1 with connectors.)
|
|
|
|
|
*/
|
2016-01-04 04:53:20 -07:00
|
|
|
if (hweight32(state->connector_mask) > 1)
|
2015-03-02 14:01:12 -07:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
2016-06-02 08:21:44 -06:00
|
|
|
drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
|
2015-03-02 14:01:12 -07:00
|
|
|
dlist_count += vc4_plane_dlist_size(plane_state);
|
|
|
|
|
|
|
|
|
|
dlist_count++; /* Account for SCALER_CTL0_END. */
|
|
|
|
|
|
2015-12-28 14:25:41 -07:00
|
|
|
spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
|
|
|
|
|
ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
|
|
|
|
|
dlist_count, 1, 0);
|
|
|
|
|
spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
|
|
|
|
|
if (ret)
|
|
|
|
|
return ret;
|
2015-03-02 14:01:12 -07:00
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
|
|
|
|
|
struct drm_crtc_state *old_state)
|
|
|
|
|
{
|
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
|
|
|
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
|
2015-12-28 14:25:41 -07:00
|
|
|
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
|
2015-03-02 14:01:12 -07:00
|
|
|
struct drm_plane *plane;
|
|
|
|
|
bool debug_dump_regs = false;
|
2015-12-28 14:25:41 -07:00
|
|
|
u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
|
|
|
|
|
u32 __iomem *dlist_next = dlist_start;
|
2015-03-02 14:01:12 -07:00
|
|
|
|
|
|
|
|
if (debug_dump_regs) {
|
|
|
|
|
DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
|
|
|
|
|
vc4_hvs_dump_state(dev);
|
|
|
|
|
}
|
|
|
|
|
|
2015-12-28 14:25:41 -07:00
|
|
|
/* Copy all the active planes' dlist contents to the hardware dlist. */
|
2015-03-02 14:01:12 -07:00
|
|
|
drm_atomic_crtc_for_each_plane(plane, crtc) {
|
|
|
|
|
dlist_next += vc4_plane_write_dlist(plane, dlist_next);
|
|
|
|
|
}
|
|
|
|
|
|
2015-12-28 14:25:41 -07:00
|
|
|
writel(SCALER_CTL0_END, dlist_next);
|
|
|
|
|
dlist_next++;
|
|
|
|
|
|
|
|
|
|
WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
|
|
|
|
|
|
2015-03-02 14:01:12 -07:00
|
|
|
if (crtc->state->event) {
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
crtc->state->event->pipe = drm_crtc_index(crtc);
|
|
|
|
|
|
|
|
|
|
WARN_ON(drm_crtc_vblank_get(crtc) != 0);
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
|
|
|
vc4_crtc->event = crtc->state->event;
|
|
|
|
|
crtc->state->event = NULL;
|
drm/vc4: Make pageflip completion handling more robust.
Protect both the setup of the pageflip event and the
latching of the new requested displaylist head pointer
by the event lock, so we can't get into a situation
where vc4_atomic_flush latches the new display list via
HVS_WRITE, then immediately gets preempted before queueing
the pageflip event, then the page-flip completes in hw and
the vc4_crtc_handle_page_flip() runs and no-ops due to
lack of a pending pageflip event, then vc4_atomic_flush
continues and only then queues the pageflip event - after
the page flip handling already no-oped. This would cause
flip completion handling only at the next vblank - one
frame too late.
In vc4_crtc_handle_page_flip() check the actual DL head
pointer in SCALER_DISPLACTX against the requested pointer
for page flip to make sure that the flip actually really
completed in the current vblank and doesn't get deferred
to the next one because the DL head pointer was written
a bit too late into SCALER_DISPLISTX, after start of
vblank, and missed the boat. This avoids handling a
pageflip completion too early - one frame too early.
According to Eric, DL head pointer updates which were
written into the HVS DISPLISTX reg get committed to hardware
at the last pixel of active scanout. Our vblank interrupt
handler, as triggered by PV_INT_VFP_START irq, gets to run
earliest at the first pixel of HBLANK at the end of the
last scanline of active scanout, ie. vblank irq handling
runs at least 1 pixel duration after a potential pageflip
completion happened in hardware.
This ordering of events in the hardware, together with the
lock protection and SCALER_DISPLACTX sampling of this patch,
guarantees that pageflip completion handling only runs at
exactly the vblank irq of actual pageflip completion in all
cases.
Background info from Eric about the relative timing of
HVS, PV's and trigger points for interrupts, DL updates:
https://lists.freedesktop.org/archives/dri-devel/2016-May/107510.html
Tested on RPi 2B with hardware timing measurement equipment
and shown to no longer complete flips too early or too late.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-05-18 06:02:46 -06:00
|
|
|
|
|
|
|
|
HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
|
|
|
|
|
vc4_state->mm.start);
|
|
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
|
} else {
|
|
|
|
|
HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
|
|
|
|
|
vc4_state->mm.start);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (debug_dump_regs) {
|
|
|
|
|
DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
|
|
|
|
|
vc4_hvs_dump_state(dev);
|
2015-03-02 14:01:12 -07:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-21 18:23:31 -06:00
|
|
|
int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id)
|
2015-03-02 14:01:12 -07:00
|
|
|
{
|
2017-01-09 04:25:45 -07:00
|
|
|
struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
|
|
|
|
|
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
|
2015-03-02 14:01:12 -07:00
|
|
|
|
|
|
|
|
CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-21 18:23:31 -06:00
|
|
|
void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id)
|
2015-03-02 14:01:12 -07:00
|
|
|
{
|
2017-01-09 04:25:45 -07:00
|
|
|
struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
|
|
|
|
|
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
|
2015-03-02 14:01:12 -07:00
|
|
|
|
|
|
|
|
CRTC_WRITE(PV_INTEN, 0);
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-24 11:11:55 -07:00
|
|
|
/* Must be called with the event lock held */
|
|
|
|
|
bool vc4_event_pending(struct drm_crtc *crtc)
|
|
|
|
|
{
|
|
|
|
|
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
|
|
|
|
|
|
|
|
|
|
return !!vc4_crtc->event;
|
|
|
|
|
}
|
|
|
|
|
|
2015-03-02 14:01:12 -07:00
|
|
|
static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
|
|
|
|
|
{
|
|
|
|
|
struct drm_crtc *crtc = &vc4_crtc->base;
|
|
|
|
|
struct drm_device *dev = crtc->dev;
|
drm/vc4: Make pageflip completion handling more robust.
Protect both the setup of the pageflip event and the
latching of the new requested displaylist head pointer
by the event lock, so we can't get into a situation
where vc4_atomic_flush latches the new display list via
HVS_WRITE, then immediately gets preempted before queueing
the pageflip event, then the page-flip completes in hw and
the vc4_crtc_handle_page_flip() runs and no-ops due to
lack of a pending pageflip event, then vc4_atomic_flush
continues and only then queues the pageflip event - after
the page flip handling already no-oped. This would cause
flip completion handling only at the next vblank - one
frame too late.
In vc4_crtc_handle_page_flip() check the actual DL head
pointer in SCALER_DISPLACTX against the requested pointer
for page flip to make sure that the flip actually really
completed in the current vblank and doesn't get deferred
to the next one because the DL head pointer was written
a bit too late into SCALER_DISPLISTX, after start of
vblank, and missed the boat. This avoids handling a
pageflip completion too early - one frame too early.
According to Eric, DL head pointer updates which were
written into the HVS DISPLISTX reg get committed to hardware
at the last pixel of active scanout. Our vblank interrupt
handler, as triggered by PV_INT_VFP_START irq, gets to run
earliest at the first pixel of HBLANK at the end of the
last scanline of active scanout, ie. vblank irq handling
runs at least 1 pixel duration after a potential pageflip
completion happened in hardware.
This ordering of events in the hardware, together with the
lock protection and SCALER_DISPLACTX sampling of this patch,
guarantees that pageflip completion handling only runs at
exactly the vblank irq of actual pageflip completion in all
cases.
Background info from Eric about the relative timing of
HVS, PV's and trigger points for interrupts, DL updates:
https://lists.freedesktop.org/archives/dri-devel/2016-May/107510.html
Tested on RPi 2B with hardware timing measurement equipment
and shown to no longer complete flips too early or too late.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-05-18 06:02:46 -06:00
|
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
|
|
|
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
|
|
|
|
|
u32 chan = vc4_crtc->channel;
|
2015-03-02 14:01:12 -07:00
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
drm/vc4: Make pageflip completion handling more robust.
Protect both the setup of the pageflip event and the
latching of the new requested displaylist head pointer
by the event lock, so we can't get into a situation
where vc4_atomic_flush latches the new display list via
HVS_WRITE, then immediately gets preempted before queueing
the pageflip event, then the page-flip completes in hw and
the vc4_crtc_handle_page_flip() runs and no-ops due to
lack of a pending pageflip event, then vc4_atomic_flush
continues and only then queues the pageflip event - after
the page flip handling already no-oped. This would cause
flip completion handling only at the next vblank - one
frame too late.
In vc4_crtc_handle_page_flip() check the actual DL head
pointer in SCALER_DISPLACTX against the requested pointer
for page flip to make sure that the flip actually really
completed in the current vblank and doesn't get deferred
to the next one because the DL head pointer was written
a bit too late into SCALER_DISPLISTX, after start of
vblank, and missed the boat. This avoids handling a
pageflip completion too early - one frame too early.
According to Eric, DL head pointer updates which were
written into the HVS DISPLISTX reg get committed to hardware
at the last pixel of active scanout. Our vblank interrupt
handler, as triggered by PV_INT_VFP_START irq, gets to run
earliest at the first pixel of HBLANK at the end of the
last scanline of active scanout, ie. vblank irq handling
runs at least 1 pixel duration after a potential pageflip
completion happened in hardware.
This ordering of events in the hardware, together with the
lock protection and SCALER_DISPLACTX sampling of this patch,
guarantees that pageflip completion handling only runs at
exactly the vblank irq of actual pageflip completion in all
cases.
Background info from Eric about the relative timing of
HVS, PV's and trigger points for interrupts, DL updates:
https://lists.freedesktop.org/archives/dri-devel/2016-May/107510.html
Tested on RPi 2B with hardware timing measurement equipment
and shown to no longer complete flips too early or too late.
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-05-18 06:02:46 -06:00
|
|
|
if (vc4_crtc->event &&
|
|
|
|
|
(vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
|
2015-03-02 14:01:12 -07:00
|
|
|
drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
|
|
|
|
|
vc4_crtc->event = NULL;
|
2016-05-06 11:26:06 -06:00
|
|
|
drm_crtc_vblank_put(crtc);
|
2015-03-02 14:01:12 -07:00
|
|
|
}
|
|
|
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
|
|
|
|
|
{
|
|
|
|
|
struct vc4_crtc *vc4_crtc = data;
|
|
|
|
|
u32 stat = CRTC_READ(PV_INTSTAT);
|
|
|
|
|
irqreturn_t ret = IRQ_NONE;
|
|
|
|
|
|
|
|
|
|
if (stat & PV_INT_VFP_START) {
|
drm/vc4: Implement precise vblank timestamping.
Precise vblank timestamping is implemented via the
usual scanout position based method. On VC4 the
pixelvalves PV do not have a scanout position
register. Only the hardware video scaler HVS has a
similar register which describes which scanline for
the output is currently composited and stored in the
HVS fifo for later consumption by the PV.
This causes a problem in that the HVS runs at a much
faster clock (system clock / audio gate) than the PV
which runs at video mode dot clock, so the unless the
fifo between HVS and PV is full, the HVS will progress
faster in its observable read line position than video
scan rate, so the HVS position reading can't be directly
translated into a scanout position for timestamp correction.
Additionally when the PV is in vblank, it doesn't consume
from the fifo, so the fifo gets full very quickly and then
the HVS stops compositing until the PV enters active scanout
and starts consuming scanlines from the fifo again, making
new space for the HVS to composite.
Therefore a simple translation of HVS read position into
elapsed time since (or to) start of active scanout does
not work, but for the most interesting cases we can still
get useful and sufficiently accurate results:
1. The PV enters active scanout of a new frame with the
fifo of the HVS completely full, and the HVS can refill
any fifo line which gets consumed and thereby freed up by
the PV during active scanout very quickly. Therefore the
PV and HVS work effectively in lock-step during active
scanout with the fifo never having more than 1 scanline
freed up by the PV before it gets refilled. The PV's
real scanout position is therefore trailing the HVS
compositing position as scanoutpos = hvspos - fifosize
and we can get the true scanoutpos as HVS readpos minus
fifo size, so precise timestamping works while in active
scanout, except for the last few scanlines of the frame,
when the HVS reaches end of frame, stops compositing and
the PV catches up and drains the fifo. This special case
would only introduce minor errors though.
2. If we are in vblank, then we can only guess something
reasonable. If called from vblank irq, we assume the irq is
usually dispatched with minimum delay, so we can take a
timestamp taken at entry into the vblank irq handler as a
baseline and then add a full vblank duration until the
guessed start of active scanout. As irq dispatch is usually
pretty low latency this works with relatively low jitter and
good results.
If we aren't called from vblank then we could be anywhere
within the vblank interval, so we return a neutral result,
simply the current system timestamp, and hope for the best.
Measurement shows the generated timestamps to be rather precise,
and at least never off more than 1 vblank duration worst-case.
Limitations: Doesn't work well yet for interlaced video modes,
therefore disabled in interlaced mode for now.
v2: Use the DISPBASE registers to determine the FIFO size (changes
by anholt)
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2)
2016-06-23 00:17:50 -06:00
|
|
|
vc4_crtc->t_vblank = ktime_get();
|
2015-03-02 14:01:12 -07:00
|
|
|
CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
|
|
|
|
|
drm_crtc_handle_vblank(&vc4_crtc->base);
|
|
|
|
|
vc4_crtc_handle_page_flip(vc4_crtc);
|
|
|
|
|
ret = IRQ_HANDLED;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2015-11-30 13:34:01 -07:00
|
|
|
struct vc4_async_flip_state {
|
|
|
|
|
struct drm_crtc *crtc;
|
|
|
|
|
struct drm_framebuffer *fb;
|
|
|
|
|
struct drm_pending_vblank_event *event;
|
|
|
|
|
|
|
|
|
|
struct vc4_seqno_cb cb;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/* Called when the V3D execution for the BO being flipped to is done, so that
|
|
|
|
|
* we can actually update the plane's address to point to it.
|
|
|
|
|
*/
|
|
|
|
|
static void
|
|
|
|
|
vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
|
|
|
|
|
{
|
|
|
|
|
struct vc4_async_flip_state *flip_state =
|
|
|
|
|
container_of(cb, struct vc4_async_flip_state, cb);
|
|
|
|
|
struct drm_crtc *crtc = flip_state->crtc;
|
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
|
|
|
struct drm_plane *plane = crtc->primary;
|
|
|
|
|
|
|
|
|
|
vc4_plane_async_set_fb(plane, flip_state->fb);
|
|
|
|
|
if (flip_state->event) {
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&dev->event_lock, flags);
|
|
|
|
|
drm_crtc_send_vblank_event(crtc, flip_state->event);
|
|
|
|
|
spin_unlock_irqrestore(&dev->event_lock, flags);
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-06 11:26:06 -06:00
|
|
|
drm_crtc_vblank_put(crtc);
|
2015-11-30 13:34:01 -07:00
|
|
|
drm_framebuffer_unreference(flip_state->fb);
|
|
|
|
|
kfree(flip_state);
|
|
|
|
|
|
|
|
|
|
up(&vc4->async_modeset);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Implements async (non-vblank-synced) page flips.
|
|
|
|
|
*
|
|
|
|
|
* The page flip ioctl needs to return immediately, so we grab the
|
|
|
|
|
* modeset semaphore on the pipe, and queue the address update for
|
|
|
|
|
* when V3D is done with the BO being flipped to.
|
|
|
|
|
*/
|
|
|
|
|
static int vc4_async_page_flip(struct drm_crtc *crtc,
|
|
|
|
|
struct drm_framebuffer *fb,
|
|
|
|
|
struct drm_pending_vblank_event *event,
|
|
|
|
|
uint32_t flags)
|
|
|
|
|
{
|
|
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
|
|
struct vc4_dev *vc4 = to_vc4_dev(dev);
|
|
|
|
|
struct drm_plane *plane = crtc->primary;
|
|
|
|
|
int ret = 0;
|
|
|
|
|
struct vc4_async_flip_state *flip_state;
|
|
|
|
|
struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
|
|
|
|
|
struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
|
|
|
|
|
|
|
|
|
|
flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
|
|
|
|
|
if (!flip_state)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
|
|
drm_framebuffer_reference(fb);
|
|
|
|
|
flip_state->fb = fb;
|
|
|
|
|
flip_state->crtc = crtc;
|
|
|
|
|
flip_state->event = event;
|
|
|
|
|
|
|
|
|
|
/* Make sure all other async modesetes have landed. */
|
|
|
|
|
ret = down_interruptible(&vc4->async_modeset);
|
|
|
|
|
if (ret) {
|
2016-02-05 16:06:15 -07:00
|
|
|
drm_framebuffer_unreference(fb);
|
2015-11-30 13:34:01 -07:00
|
|
|
kfree(flip_state);
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-06 11:26:06 -06:00
|
|
|
WARN_ON(drm_crtc_vblank_get(crtc) != 0);
|
|
|
|
|
|
2015-11-30 13:34:01 -07:00
|
|
|
/* Immediately update the plane's legacy fb pointer, so that later
|
|
|
|
|
* modeset prep sees the state that will be present when the semaphore
|
|
|
|
|
* is released.
|
|
|
|
|
*/
|
|
|
|
|
drm_atomic_set_fb_for_plane(plane->state, fb);
|
|
|
|
|
plane->fb = fb;
|
|
|
|
|
|
|
|
|
|
vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
|
|
|
|
|
vc4_async_page_flip_complete);
|
|
|
|
|
|
|
|
|
|
/* Driver takes ownership of state on successful async commit. */
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int vc4_page_flip(struct drm_crtc *crtc,
|
|
|
|
|
struct drm_framebuffer *fb,
|
|
|
|
|
struct drm_pending_vblank_event *event,
|
|
|
|
|
uint32_t flags)
|
|
|
|
|
{
|
|
|
|
|
if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
|
|
|
|
|
return vc4_async_page_flip(crtc, fb, event, flags);
|
|
|
|
|
else
|
|
|
|
|
return drm_atomic_helper_page_flip(crtc, fb, event, flags);
|
|
|
|
|
}
|
|
|
|
|
|
2015-12-28 14:25:41 -07:00
|
|
|
static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
|
|
|
|
|
{
|
|
|
|
|
struct vc4_crtc_state *vc4_state;
|
|
|
|
|
|
|
|
|
|
vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
|
|
|
|
|
if (!vc4_state)
|
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
|
|
__drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
|
|
|
|
|
return &vc4_state->base;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
|
|
|
|
|
struct drm_crtc_state *state)
|
|
|
|
|
{
|
|
|
|
|
struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
|
|
|
|
|
struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
|
|
|
|
|
|
|
|
|
|
if (vc4_state->mm.allocated) {
|
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
|
|
spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
|
|
|
|
|
drm_mm_remove_node(&vc4_state->mm);
|
|
|
|
|
spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
2016-05-09 08:34:09 -06:00
|
|
|
__drm_atomic_helper_crtc_destroy_state(state);
|
2015-12-28 14:25:41 -07:00
|
|
|
}
|
|
|
|
|
|
2015-03-02 14:01:12 -07:00
|
|
|
static const struct drm_crtc_funcs vc4_crtc_funcs = {
|
|
|
|
|
.set_config = drm_atomic_helper_set_config,
|
|
|
|
|
.destroy = vc4_crtc_destroy,
|
2015-11-30 13:34:01 -07:00
|
|
|
.page_flip = vc4_page_flip,
|
2015-03-02 14:01:12 -07:00
|
|
|
.set_property = NULL,
|
|
|
|
|
.cursor_set = NULL, /* handled by drm_mode_cursor_universal */
|
|
|
|
|
.cursor_move = NULL, /* handled by drm_mode_cursor_universal */
|
|
|
|
|
.reset = drm_atomic_helper_crtc_reset,
|
2015-12-28 14:25:41 -07:00
|
|
|
.atomic_duplicate_state = vc4_crtc_duplicate_state,
|
|
|
|
|
.atomic_destroy_state = vc4_crtc_destroy_state,
|
2016-03-31 19:38:20 -06:00
|
|
|
.gamma_set = vc4_crtc_gamma_set,
|
2015-03-02 14:01:12 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
|
|
|
|
|
.mode_set_nofb = vc4_crtc_mode_set_nofb,
|
|
|
|
|
.disable = vc4_crtc_disable,
|
|
|
|
|
.enable = vc4_crtc_enable,
|
2016-07-19 12:58:58 -06:00
|
|
|
.mode_fixup = vc4_crtc_mode_fixup,
|
2015-03-02 14:01:12 -07:00
|
|
|
.atomic_check = vc4_crtc_atomic_check,
|
|
|
|
|
.atomic_flush = vc4_crtc_atomic_flush,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct vc4_crtc_data pv0_data = {
|
|
|
|
|
.hvs_channel = 0,
|
2016-12-02 06:48:07 -07:00
|
|
|
.encoder_types = {
|
|
|
|
|
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
|
|
|
|
|
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
|
|
|
|
|
},
|
2015-03-02 14:01:12 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct vc4_crtc_data pv1_data = {
|
|
|
|
|
.hvs_channel = 2,
|
2016-12-02 06:48:07 -07:00
|
|
|
.encoder_types = {
|
|
|
|
|
[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
|
|
|
|
|
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
|
|
|
|
|
},
|
2015-03-02 14:01:12 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct vc4_crtc_data pv2_data = {
|
|
|
|
|
.hvs_channel = 1,
|
2016-12-02 06:48:07 -07:00
|
|
|
.encoder_types = {
|
|
|
|
|
[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
|
|
|
|
|
[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
|
|
|
|
|
},
|
2015-03-02 14:01:12 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct of_device_id vc4_crtc_dt_match[] = {
|
|
|
|
|
{ .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
|
|
|
|
|
{ .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
|
|
|
|
|
{ .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
|
|
|
|
|
{}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static void vc4_set_crtc_possible_masks(struct drm_device *drm,
|
|
|
|
|
struct drm_crtc *crtc)
|
|
|
|
|
{
|
|
|
|
|
struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
|
2016-12-02 06:48:07 -07:00
|
|
|
const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
|
|
|
|
|
const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
|
2015-03-02 14:01:12 -07:00
|
|
|
struct drm_encoder *encoder;
|
|
|
|
|
|
|
|
|
|
drm_for_each_encoder(encoder, drm) {
|
|
|
|
|
struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
|
2016-12-02 06:48:07 -07:00
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
|
|
|
|
|
if (vc4_encoder->type == encoder_types[i]) {
|
|
|
|
|
vc4_encoder->clock_select = i;
|
|
|
|
|
encoder->possible_crtcs |= drm_crtc_mask(crtc);
|
|
|
|
|
break;
|
|
|
|
|
}
|
2015-03-02 14:01:12 -07:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
drm/vc4: Implement precise vblank timestamping.
Precise vblank timestamping is implemented via the
usual scanout position based method. On VC4 the
pixelvalves PV do not have a scanout position
register. Only the hardware video scaler HVS has a
similar register which describes which scanline for
the output is currently composited and stored in the
HVS fifo for later consumption by the PV.
This causes a problem in that the HVS runs at a much
faster clock (system clock / audio gate) than the PV
which runs at video mode dot clock, so the unless the
fifo between HVS and PV is full, the HVS will progress
faster in its observable read line position than video
scan rate, so the HVS position reading can't be directly
translated into a scanout position for timestamp correction.
Additionally when the PV is in vblank, it doesn't consume
from the fifo, so the fifo gets full very quickly and then
the HVS stops compositing until the PV enters active scanout
and starts consuming scanlines from the fifo again, making
new space for the HVS to composite.
Therefore a simple translation of HVS read position into
elapsed time since (or to) start of active scanout does
not work, but for the most interesting cases we can still
get useful and sufficiently accurate results:
1. The PV enters active scanout of a new frame with the
fifo of the HVS completely full, and the HVS can refill
any fifo line which gets consumed and thereby freed up by
the PV during active scanout very quickly. Therefore the
PV and HVS work effectively in lock-step during active
scanout with the fifo never having more than 1 scanline
freed up by the PV before it gets refilled. The PV's
real scanout position is therefore trailing the HVS
compositing position as scanoutpos = hvspos - fifosize
and we can get the true scanoutpos as HVS readpos minus
fifo size, so precise timestamping works while in active
scanout, except for the last few scanlines of the frame,
when the HVS reaches end of frame, stops compositing and
the PV catches up and drains the fifo. This special case
would only introduce minor errors though.
2. If we are in vblank, then we can only guess something
reasonable. If called from vblank irq, we assume the irq is
usually dispatched with minimum delay, so we can take a
timestamp taken at entry into the vblank irq handler as a
baseline and then add a full vblank duration until the
guessed start of active scanout. As irq dispatch is usually
pretty low latency this works with relatively low jitter and
good results.
If we aren't called from vblank then we could be anywhere
within the vblank interval, so we return a neutral result,
simply the current system timestamp, and hope for the best.
Measurement shows the generated timestamps to be rather precise,
and at least never off more than 1 vblank duration worst-case.
Limitations: Doesn't work well yet for interlaced video modes,
therefore disabled in interlaced mode for now.
v2: Use the DISPBASE registers to determine the FIFO size (changes
by anholt)
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2)
2016-06-23 00:17:50 -06:00
|
|
|
static void
|
|
|
|
|
vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
|
|
|
|
|
{
|
|
|
|
|
struct drm_device *drm = vc4_crtc->base.dev;
|
|
|
|
|
struct vc4_dev *vc4 = to_vc4_dev(drm);
|
|
|
|
|
u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
|
|
|
|
|
/* Top/base are supposed to be 4-pixel aligned, but the
|
|
|
|
|
* Raspberry Pi firmware fills the low bits (which are
|
|
|
|
|
* presumably ignored).
|
|
|
|
|
*/
|
|
|
|
|
u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
|
|
|
|
|
u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
|
|
|
|
|
|
|
|
|
|
vc4_crtc->cob_size = top - base + 4;
|
|
|
|
|
}
|
|
|
|
|
|
2015-03-02 14:01:12 -07:00
|
|
|
static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
|
|
|
|
|
{
|
|
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
|
struct drm_device *drm = dev_get_drvdata(master);
|
|
|
|
|
struct vc4_crtc *vc4_crtc;
|
|
|
|
|
struct drm_crtc *crtc;
|
2015-10-20 07:18:56 -06:00
|
|
|
struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
|
2015-03-02 14:01:12 -07:00
|
|
|
const struct of_device_id *match;
|
2015-10-20 07:18:56 -06:00
|
|
|
int ret, i;
|
2015-03-02 14:01:12 -07:00
|
|
|
|
|
|
|
|
vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
|
|
|
|
|
if (!vc4_crtc)
|
|
|
|
|
return -ENOMEM;
|
|
|
|
|
crtc = &vc4_crtc->base;
|
|
|
|
|
|
|
|
|
|
match = of_match_device(vc4_crtc_dt_match, dev);
|
|
|
|
|
if (!match)
|
|
|
|
|
return -ENODEV;
|
|
|
|
|
vc4_crtc->data = match->data;
|
|
|
|
|
|
|
|
|
|
vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
|
|
|
|
|
if (IS_ERR(vc4_crtc->regs))
|
|
|
|
|
return PTR_ERR(vc4_crtc->regs);
|
|
|
|
|
|
|
|
|
|
/* For now, we create just the primary and the legacy cursor
|
|
|
|
|
* planes. We should be able to stack more planes on easily,
|
|
|
|
|
* but to do that we would need to compute the bandwidth
|
|
|
|
|
* requirement of the plane configuration, and reject ones
|
|
|
|
|
* that will take too much.
|
|
|
|
|
*/
|
|
|
|
|
primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
|
2015-11-04 06:21:40 -07:00
|
|
|
if (IS_ERR(primary_plane)) {
|
2015-03-02 14:01:12 -07:00
|
|
|
dev_err(dev, "failed to construct primary plane\n");
|
|
|
|
|
ret = PTR_ERR(primary_plane);
|
|
|
|
|
goto err;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-20 07:18:56 -06:00
|
|
|
drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
|
drm: Pass 'name' to drm_crtc_init_with_planes()
Done with coccinelle for the most part. However, it thinks '...' is
part of the semantic patch, so I put an 'int DOTDOTDOT' placeholder
in its place and got rid of it with sed afterwards.
I didn't convert drm_crtc_init() since passing the varargs through
would mean either cpp macros or va_list, and I figured we don't
care about these legacy functions enough to warrant the extra pain.
@@
identifier dev, crtc, primary, cursor, funcs;
@@
int drm_crtc_init_with_planes(struct drm_device *dev,
struct drm_crtc *crtc,
struct drm_plane *primary, struct drm_plane *cursor,
const struct drm_crtc_funcs *funcs
+ ,const char *name, int DOTDOTDOT
)
{ ... }
@@
identifier dev, crtc, primary, cursor, funcs;
@@
int drm_crtc_init_with_planes(struct drm_device *dev,
struct drm_crtc *crtc,
struct drm_plane *primary, struct drm_plane *cursor,
const struct drm_crtc_funcs *funcs
+ ,const char *name, int DOTDOTDOT
);
@@
expression E1, E2, E3, E4, E5;
@@
drm_crtc_init_with_planes(E1, E2, E3, E4, E5
+ ,NULL
)
v2: Split crtc and plane changes apart
Pass NULL for no-name instead of ""
Leave drm_crtc_init() alone
v3: Add ', or NULL...' to @name kernel doc (Jani)
Annotate the function with __printf() attribute (Jani)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1449670771-2751-1-git-send-email-ville.syrjala@linux.intel.com
2015-12-09 07:19:31 -07:00
|
|
|
&vc4_crtc_funcs, NULL);
|
2015-03-02 14:01:12 -07:00
|
|
|
drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
|
|
|
|
|
primary_plane->crtc = crtc;
|
|
|
|
|
vc4_crtc->channel = vc4_crtc->data->hvs_channel;
|
2016-03-31 19:38:20 -06:00
|
|
|
drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
|
2015-03-02 14:01:12 -07:00
|
|
|
|
2015-10-20 07:18:56 -06:00
|
|
|
/* Set up some arbitrary number of planes. We're not limited
|
|
|
|
|
* by a set number of physical registers, just the space in
|
|
|
|
|
* the HVS (16k) and how small an plane can be (28 bytes).
|
|
|
|
|
* However, each plane we set up takes up some memory, and
|
|
|
|
|
* increases the cost of looping over planes, which atomic
|
|
|
|
|
* modesetting does quite a bit. As a result, we pick a
|
|
|
|
|
* modest number of planes to expose, that should hopefully
|
|
|
|
|
* still cover any sane usecase.
|
|
|
|
|
*/
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
|
struct drm_plane *plane =
|
|
|
|
|
vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
|
|
|
|
|
|
|
|
|
|
if (IS_ERR(plane))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
plane->possible_crtcs = 1 << drm_crtc_index(crtc);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Set up the legacy cursor after overlay initialization,
|
|
|
|
|
* since we overlay planes on the CRTC in the order they were
|
|
|
|
|
* initialized.
|
|
|
|
|
*/
|
|
|
|
|
cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
|
|
|
|
|
if (!IS_ERR(cursor_plane)) {
|
|
|
|
|
cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
|
|
|
|
|
cursor_plane->crtc = crtc;
|
|
|
|
|
crtc->cursor = cursor_plane;
|
|
|
|
|
}
|
|
|
|
|
|
drm/vc4: Implement precise vblank timestamping.
Precise vblank timestamping is implemented via the
usual scanout position based method. On VC4 the
pixelvalves PV do not have a scanout position
register. Only the hardware video scaler HVS has a
similar register which describes which scanline for
the output is currently composited and stored in the
HVS fifo for later consumption by the PV.
This causes a problem in that the HVS runs at a much
faster clock (system clock / audio gate) than the PV
which runs at video mode dot clock, so the unless the
fifo between HVS and PV is full, the HVS will progress
faster in its observable read line position than video
scan rate, so the HVS position reading can't be directly
translated into a scanout position for timestamp correction.
Additionally when the PV is in vblank, it doesn't consume
from the fifo, so the fifo gets full very quickly and then
the HVS stops compositing until the PV enters active scanout
and starts consuming scanlines from the fifo again, making
new space for the HVS to composite.
Therefore a simple translation of HVS read position into
elapsed time since (or to) start of active scanout does
not work, but for the most interesting cases we can still
get useful and sufficiently accurate results:
1. The PV enters active scanout of a new frame with the
fifo of the HVS completely full, and the HVS can refill
any fifo line which gets consumed and thereby freed up by
the PV during active scanout very quickly. Therefore the
PV and HVS work effectively in lock-step during active
scanout with the fifo never having more than 1 scanline
freed up by the PV before it gets refilled. The PV's
real scanout position is therefore trailing the HVS
compositing position as scanoutpos = hvspos - fifosize
and we can get the true scanoutpos as HVS readpos minus
fifo size, so precise timestamping works while in active
scanout, except for the last few scanlines of the frame,
when the HVS reaches end of frame, stops compositing and
the PV catches up and drains the fifo. This special case
would only introduce minor errors though.
2. If we are in vblank, then we can only guess something
reasonable. If called from vblank irq, we assume the irq is
usually dispatched with minimum delay, so we can take a
timestamp taken at entry into the vblank irq handler as a
baseline and then add a full vblank duration until the
guessed start of active scanout. As irq dispatch is usually
pretty low latency this works with relatively low jitter and
good results.
If we aren't called from vblank then we could be anywhere
within the vblank interval, so we return a neutral result,
simply the current system timestamp, and hope for the best.
Measurement shows the generated timestamps to be rather precise,
and at least never off more than 1 vblank duration worst-case.
Limitations: Doesn't work well yet for interlaced video modes,
therefore disabled in interlaced mode for now.
v2: Use the DISPBASE registers to determine the FIFO size (changes
by anholt)
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2)
2016-06-23 00:17:50 -06:00
|
|
|
vc4_crtc_get_cob_allocation(vc4_crtc);
|
|
|
|
|
|
2015-03-02 14:01:12 -07:00
|
|
|
CRTC_WRITE(PV_INTEN, 0);
|
|
|
|
|
CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
|
|
|
|
|
ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
|
|
|
|
|
vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
|
|
|
|
|
if (ret)
|
2015-10-20 07:18:56 -06:00
|
|
|
goto err_destroy_planes;
|
2015-03-02 14:01:12 -07:00
|
|
|
|
|
|
|
|
vc4_set_crtc_possible_masks(drm, crtc);
|
|
|
|
|
|
2016-03-31 19:38:20 -06:00
|
|
|
for (i = 0; i < crtc->gamma_size; i++) {
|
|
|
|
|
vc4_crtc->lut_r[i] = i;
|
|
|
|
|
vc4_crtc->lut_g[i] = i;
|
|
|
|
|
vc4_crtc->lut_b[i] = i;
|
|
|
|
|
}
|
|
|
|
|
|
2015-03-02 14:01:12 -07:00
|
|
|
platform_set_drvdata(pdev, vc4_crtc);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
2015-10-20 07:18:56 -06:00
|
|
|
err_destroy_planes:
|
|
|
|
|
list_for_each_entry_safe(destroy_plane, temp,
|
|
|
|
|
&drm->mode_config.plane_list, head) {
|
|
|
|
|
if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
|
|
|
|
|
destroy_plane->funcs->destroy(destroy_plane);
|
|
|
|
|
}
|
2015-03-02 14:01:12 -07:00
|
|
|
err:
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void vc4_crtc_unbind(struct device *dev, struct device *master,
|
|
|
|
|
void *data)
|
|
|
|
|
{
|
|
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
|
struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
|
|
vc4_crtc_destroy(&vc4_crtc->base);
|
|
|
|
|
|
|
|
|
|
CRTC_WRITE(PV_INTEN, 0);
|
|
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static const struct component_ops vc4_crtc_ops = {
|
|
|
|
|
.bind = vc4_crtc_bind,
|
|
|
|
|
.unbind = vc4_crtc_unbind,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int vc4_crtc_dev_probe(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
return component_add(&pdev->dev, &vc4_crtc_ops);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int vc4_crtc_dev_remove(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
component_del(&pdev->dev, &vc4_crtc_ops);
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
struct platform_driver vc4_crtc_driver = {
|
|
|
|
|
.probe = vc4_crtc_dev_probe,
|
|
|
|
|
.remove = vc4_crtc_dev_remove,
|
|
|
|
|
.driver = {
|
|
|
|
|
.name = "vc4_crtc",
|
|
|
|
|
.of_match_table = vc4_crtc_dt_match,
|
|
|
|
|
},
|
|
|
|
|
};
|