This patch increase the DPU single pipe maximum from 1920 to 2560 for
both the DPU common and HDMI/DP.
Signed-off-by: Oliver F. Brown <oliver.brown@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
This patch adds helper disengcfg_sig_select() support so that
users may select different taps(FrameGen, GammaCor, Matrix or
Dither) to do signature computation. Also, select FrameGen as
the default tap in _dpu_dec_init() and call it in dpu_dec_init().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
This patch adds signature unit support in the dpu common driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
It would be good to check of_match_device() return value in dpu_probe()
in case it returns a NULL pointer. This may avoid NULL pointer dereference
from happening.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Sandor Yu <sandor.yu@nxp.com>
The dpu common driver creates a irq chip for dpu irqs.
The parent of the irq chip on the i.MX8qm/qxp SoC is the irqsteer.
Since the irqsteer driver may support runtime PM, the dpu common
driver needs to call irq_chip_pm_get/put() where necessary to make
sure power of the irq chip is enabled/disabled properly. This
patch enables the power at the driver probe stage and disables it
at driver remove stage to achieve basic power management support
for the irq chip.
Suggested-by: Andy Duan <fugang.duan@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
After attach multiple power domains, these power domains are
power on since the state is DL_FLAG_PM_RUNTIME & DL_FLAG_RPM_ACTIVE.
The action is expected by the driver to let all power domains
always on.
Fixes: 583c9de66ebf(gpu: imx: Add dpu common driver support)
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
DPU found in i.MX8qxp SoC may drive parallel display via
pixel link with display stream1. The pixel link MST address
of this particular display path is 1 instead of 0. So, this
patch adds DPI encoder support so as to specify the MST
address and also to enable SYNC_CTRL and pixel link MST_VLD.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds MEDIA_BUS_FMT_RGB565_1X30_PADLO format support for
the DPU TCON unit.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
In the coming patch, we would wait for FrameGen counter moving in
->atomic_disable() to get synchronization before disabling DPRC
repeat_en. It appears that waiting for 50ms for video mode
1920x1080@24Hz is not enough in this case and increasing timeout
to 100ms looks ok.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 910d3b8759bb8635b2b9d563cc934748e5aeaa81)
No one is using pin-off operations, so let's remove them.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 7243d962bb29a35ba4ee1328bdb5d011cf1471cd)
Another coming patch will wait for framegen secondary channel syncup
for non-sync mode cases. It appears that waiting for 50ms for video
modes like 1920x1080p@24 and 1920x1080p@30 is not enough. So, this
patch increases the timeout value to 100ms.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Since of_irq_count() is not exported as a symbol, we cannot
find it's definition when imx-dpu-core is built as a module.
To address this issue, this patch calls platform_irq_count()
to get irq count instead.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Any CRTC driver should use the crtc_clock instead of clock value from
drm_display_mode structure, since the crtc_clock might differ from the
actual pixel clock needed by that mode.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
To make sure SCU misc settings are in valid status at system resume
stage, let's initialize them in dpu_resume().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The KACHUNK_CNT SCU misc setting is for DPU blit engine's prefetch engine.
It represents how many cycles are needed to trigger prefetch engine after
DPU shadow being loaded. Set it to be 32, which is recommended and tested.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The SCU misc settings of DC subsystem contain pixel link settings
and other settings, like DC sync mode and KACHUNK_CNT. So, it would
be better to rename dpu_pxlink_init() to dpu_sc_misc_init(), which
includes initialization code for all SCU misc settings of DC subsystem.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The function dpu_sc_misc_init() actually gets the SCU handle only.
So, renaming it to dpu_sc_misc_get_handle() better reflects what it does.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The LVDS encoder driver for i.MX8qxp SoC needs to enable/disable pixel link
in order to meet some sequence requirements, otherwise, display artifacts
will be seen on LVDS display. This patch avoids to enable/disable pixel
link in the FrameGen driver for this special encoder.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
i.MX8qxp LDB dual channel mode uses two LDB channels from two LDB
instances, while i.MX8qm LDB uses two LDB channels from one LDB
instance. So, this patch adds flag has_dual_ldb in struct dpu_data
so that it can be used to tell the difference.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch caches encoder_type in struct dpu_framegen when we
call framegen_cfg_videomode(). This cached type can be used
later when determining whether to enable pixel link in the
FrameGen driver or not.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
As DPU fetchunits support ITU601(limited range)/ITU601_FR(full range)
and ITU709(limited range) YUV to RGB color space conversions, we may
add color encoding and color range properties support for planes.
Considering software backward compatibility, the default color encoding
is set to ITU601 with full color range.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds mulitple pixel blend modes for DPU plane.
The modes are "None", "Pre-multiplied" and "Coverage".
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Without the new blend modes("None", "Pre-multiplied" and "Coverage")
introduced in the below commit, the old userspace assumes alpha in
pixel is per-premultiplied by default. So, let's support the default
blend mode properly.
commit a5ec8332d4 ("drm: Add per-plane pixel blend mode property")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds extdst_pixengcfg_syncmode_master() helper support
so that the callers may control if a extdst is master or slave
when it works in sync mode. The bit16 of extdst's PIXENGCFG_STATIC
register controls this and it's a part of sync mode fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Bit7 of framegen's SECSTATCONFIG register is used to control
the sync mode fixup logic implemented in framegen. This patch
adds framegen_syncmode_fixup() helper so that the callers
may enable/disable the fixup logic for a framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Store9 unit can be shared bewteen display engine(for sync mode fixup)
and blit engine. It's proper to get the store resource in the DPU
common driver and then provide it to client platform device via
platform data.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Bit16 of store9's PIXENGCFG_STATIC register is used to control
the sync mode fixup logic implemented in store9. So, let's
add store9 support in the DPU core driver and export a function
for users to enable/disable the fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch sets master stream id to be 1 for i.MX8QM DPU.
The master stream id is used when FrameGen works in sync mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds pixel combiner support in the DPU core driver.
Users may get and enable/disable/control a pixel combiner instant
via tcon functions and may tell if it is needed in a specific usecase
via the dpu_get_syncmode_min_prate() and dpu_get_singlemode_max_width()
helpers.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for tcon so that
two tcons can participate in the dual display streams
to work with pixel combiner to drive a high pixel rate
display.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for framegen so that
two framegens can work in sync mode to participate in the
dual display streams to drive a high pixel rate display
via a pixel combiner.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds helper dpu_pxlink_set_dc_sync_mode() support
so that callers may enable or disable DC sync mode.
In DC sync mode, high pixel rate video mode can be supported
by combining two display streams together.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds tcon_is_master/slave() helpers support so that
callers may know if a tcon is a master or slave tcon.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds extdst_is_master() helper support so that
callers may know if a extdst is a master extdst or not.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds framegen_is_master/slave() helpers support so that
callers may know if a framegen is a master or slave framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds helper dpu_get_master_stream_id() support
so that callers may know the master stream when FrameGen
works in sync mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch introduces master_stream_id flag in struct dpu_data
so that master stream can be chosen when FrameGen works in sync mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds a new di_grp_id entry in display client pdev's data
so that the relevant display platform driver may know the display
group ID of the display device.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The CRTC background should be full screen instead of partial
screen, because the DRM core is likely to add configurable
background color support in the future. We may cover the full
screen with ConstFrame0/1, upon which builds planes. With this,
it is easier to compute each plane's layer offset vs CRTC start
point and all ConstFrame units can be controlled by CRTC.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds two helpers to get and clear FrameGen secondary channel
status respectively. Via the two helpers, users may know if there is
empty FIFO read request on this channel or not after getting the status.
And, if yes, users may choose to clear the status. According to the IP
spec, the empty FIFO read request indicates that data stream from a Fetch
unit(e.g., AXI bandwidth not sufficient) fell down. Assuming the display
driver sets things up properly, the falling down is very likely caused by
the insufficient AXI bandwidth, that is, display underrun.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
To workaround the errata TKT320950, DPR/PRG need to evade the first dumb frame
which is generated by DPU. The way we achieve that is to bypass TCON(but set
the TCON sync signals and KA_CHUCK strobe signal up) before enabling the DPU
display controller, and then 1) enable the display controller, 2) wait for the
frame index starting to move and 3) finally switch TCON to operation mode.
Steps 1) to 3) should be done within a frame, so we disable local irq and
preemption to make sure we don't relinquish CPU during the procedure.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We don't need holding mutex when accessing registers in display engine
units, because KMS is the only relevant client driver and it has ww mutex
mechansim to ensure there is no race condition on the CRTC resources.
Also, we are naturally safe when the driver initializes the units at the
probe and system power management stages.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Oliver F. Brown