This patch adds all pinctrl settings for LCDIF to send
out parallel display signals to externel display device.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds pwm device tree support for i.MX8qxp ADMA support.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds pwm lpcg clocks support for i.MX8qxp ADMA subsystem.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
LCDIF mux found in i.MX8qxp SoC muxes different inputs to
parallel display interface. The control register for the
mux lives in LCDIF mux regs region. This patch adds a
relevant LCDIF mux regs syscon node for that region.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
i.MX8qxp DPU display stream1 may drive a parallel display through
pixel link to LCDIF mux. This patch adds lcdif endpoint to DPU node.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Add extra pcie dts file to enable wireless (like NXP
88w8997 and CYPRESS 4356/4359) since most of A0 chips
pcie has issue, which is convenient for tester to verify
wireless on comming release with golden chips.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Correct ldo1/ldo2 voltage as below:
ldo1 --NVCC_SNVS_1V8
ldo2 --VDD_SNVS_0V8
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 6e1db954c1261c9a8a40f7c4e33f03173c4d05b6)
(cherry picked from commit c159238cd48be1814736ed1eed8905572777d195)
Add CM7 remote proc node, decrease rpmsg dma node to 2MB only for
pcie usage.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add cm4 node for remoteproc usage. Currently added ipc-only
for partitioned M4 usage, late this property will be dropped
and check partitioned M4 in driver.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Make sure all the needed clocks are enabled for mipi_csi,
do not rely on mipi_dsi or lcdif to enable them.
Needed: media_cam1_pix, media_axi_root, media_apb_root
Tested with VSI ISP demo.
Not tested with camera on CSI2.
Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
Tested-by: Oliver Brown <oliver.brown@nxp.com>
Add property audio-interface for set sai or esai.
Add imx8mp-evk-dsp.dts for supporting cplay in mp board.
Signed-off-by: Zhang Peng <peng_zhang_8@nxp.com>
commit d79e9d7c1e upstream.
The correct setting for the RGMII ports on LS1046ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID.
Since commit 1b3047b520 ("net: phy: realtek: add support for
configuring the RX delay on RTL8211F") the Realtek 8211F PHY driver
has control over the RGMII RX delay and it is disabling it for
RGMII_TXID. The LS1046ARDB uses two such PHYs in RGMII_ID mode but
in the device tree the mode was described as "rgmii".
Changing the phy-connection-type to "rgmii-id" to address the issue.
Fixes: 3fa395d2c4 ("arm64: dts: add LS1046A DPAA FMan nodes")
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 4022d808c4 upstream.
The correct setting for the RGMII ports on LS1043ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID.
Since commit 1b3047b520 ("net: phy: realtek: add support for
configuring the RX delay on RTL8211F") the Realtek 8211F PHY driver
has control over the RGMII RX delay and it is disabling it for
RGMII_TXID. The LS1043ARDB uses two such PHYs in RGMII_ID mode but
in the device tree the mode was described as "rgmii_txid".
This issue was not apparent at the time as the PHY driver took the
same action for RGMII_TXID and RGMII_ID back then but it became
visible (RX no longer working) after the above patch.
Changing the phy-connection-type to "rgmii-id" to address the issue.
Fixes: bf02f2ffe5 ("arm64: dts: add LS1043A DPAA FMan support")
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit b54d390086 ]
The LS1043A SoC is affected by the A050385 erratum stating that
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak thus stopping further packet processing.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
increase the resolution limitation from 1920x1080 to 1920x1920
I have submitted the patch on branch 4.19.y
I don't know why branch 5.4 doesn't include this patch
so I submit it again
Signed-off-by: Ming Qian <ming.qian@nxp.com>
Currently hsio root clock is always on, which should be handled
by hsiomix power domain driver but there is problem on doing that,
see commit 5aaceda10a ("MLK-23671-02 arm64: dts: imx8mp: Add the
rpm-always-on flag for hsiomix domain"):
"The hsiomix power domain need to be runtime always-on to maintain USB's
wakeup ability. As this domain need to be boot on by default, no one
will call the power on callback during system boot up, the clock
enable/disable will mismatch, so remove the clocks from this domain.
the necessary clocks will be handled in TF-A."
There is one clock(AXI_DIV) shared between hsiomix and USB, with
rpm-always-on property added, like above commit description, power
domain driver will not do enable/disable and think it's always on, but
it can be disabled by USB driver, afterwards if power domain driver does
hsiomix register access, system will hang because the required clock was
disabled.
Now with above commit and change in TF-A, those clocks are not
controlled by Linux for power domain operations, but user driver(i.e. USB
and PCIE) has to handle it.
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
USB controller isolation is controlled by hsiomix power domain,
instead of usb_otg1_pd and usb_otg2_pd, those 2 power domains are
for USB PHY isolation and in our case, PHY is power is kept always
on(but can be suspended).
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
1. add i2c-rpmsg support for i2c3
2. reserve memory for LPA, for the accessable memory
of m7: 0x40000000-0xbfffffff.
3. support LPA, playback only
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
Add two ov5640 support for iMX8DX platform. One work at DVP mode,
the other work at MIPI mode.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
USBOTG2 PHY's output name should be PHY ipg clock, but not controller
ahb clock, it is aligned with USBOTG1 PHY's output clock.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
the HDMI APB clock & 266M REF clock should be on when doing HDMIMIX power domain
on/off, so add these clock to hdmimix pd node.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
There is hardware issue: TKT0535653
SDMA3 can't work without setting AUDIOMIX_CLKEN0[SDMA2] (bit-26) to 1
The workaround is:
As the reset state of AUDIOMIX_CLKEN0[SDMA2] is enabled,
we just need to keep it on as reset state, don't touch it
in kernel, then every thing is same as before.
So for sdma node, it only need to care about AHB and IPG clock,
the gate of AUDIOMIX_CLKEN0[SDMA2] is always enabled.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Add i2c controller and irqsteer device node for CI_PI subsystem of iMX8QXP
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
"fsl,imx8qm-usb" is not defined at driver, and "fsl,imx27-usb"
is older model. We need to use the closest model for it to get
the newer features, like runtime pm.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
The hsiomix power domain need to be runtime always-on to maintain USB's
wakeup ability. As this domain need to be boot on by default, no one will
call the power on callback during system boot up, the clock enable/disable
will mismatch, so remove the clocks from this domain. the necessary clocks
will be handled in TF-A.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Update enet wakeup interrupt number since they are different
with imx8qxp.
Reviewed-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Add aliases for ethernet node to support set mac
address by uboot ethnaddr env.
Reviewed-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Different HSIO usecase may be used by customers.
- add PCIEAx2PCIEBx1 usecase for example.
Only verified PCIA one lane refer to the iMX8QM MEK and Baseboard
hardware limitation.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
- Enable the PCIEB port on the i.MX8QM MEK and base board.
- In the PCIEAX1PCIEBx1SATA usecase, the PHYX2_PCLK[0] is mandatory
required by PCIEB. Otherwise PCIEB can't link up when exist from
L2 mode when only PCIEB is used.
- PCIEB has one more PER clock, since that the PCIEA CSR register
would be configuired when PCIEB is initialized.
- Regarding to the base board HW limitation(two Disable#) are not
connected. Only the standard PCIe EP device is supported on PCIEB port.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Add the PCIe DMA IRQ name.
Enable the PCIe EP RC validation on iMX8MP EVK boards.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Because our relase image include m4 image by default, but dts for two
ov5640 don't include rpmsg, so user need to burn non-rpmsg flash.bin
if they want to test two ov5640 case. Test team and more and more guys
request to add rpmsg ov5640. The patch is used for the purpose.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Change sai to master for bt-sco to resolve the long latence issue
for uplink
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Correct the legacy INTX numbers of the iMX8DXL PCIe.
Use the internal PLL as PCIe REF clock.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
support only basic function
eqos network
USB1 and USB2 basic work
Only total 512MB in DDR3 evk boards
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Due to 8MQ/MM IOMUX specifics for DSD stereo case the audio
data is routed via DATA0 and DATA4 SAI1 signals, thus a
specific channel map is required for DSD stereo case. For
8MP there is no need for a such specific case, so remove it.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
This patch adds APB clock related properties in lvds phy node,
so that the driver may get and control the APB clock.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The power domain for clocks is not needed by audio drivers, which
is handled by clock driver.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
The HSIOMIX domain need to be on if usb wakeup is enabled for system
wakeup source, so add the 'active-wakeup' property for this domain.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Add power domain property for vpu node to enable power domain
off when module entering runtime PM.
BuildInfo:
- ATF 13de44f73
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Zhou Peng <eagle.zhou@nxp.com>
SOFITPSYNC
If this bit is set to '0' operating in host mode, the core keeps the
UTMI/ULPI PHY on the first port in a non-suspended state whenever there
is a SuperSpeed port that is not in Rx.Detect, SS.Disable and U3.
If this bit is set to '1' operating in host mode, the core keeps the
UTMI/ULPI PHY on the first port in a non-suspended state whenever the
other non-SuperSpeed ports are not in a suspended state. This feature is
useful because it saves power by suspending UTMI/ULPI when SuperSpeed
only is active, and it helps resolve when the PHY does not transmit a
host resume unless it is placed in suspend state. This bit must be
programmed as a part of initialization at power-on reset, and must not
be dynamically changed afterwards.
with this property specified, this bit is set to be 1.
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Disable busfreq node for AB2 as currently it is
causing "underrun" errors.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Enabled the usbotg ports on imx8qxp lpddr4 val board for uuu download
NAND image.
Signed-off-by: Han Xu <han.xu@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
8DXL have a different IRQ mapping compare to
8QM and 8QxP.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
The irqsteer_lvds1 node's ipg clock source should be
lvds1_lis_lpcg_ipg_clk, instead of lvds0_lis_lpcg_ipg_clk.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
commit 26c4b4758f upstream.
There is only on Ethernet port and one Ethernet PHY on imx8qxp-mek.
Remove the unexisting ethphy1 port.
This fixes a run-time warning:
mdio_bus 5b040000.ethernet-1: MDIO device at address 1 is missing.
Fixes: fdea904e85 ("arm64: dts: imx: add imx8qxp mek support")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Enable CAN on i.MX8QM/QXP validation board for test team requirement.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Ranges for the security subsystem node is too small and does not include
the caam_sm range.
Fixes: e08b2903ae ("LF-824: arm64: dts: Add seco mu nodes")
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Tested-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
IP module name is AUDIO XCVR, eARC being just one
of the audio interfaces supported by XCVR IP module.
Use IP module name instead of a specific audio interface
in order to avoid confusion.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Remove non-existing ADMA nodes on iMX8DXL, update the edma0 and
enable acm since this parent for some audio lpcg nodes.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
iMX8DXL does not have IMG subsystem, so remove this SS dtsi file
from iMX8DXL
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
iMX8DXL does not have MLB in connectivity subsystem, remove mlb node
and mlb_lpcg node from imx8dxl conn DTSi.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Disable those audio lpcgs which probe failed to avoid below error message during
kernel boot up:
[ 0.322195] imx8qxp-lpcg-clk 59420000.clock-controller: failed to get clock parent names
[ 0.322275] imx8qxp-lpcg-clk: probe of 59420000.clock-controller failed with error -22
[ 0.322400] imx8qxp-lpcg-clk 59440000.clock-controller: failed to get clock parent names
[ 0.322440] imx8qxp-lpcg-clk: probe of 59440000.clock-controller failed with error -22
[ 0.322568] imx8qxp-lpcg-clk 59450000.clock-controller: failed to get clock parent names
[ 0.322605] imx8qxp-lpcg-clk: probe of 59450000.clock-controller failed with error -22
[ 0.322814] imx8qxp-lpcg-clk 59460000.clock-controller: failed to get clock parent names
[ 0.322859] imx8qxp-lpcg-clk: probe of 59460000.clock-controller failed with error -22
[ 0.323022] imx8qxp-lpcg-clk 59470000.clock-controller: failed to get clock parent names
[ 0.323067] imx8qxp-lpcg-clk: probe of 59470000.clock-controller failed with error -22
[ 0.323195] imx8qxp-lpcg-clk 59c50000.clock-controller: failed to get clock parent names
[ 0.323236] imx8qxp-lpcg-clk: probe of 59c50000.clock-controller failed with error -22
[ 0.324090] imx8qxp-lpcg-clk 59d50000.clock-controller: failed to get clock parent names
[ 0.324152] imx8qxp-lpcg-clk: probe of 59d50000.clock-controller failed with error -22
[ 0.324257] imx8qxp-lpcg-clk 59d60000.clock-controller: failed to get clock parent names
[ 0.324296] imx8qxp-lpcg-clk: probe of 59d60000.clock-controller failed with error -22
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
SLSLICE[2] cannot be accessed on 8DXL platform since it is
fixed and locked clock, but can be accessed on 8qm/8qxp platforms
who want to assign the clock to 250Mhz.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Align i.MX 8mm Job ring node naming
with the rest of the i.MX 8 platforms.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Align i.MX 8QXP/QM Job ring node naming
with the rest of the i.MX 8 platforms.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
There is a shared gate clock exists after 'IMX8MP_CLK_MEDIA_
AXI_ROOT' and 'IMX8MP_CLK_MEDIA_AXI_ROOT' clocks according to
the clock tree, so correct clock values for 'mediamix-pd' by
using the corresponding gate clocks.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Tested-by: Liu Ying <victor.liu@nxp.com>
The GPU3D shader clock must be on to make sure that GPU3D can be reset
successfully.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
correct property name. power-active-high
USB OTG2 power pin function set problem is fixed by scfw
848498bf4c6d79b33cc5018969574a5369479bc4
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Commit 729dcffd1e ("usb: dwc3: gadget: Add support for disabling
U1 and U2 entries") give detail explaination for user case of
disable u1 and u2 in gadget mode:
"Usecase 1:
When combining dwc3 with an redriver for a USB Type-C device
solution, itsometimes have problems with leaving U1/U2 for
certain hosts, resulting in link training errors and reconnects.
For this U1/U2 state entries may be avoided."
on imx8mq-evk board, we have typec and redriver used and android
reported unstable issue when use some host PC for adb, so to have
a better performance, we disable u1 and u2 entries.
Reported-by: Richard Liu <xuegang.liu@nxp.com>
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
dai-index property must match dai-index from topology. FSL DAI
driver uses it for now figure out the correct DAI name, but might
be used for other things in the future.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
With the reserved memory for optee, Linux is no
longer able to allocate CMA within the allocation
range defined in the dtb.
Increase the alloc-range so that Linux can allocate in the 4G
address range (in case some DMA are not able to address more).
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
Correct the HDMI irqsteer's interrupt controller parent, otherwise the HDMI
irq can NOT wakeup the cpu core from idle timely, then HDMI performance
will be impacted.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
IC confirmed the both imx8qm and imx8qxp could use 250M as usb3_clk
and no performance drop.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Add new compatible 'imx8mp-sdma' for sdma2/sdma3 to support resume back after
audiomix off.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Topology is similar with the one for i.MX8QXP but now we really
use correct name for SAI: sai3 instead of sai1.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
The GPU AXI/AHB & ML AXI/AHB clock must be on when doing corresponding
power domain on/off, so Add these clocks to GPUMIX & MLMIX power domain.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
With GPC as interrupt parent, need set edac and irqsteer interrupt
parent as gpc.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
iMX8DXL EVK board only has 1GB DDR, so it can't allocate 960MB CMA.
Change the CMA size to 320M to align with 8DX.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
The MIPI clock parenting is made in dts file, causing the MIPI clocks to
be parented even if that specific MIPI node is needed or not, causing
issues to the LVDS block (which has a shared PHY with MIPI on 8QXP).
In order to avoid these problems with the shared PHY on 8QXP, store the
MIPI parent clock for phy and escape clocks, along with their rates and
do the re-parenting in the MIPI driver only when a bridge (or panel) is
attached to it.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Dong Aisheng <aisheng.dong@nxp.com>
[Aisheng: Tested on MX8QM/QXP with single LVDS-HDMI or MIPI panel]
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 2f794bb2f88e18e43dab31f2edea98177fce4e95)
A new device tree file fsl-ls1028a-rdb-dpdk.dts is added
for user space networking.
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com>
Reviewed-by: Li Yang <leoyang.li@nxp.com>
(cherry picked from commit 5c1ec7a8a42de9b144ee87177c016270a3334492)
Now seems only ls1028a-qds using overlay by adding fragment dtbs.
Add their support in Makefile.
This is one of approach suggested by DT maintainer Rob here:
https://lore.kernel.org/patchwork/patch/821645/
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com>
Tested-by: Alex Marginean <alexandru.marginean@nxp.com>
(cherry picked from commit 7220fa2e1a02e471f5d3276601709f3df372ee63)
Labels are used to name switch port net devices in Linux, use more
convenient names to make it simpler for users.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
(cherry picked from commit 3ad82375cfc4d4f6df68ebe02164995de654001c)
Adds overlays for various serdes protocols on LS1028A QDS board using
different PHY cards. These should be applied at boot, based on serdes
configuration. If no overlay is applied, only the RGMII interface on
the QDS is available in Linux.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
(cherry picked from commit 779c69e4ae9d1535e958cda7309f030293e3c45c)
Named the ports node of the Felix Eth switch so it can be used in DT
overlays to associate the ports with proper PHYs.
Ports are now by default disabled in dtsi, so if the board dts doesn't
do anything about them they stay disabled.
Updated RDB and QDS dts files to match.
Replaced all 'phy-connection-type' with 'phy-mode'.
The set-up for protocol 7777 on QDS was changed to a single quad port card
in slot 1. This requires a QDS board with no lane B rework and a AQR412
or similar PHY card without any lane rework done on it.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
(cherry picked from commit 0462421755cb92b3ee9ace632d15a9a19db9f14c)
Use ethernet-phy@ADDR, previously the numbers were wrong.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
(cherry picked from commit 4085dc853441dd17b53a95d19f324d76d946fee3)
This was missed when moving the CPU port and disabling eno3.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
(cherry picked from commit b180bb294ef127e40f11d186443aed162cd5d270)
This enables monitoring of link status and AN. It should also physically
enable SGMII AN with the VSC8514 PHY, but in practice that is still
hardcoded as "on" in the PHY driver, at the moment. So since Felix
actually disables SGMII AN when this DT property is absent, this would
result in an in-band AN mismatch between the MAC and the PHY. So this
property is required for the moment for this MAC/PHY combination.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
(cherry picked from commit 57575d3b92a1b2ca9fb0e75dcf20d8283df2dcfd)
This reverts commit 841edb9867.
There are 2 separate issues with interrupts on the LS1028A-RDB board:
1. The GPIO1_DAT25 interrupt line is shared, so there is a real risk of
race conditions if used in edge-triggered mode, as we currently do.
This can be illustrated in the following setup:
- Take 2 LS1028A-RDB boards
- Connect swp0 to swp0, swp1 to swp1, swp2 to swp2
- Plug/unplug the power to board 2, 10 times in a row. This will make
the PHYs lose link simultaneously.
- Notice that at one point, the net devices on board 1 remain in a
state where not all the links are down (visible in "ip link"):
5: swp0: <BROADCAST,MULTICAST,UP> mtu 1468 qdisc pfifo_fast master br0 state UP mode DEFAULT group default qlen 1000
link/ether be:97:36:d3:3d:70 brd ff:ff:ff:ff:ff:ff
6: swp1: <BROADCAST,MULTICAST,UP> mtu 1468 qdisc pfifo_fast master br0 state UP mode DEFAULT group default qlen 1000
link/ether be:97:36:d3:3d:71 brd ff:ff:ff:ff:ff:ff
7: swp2: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1468 qdisc pfifo_fast master br0 state DOWN mode DEFAULT group default qlen 1000
link/ether be:97:36:d3:3d:72 brd ff:ff:ff:ff:ff:ff
This cannot be solved by making the interrupts level-triggered,
because the gpio-mpc8xxx controller only supports generating
edge-triggered interrupts. So the effective reality is that we
cannot not use shared interrupts connected to the gpio1
interrupt-parent.
2. The uBUS1 and uBUS2 slots that share this interrupt line with the
Ethernet PHYs are not pulled up by default, they are left floating on
current revisions of the LS1028A-RDB boards. So sufficient electrical
noise on these lines will make the CPLD think there's an interrupt
request, so it asserts the GPIO1_DAT25 signal and leaves it asserted.
This means that the PHYs on those boards will never have link when
used in interrupt mode, because their IRQ will be masked by the uBUS
line that is erroneously kept asserted. In poll mode this issue does
not occur.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
(cherry picked from commit f0d8d28ed417194f9e83e495949225d18d1505c7)
Use generic node name and specific label name.
Add m25p,fast-read.
Use dt-bindings constants in interrupts instead of using numbers.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
(cherry picked from commit 58f10e679079d68275f961f131bb146abf532b6d)
Use compatibles as "jedec,spi-nor" to probe flash without displaying
warning: found s25fs512s, expected m25p80.
Remove "fsl,qspi-has-second-chip" as new driver doesn't use it anymore.
Update rx and tx width to 1.
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
(cherry picked from commit 538bebe00be17f49d6f4c5b5b75be67ba4bf6ed4)
Use compatibles as "jedec,spi-nor" to probe flash without displaying
warning: found s25fs512s, expected m25p80.
Also remove "fsl,qspi-has-second-chip" property as new driver doesn't use
it anymore.
Update dtsi compatibles to use "fsl,ls2080a-qspi".
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
(cherry picked from commit 7afe154e046717c9c6249ac7ded256563236811a)
Add the iommu-map property to the pci nodes so that the firmware
fixes it up with the required values thus enabling iommu for
devices connected over pci.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
(cherry picked from commit 94db63e57e5150e693ab39a3195a0ac02000fb05)
Decrease the maximum allowed memory bandwidth for the LCDIF-ADV7535
use-case. The reason for this decrease is described by errata e11326.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit 3fb1a1b1065be60b06540de066a737244c97fb86)
The eDMA of LS1028A soc has a little bit different from others, So we
should distinguish them in driver by compatible.
Signed-off-by: Peng Ma <peng.ma@nxp.com>
(cherry picked from commit fa6956d853b3ebed26e1588e7b78d959701fa841)
remove the redundant qspi node in i.MX8MQ EVK dts
Signed-off-by: Han Xu <han.xu@nxp.com>
(cherry picked from commit 55983f692e8cff1c0892dfb7d3c5b7fa2a2341b4)
Update rx and tx bus-width to 1.
Use compatibles as "jedec,spi-nor" to probe flash without displaying warning:
found s25fs512s, expected m25p80
Remove property 'big-endian' as it is not used by new driver anymore.
Also, update dtsi compatibles to use "fsl,ls1021a-qspi".
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
(cherry picked from commit e9f44d4f413bc6b8cd0d9fdaece2bcc1cb1edbc5)
According to latest datasheet Rev.0.1, 03/2020, VDD_ARM does
NOT have dependency on VDD_SOC, so below table in datasheet
can be used directly for VDD_ARM:
Clock Voltage
1.2GHz 0.85V
1.4GHz 0.95V
1.5GHz 1.0V
For DDR4 EVK board, system runs at nominal mode, so GPU can
ONLY run up to 400MHz.
For LPDDR4 EVK board, system runs at over-drive mode, so GPU
can run up to 600MHz.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
BL32 base address is set within the first 1GByte of DDR.
As a new rule it will be set at base address + 0x16000000.
This new position will relax current dependency of the OPTEE
base address on the size of the DDR.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
[ Upstream commit 3f03a58b25 ]
Add power-domains entry for smmu, so that the it is accessible as long
as the driver is active. Without this device shutdown is throwing the
below warning:
"[ 44.736348] arm-smmu-v3 36600000.smmu: failed to clear cr0"
Reported-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 96ff264bcc ]
An experimental test with the command below gives this error:
rk3399-firefly.dt.yaml: dwmmc@fe310000: wifi@1:
'reg' is a required property
rk3399-orangepi.dt.yaml: dwmmc@fe310000: wifi@1:
'reg' is a required property
rk3399-khadas-edge.dt.yaml: dwmmc@fe310000: wifi@1:
'reg' is a required property
rk3399-khadas-edge-captain.dt.yaml: dwmmc@fe310000: wifi@1:
'reg' is a required property
rk3399-khadas-edge-v.dt.yaml: dwmmc@fe310000: wifi@1:
'reg' is a required property
So fix this by adding a reg property to the brcmf sub node.
Also add #address-cells and #size-cells to prevent more warnings.
make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200110142128.13522-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 7f21473502 ]
An experimental test with the command below gives this error:
px30-evb.dt.yaml: dwmmc@ff390000: clock-names:2:
'ciu-drive' was expected
'ciu-drv' is not a valid dwmmc clock name,
so fix this by changing it to 'ciu-drive'.
make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
Link: https://lore.kernel.org/r/20200110161200.22755-1-jbx6244@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 2e198c395a ]
The WiFi firmware used on db845c implements the 8bit host-capability
message, so enable the quirk for this.
Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191113232245.4039932-1-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit d026c96b25 ]
QUSB2 PHY on msm8996 doesn't work well when autosuspend by
dwc3 core using USB2PHYCFG register is enabled. One of the
issue seen is that PHY driver reports PLL lock failure and
fails phy_init() if dwc3 core has USB2 PHY suspend enabled.
Fix this by using quirks to disable USB2 PHY LPM/suspend and
dwc3 core already takes care of explicitly suspending PHY
during suspend if quirks are specified.
Signed-off-by: Manu Gautam <mgautam@codeaurora.org>
Signed-off-by: Paolo Pisati <p.pisati@gmail.com>
Link: https://lore.kernel.org/r/20191209151501.26993-1-p.pisati@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit c35a516a46 ]
Add the Performance Monitoring Unit (PMU) device tree node to the H5
.dtsi, which tells DT users which interrupts are triggered by PMU
overflow events on each core.
As with the A64, the interrupt numbers from the manual were wrong (off
by 4), the actual SPI IDs have been gathered in U-Boot, and were
verified with perf in Linux.
Tested with perf record and taskset on an OrangePi PC2.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 7aa9b9eb7d ]
Add the Performance Monitoring Unit (PMU) device tree node to the H6
.dtsi, which tells DT users which interrupts are triggered by PMU
overflow events on each core. The numbers come from the manual and have
been checked in U-Boot and with perf in Linux.
Tested with perf record and taskset on a Pine H64.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit a793e19c15 ]
Although it appeared to follow logically from the bindings, apparently
the thermal framework can't properly cope with a single cooling device
being shared between multiple maps. The CPU zone is probably easier to
overheat, so remove the references to the (optional) fan from the GPU
cooling zone to avoid things getting confused. Hopefully GPU-intensive
tasks will leak enough heat across to the CPU zone to still hit the
fan trips before reaching critical GPU temperatures.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Link: https://lore.kernel.org/r/5bb39f3115df1a487d717d3ae87e523b03749379.1573908197.git.robin.murphy@arm.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Design team confirms that i.MX8MP can support ARM/SOC with any
combinations(SOD/OD, SOD/ND, OD/OD, OD/ND, ND/ND, ND/OD), it has
level shift and STA timing passed, so ARM's 1.2GHz opp can use
typical 0.85V directly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
DXL use usb pwr alternate function in pinmux.
Needn't GPIO regulator
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
We use existing simple-audio-card machine driver to demonstrate
the usage of SAI3 + wm8960 codec.
FSL DAI driver is used in order to manage SAI resources (PD, clocks,
pinctrl) the rest is taken care of by the SAI driver from the DSP.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
mu2 node is used by the mailbox framework for SOF. Add corresponding
compatible, clocks and mbox-cells properties.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Move MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_EARC_SCL,
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_EARC_SDA
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_EARC_DC_HPD
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_EARC_CEC
into pinctrl_hog since are needed by both hdmi and xcvr modules.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Add the wait mode workaround on i.MX8MP. it is just
a provisional patch for Alpha release. it will be
dropped in the future. As all the changes in this
patch need to be revered for that time, just including
all the changes of dts & driver in one patch to make
it more easier to track all the changes.
Coresight probe has some conlict with the IPI workaround.
it is meaningless to put effort on resolve such conflict,
and Coresight is not an must feature for Alpha release,
disable the Coresight support directly.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Add lpspi3 for imx8dxl-evk. According to the schematic, disable it
by default to support display functions.
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Add i2c3 node.
Correct the place of pca9548 to i2c2 and i2c3.
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
commit 3543d7ddd5 upstream.
The interrupt map for the FVP's PCI node is missing the
parent-unit-address cells for each of the INTx entries, leading to the
kernel code failing to parse the entries correctly.
Add the missing zero cells, which are pretty useless as far as the GIC
is concerned, but that the spec requires. This allows INTx to be usable
on the model, and VFIO to work correctly.
Fixes: fa083b99eb ("arm64: dts: fast models: Add DTS fo Base RevC FVP")
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add eqos support for imx8dxl evk board.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Add missing cpu-supply assignment to support voltage scaling by cpu-freq
driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
operating-points-v2 is used on i.MX8MN, so the 1.2GHz OPP overwrite
based on old i.MX8M cpu-freq driver is incorrect, correct it to be
based on operating-points-v2.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
With these two parameters tuning, it can pass USB eye diagram at evk board.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
commit 62bba54d99 upstream.
Explicitly set the switch cpu (upstream) port phy-mode and managed
properties. This fixes the Marvell 88E6141 switch serdes configuration
with the recently enabled phylink layer.
Fixes: a612083327 ("arm64: dts: add support for SolidRun Clearfog GT 8K")
Reported-by: Denis Odintsov <d.odintsov@traviangames.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 1eebac0240 upstream.
The uDPU uses both ethernet controllers, which ties up COMPHY 0 for
eth1 and COMPHY 1 for eth0, with no USB3 comphy. The addition of
COMPHY support made the kernel override the setup by the boot loader
breaking this platform by assuming that COMPHY 0 was always used for
USB3. Delete the USB3 COMPHY definition at platform level, and add
phy specifications for the ethernet channels.
Fixes: bd3d25b073 ("arm64: dts: marvell: armada-37xx: link USB hosts with their PHYs")
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 05caa5bf9c upstream.
The tcsr syscon region is really 0x40000 in size. We need access to the
full region so that we can access the axi resets when managing the
modem subsystem.
Fixes: c783394956 ("arm64: dts: qcom: msm8998: Add smem related nodes")
Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
Link: https://lore.kernel.org/r/20191107045948.4341-1-jeffrey.l.hugo@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add the display port firmware name property and set it to dpfw.bin for
the lpddr4 validation board, and the hdmi firmware name property and
set it to hdmitxfw.bin for the mek board. This tells the driver to load
right the firmware based on the compatible property.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Sandor Yu <sandor.yu@nxp.com>
Add ddr controller dts node to support edac driver for imx8mp.
Also change CMA alloc-ranges to avoid memory address confilct with
inline ECC region if ECC is enabled on imx8mp lpddr4.
Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
All i.MX8DXL EVK boards are reworked, so no need to have SD workaround
DTB.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
This patch adds JDI WUXGA LVDS panel device tree node support
on the i.MX8mp EVK platform.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds PWM backlight device tree node support for LVDS panel
on the i.MX8mp EVK platform.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds it6263 LVDS to HDMI transmitter channel0 support
on the i.MX8mp EVK platform.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds it6263 LVDS to HDMI transmitter dual channel support
on the i.MX8mp EVK platform.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds LDB devictree node support.
LVDS PHY node is also added as needed by the LDB node.
Also, connect lcdif2_disp port with lvds-channel@0/1 ports.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Add the busfreq node to enable the DDR DVFS support on i.MX8MP.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
This is a subdevice of audiomix MFD device, exposing
access to DSP control register from AudioMIX subsystem.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
1. Add reserved_mem for DSP and enable DSP.
2. Audio-mix DSP node will instantiate part of the AUDIOMIX who
takes care of DSP configuration.
Signed-off-by: Zhang Peng <peng_zhang_8@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
commit eac8ce86cb upstream.
vdd_apc is the regulator that supplies the main CPU cluster.
At sudden CPU load changes, we have noticed invalid page faults on
addresses with all bits shifted, as well as on addresses with individual
bits flipped.
By putting the vdd_apc regulator in high power mode, the voltage drops
during sudden load changes will be less severe, and we have not been able
to reproduce the invalid page faults with the regulator in this mode.
Fixes: 8faea8edbb ("arm64: dts: qcom: qcs404-evb: add spmi regulators")
Cc: stable@vger.kernel.org
Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20191014120920.12691-1-niklas.cassel@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Enable HDMI audio, playback only.
errata ERR050440:
HDMI Audio interface from the Audio subsystem to the HDMI
subsystem has an incorrectly inverted sampling clock, this
results in corrupted audio on HDMI output. (noise)
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
simple-audio-card uses 'label' property to set the correct card name. We
were using 'model' because that name was used by non-SOF drivers.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
i.MX8MP should not share i.MX8MQ ocotp, it has different ocotp
ctrl layout and register numbers
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Liu Ying