The mediamix block control module access requires the
'IMX8MP_CLK_MEDIA_APB_ROOT' clock to be enabled, so
add this clock to this device node.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
To align with the port names of 'lcdif2_disp' and 'lcdif3_disp',
rename 'lcdif_disp0' to 'lcdif1_disp'.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Since the 'mipi_phy1_ref' clock rate is usually set to
be 27MHz and won't be changed after boot up. So assign
27MHz rate instead of 594MHz to this clock is much more
reasonable.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
The 'disp1_pix' clock is used to provide pixel clock for
LCDIF1 and its rate is closely related with the display
mode resolution which is configured. So this clock rate
is dynamically determined and unnecessary to be assigned
with a default value at boot up.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
The 'video_pll1' clock is shared by MIPI and LVDS displays
and each of the display has a specific requirement for the
PLL rate which can be satified by set 'video_pll1' rate to
be 2079MHz. So assign 2079MHz rate to 'video_pll1' under
CCM device.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Inculding below cleanup for BD71847 pmic driver:
--Remove ldo4 which's not used by board, otherwise,ldo4 will be on
since it's always_on.
--Remove buck5 which's not used by board too,although that may be off
by kernel requlator common framework after kernel bootup.
--Add dvs-run-voltage/dvs-idle-voltage setting for buck2 as i.mx8mm.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
[ Upstream commit 46f94c7818 ]
If the mv88e6xxx DSA driver is built as a module, it causes the
ethernet driver to re-probe when it's loaded. This in turn causes
the gigabit PHY to be momentarily reset and reprogrammed. However,
we attempt to reprogram the PHY immediately after deasserting reset,
and the PHY ignores the writes.
This results in the PHY operating in the wrong mode, and the copper
link states down.
Set a reset deassert delay of 10ms for the gigabit PHY to avoid this.
Fixes: babc5544c2 ("arm64: dts: clearfog-gt-8k: 1G eth PHY reset signal")
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit f9f711efd4 ]
If the kernel configuration option CONFIG_PCIE_DW_PLAT_HOST is enabled
then this can cause the kernel to incorrectly probe the generic
designware PCIe platform driver instead of the Tegra194 designware PCIe
driver. This causes a boot failure on Tegra194 because the necessary
configuration to access the hardware is not performed.
The order in which the compatible strings are populated in Device-Tree
is not relevant in this case, because the kernel will attempt to probe
the device as soon as a driver is loaded and if the generic designware
PCIe driver is loaded first, then this driver will be probed first.
Therefore, to fix this problem, remove the "snps,dw-pcie" string from
the compatible string as we never want this driver to be probe on
Tegra194.
Fixes: 2602c32f15 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 3e9a1a8b7f ]
Register range of display clocks is 0x10000, as it can be seen from
DE2 documentation.
Fix it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Fixes: 2c796fc8f5 ("arm64: dts: allwinner: a64: add necessary device tree nodes for DE2 CCU")
[wens@csie.org: added fixes tag]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Update the model string of i.MX8MP EVK board to align with upstream kernel.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Add easrc clk control in dsp driver, easrc is added to offload audio
playback pipeline in imx8mp board.
Signed-off-by: Zhang Peng <peng.zhang_8@nxp.com>
Correct ldo1/ldo2 voltage as below:
ldo1 --NVCC_SNVS_1V8
ldo2 --VDD_SNVS_0V8
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit d11796134f55d88b49d79bf25d6c42b677ff47bc)
commit dde061b865 upstream.
Without a VBUS supply the dwc3 driver won't go into otg mode.
Fixes: eb4ea0857c ("arm64: dts: fsl: librem5: Add a device tree for the Librem5 devkit")
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit a81e5442d7 upstream.
The TI sci-clk driver can scan the DT for all clocks provided by system
firmware and does this by checking the clocks property of all nodes, so
we must add this to the dwc3 nodes so USB clocks are available.
Without this USB does not work with latest system firmware i.e.
[ 1.714662] clk: couldn't get parent clock 0 for /interconnect@100000/dwc3@4020000
Fixes: cc54a99464 ("arm64: dts: ti: k3-am6: add USB suppor")
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Cc: stable@kernel.org
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 4ae7a3c3d7 upstream.
The commit c35a516a46 ("arm64: dts: allwinner: H5: Add PMU node")
introduced support for the PMU found on the Allwinner H5. However, the
binding only allows for a single compatible, while the patch was adding
two.
Make sure we follow the binding.
Fixes: c35a516a46 ("arm64: dts: allwinner: H5: Add PMU node")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Cc: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 4c7eeb9af3 upstream.
The commit 7aa9b9eb7d ("arm64: dts: allwinner: H6: Add PMU mode")
introduced support for the PMU found on the Allwinner H6. However, the
binding only allows for a single compatible, while the patch was adding
two.
Make sure we follow the binding.
Fixes: 7aa9b9eb7d ("arm64: dts: allwinner: H6: Add PMU mode")
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Cc: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This patch adds DPU LCDIF support with rpmsg on the i.MX8qxp MEK platform.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
As the dts file name doesn't contain 'rpmsg', we should remove the
rpmsg support to avoid user's confusion.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch introduces DPU LCDIF dts include file,
so that it may be included in some dts files as needed.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds IT6263 LVDS0/1 dual channel support with rpmsg on
the i.MX8qxp MEK platform.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds JDI WUXGA LVDS0/1 panel support with rpmsg on
the i.MX8qxp MEK platform.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
As the dts file names don't contain 'rpmsg', we should remove the
rpmsg support to avoid user's confusion.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
As the dts file names don't contain 'rpmsg', we should remove the
rpmsg support to avoid user's confusion.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch introduces IT6263 LVDS0/1 dual channel dts include files,
so that they may be included in some dts files as needed.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch introduces JDI WUXGA LVDS0/1 panel dts include files,
so that they may be included in some dts files as needed.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds JDI WUXGA LVDS1 panel support with rpmsg on
the i.MX8qm MEK platform.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
As the dts file name doesn't contain 'rpmsg', we should remove the
rpmsg support to avoid user's confusion.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch introduces JDI WUXGA LVDS1 panel dts include file,
so that it may be included in some dts files as needed.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Move mipi_csi clock changes from imx8mp.dtsi into 0v2775 dtb,
to avoid failures for ov5460.
Tested with VSI ISP demo 28/02/20 release.
Not tested with camera on CSI2.
Fixes: 636de0a39e ("Add ov2775 dtb for imx8mp")
Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
Acked-by: G.n. Zhou <guoniu.zhou@nxp.com>
Change the reserved RPMSG base address from 0xb8000000 to 0x55000000,
refer to the reserved memory conflictions with DDR ECC.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Add the PCIe power domain into the PCIe DTS node refer to the power
consumption refine.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-and-tested-by: Jacky Bai <ping.bai@nxp.com>
This patch adds Seiko WVGA LCD panel support on the i.MX8qxp mek platform.
The panel is driven by DPU in DC0 subsystem.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds backlight support for LCDIF display on
i.MX8qxp mek platform.
The backlight brightness is controlled by PWM.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds adma_pwm support for i.MX8qxp mek platform.
The PWM can be used to control display panel's backlight.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds PWM pinctrl setting support for LCDIF display.
The PWM can be used to control display panel's backlight.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds all pinctrl settings for LCDIF to send
out parallel display signals to externel display device.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds pwm device tree support for i.MX8qxp ADMA support.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds pwm lpcg clocks support for i.MX8qxp ADMA subsystem.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
LCDIF mux found in i.MX8qxp SoC muxes different inputs to
parallel display interface. The control register for the
mux lives in LCDIF mux regs region. This patch adds a
relevant LCDIF mux regs syscon node for that region.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
i.MX8qxp DPU display stream1 may drive a parallel display through
pixel link to LCDIF mux. This patch adds lcdif endpoint to DPU node.
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Add extra pcie dts file to enable wireless (like NXP
88w8997 and CYPRESS 4356/4359) since most of A0 chips
pcie has issue, which is convenient for tester to verify
wireless on comming release with golden chips.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Correct ldo1/ldo2 voltage as below:
ldo1 --NVCC_SNVS_1V8
ldo2 --VDD_SNVS_0V8
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 6e1db954c1261c9a8a40f7c4e33f03173c4d05b6)
(cherry picked from commit c159238cd48be1814736ed1eed8905572777d195)
Add CM7 remote proc node, decrease rpmsg dma node to 2MB only for
pcie usage.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add cm4 node for remoteproc usage. Currently added ipc-only
for partitioned M4 usage, late this property will be dropped
and check partitioned M4 in driver.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Make sure all the needed clocks are enabled for mipi_csi,
do not rely on mipi_dsi or lcdif to enable them.
Needed: media_cam1_pix, media_axi_root, media_apb_root
Tested with VSI ISP demo.
Not tested with camera on CSI2.
Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
Tested-by: Oliver Brown <oliver.brown@nxp.com>
Add property audio-interface for set sai or esai.
Add imx8mp-evk-dsp.dts for supporting cplay in mp board.
Signed-off-by: Zhang Peng <peng_zhang_8@nxp.com>
commit d79e9d7c1e upstream.
The correct setting for the RGMII ports on LS1046ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID.
Since commit 1b3047b520 ("net: phy: realtek: add support for
configuring the RX delay on RTL8211F") the Realtek 8211F PHY driver
has control over the RGMII RX delay and it is disabling it for
RGMII_TXID. The LS1046ARDB uses two such PHYs in RGMII_ID mode but
in the device tree the mode was described as "rgmii".
Changing the phy-connection-type to "rgmii-id" to address the issue.
Fixes: 3fa395d2c4 ("arm64: dts: add LS1046A DPAA FMan nodes")
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 4022d808c4 upstream.
The correct setting for the RGMII ports on LS1043ARDB is to
enable delay on both Rx and Tx so the interface mode used must
be PHY_INTERFACE_MODE_RGMII_ID.
Since commit 1b3047b520 ("net: phy: realtek: add support for
configuring the RX delay on RTL8211F") the Realtek 8211F PHY driver
has control over the RGMII RX delay and it is disabling it for
RGMII_TXID. The LS1043ARDB uses two such PHYs in RGMII_ID mode but
in the device tree the mode was described as "rgmii_txid".
This issue was not apparent at the time as the PHY driver took the
same action for RGMII_TXID and RGMII_ID back then but it became
visible (RX no longer working) after the above patch.
Changing the phy-connection-type to "rgmii-id" to address the issue.
Fixes: bf02f2ffe5 ("arm64: dts: add LS1043A DPAA FMan support")
Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit b54d390086 ]
The LS1043A SoC is affected by the A050385 erratum stating that
FMAN DMA read or writes under heavy traffic load may cause FMAN
internal resource leak thus stopping further packet processing.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
increase the resolution limitation from 1920x1080 to 1920x1920
I have submitted the patch on branch 4.19.y
I don't know why branch 5.4 doesn't include this patch
so I submit it again
Signed-off-by: Ming Qian <ming.qian@nxp.com>
Currently hsio root clock is always on, which should be handled
by hsiomix power domain driver but there is problem on doing that,
see commit 5aaceda10a ("MLK-23671-02 arm64: dts: imx8mp: Add the
rpm-always-on flag for hsiomix domain"):
"The hsiomix power domain need to be runtime always-on to maintain USB's
wakeup ability. As this domain need to be boot on by default, no one
will call the power on callback during system boot up, the clock
enable/disable will mismatch, so remove the clocks from this domain.
the necessary clocks will be handled in TF-A."
There is one clock(AXI_DIV) shared between hsiomix and USB, with
rpm-always-on property added, like above commit description, power
domain driver will not do enable/disable and think it's always on, but
it can be disabled by USB driver, afterwards if power domain driver does
hsiomix register access, system will hang because the required clock was
disabled.
Now with above commit and change in TF-A, those clocks are not
controlled by Linux for power domain operations, but user driver(i.e. USB
and PCIE) has to handle it.
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
USB controller isolation is controlled by hsiomix power domain,
instead of usb_otg1_pd and usb_otg2_pd, those 2 power domains are
for USB PHY isolation and in our case, PHY is power is kept always
on(but can be suspended).
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
1. add i2c-rpmsg support for i2c3
2. reserve memory for LPA, for the accessable memory
of m7: 0x40000000-0xbfffffff.
3. support LPA, playback only
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
Add two ov5640 support for iMX8DX platform. One work at DVP mode,
the other work at MIPI mode.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
USBOTG2 PHY's output name should be PHY ipg clock, but not controller
ahb clock, it is aligned with USBOTG1 PHY's output clock.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
the HDMI APB clock & 266M REF clock should be on when doing HDMIMIX power domain
on/off, so add these clock to hdmimix pd node.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
There is hardware issue: TKT0535653
SDMA3 can't work without setting AUDIOMIX_CLKEN0[SDMA2] (bit-26) to 1
The workaround is:
As the reset state of AUDIOMIX_CLKEN0[SDMA2] is enabled,
we just need to keep it on as reset state, don't touch it
in kernel, then every thing is same as before.
So for sdma node, it only need to care about AHB and IPG clock,
the gate of AUDIOMIX_CLKEN0[SDMA2] is always enabled.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Add i2c controller and irqsteer device node for CI_PI subsystem of iMX8QXP
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
"fsl,imx8qm-usb" is not defined at driver, and "fsl,imx27-usb"
is older model. We need to use the closest model for it to get
the newer features, like runtime pm.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
The hsiomix power domain need to be runtime always-on to maintain USB's
wakeup ability. As this domain need to be boot on by default, no one will
call the power on callback during system boot up, the clock enable/disable
will mismatch, so remove the clocks from this domain. the necessary clocks
will be handled in TF-A.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Update enet wakeup interrupt number since they are different
with imx8qxp.
Reviewed-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Add aliases for ethernet node to support set mac
address by uboot ethnaddr env.
Reviewed-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Different HSIO usecase may be used by customers.
- add PCIEAx2PCIEBx1 usecase for example.
Only verified PCIA one lane refer to the iMX8QM MEK and Baseboard
hardware limitation.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
- Enable the PCIEB port on the i.MX8QM MEK and base board.
- In the PCIEAX1PCIEBx1SATA usecase, the PHYX2_PCLK[0] is mandatory
required by PCIEB. Otherwise PCIEB can't link up when exist from
L2 mode when only PCIEB is used.
- PCIEB has one more PER clock, since that the PCIEA CSR register
would be configuired when PCIEB is initialized.
- Regarding to the base board HW limitation(two Disable#) are not
connected. Only the standard PCIe EP device is supported on PCIEB port.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Add the PCIe DMA IRQ name.
Enable the PCIe EP RC validation on iMX8MP EVK boards.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Because our relase image include m4 image by default, but dts for two
ov5640 don't include rpmsg, so user need to burn non-rpmsg flash.bin
if they want to test two ov5640 case. Test team and more and more guys
request to add rpmsg ov5640. The patch is used for the purpose.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Change sai to master for bt-sco to resolve the long latence issue
for uplink
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Correct the legacy INTX numbers of the iMX8DXL PCIe.
Use the internal PLL as PCIe REF clock.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
support only basic function
eqos network
USB1 and USB2 basic work
Only total 512MB in DDR3 evk boards
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Due to 8MQ/MM IOMUX specifics for DSD stereo case the audio
data is routed via DATA0 and DATA4 SAI1 signals, thus a
specific channel map is required for DSD stereo case. For
8MP there is no need for a such specific case, so remove it.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
This patch adds APB clock related properties in lvds phy node,
so that the driver may get and control the APB clock.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The power domain for clocks is not needed by audio drivers, which
is handled by clock driver.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
The HSIOMIX domain need to be on if usb wakeup is enabled for system
wakeup source, so add the 'active-wakeup' property for this domain.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Add power domain property for vpu node to enable power domain
off when module entering runtime PM.
BuildInfo:
- ATF 13de44f73
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Zhou Peng <eagle.zhou@nxp.com>
SOFITPSYNC
If this bit is set to '0' operating in host mode, the core keeps the
UTMI/ULPI PHY on the first port in a non-suspended state whenever there
is a SuperSpeed port that is not in Rx.Detect, SS.Disable and U3.
If this bit is set to '1' operating in host mode, the core keeps the
UTMI/ULPI PHY on the first port in a non-suspended state whenever the
other non-SuperSpeed ports are not in a suspended state. This feature is
useful because it saves power by suspending UTMI/ULPI when SuperSpeed
only is active, and it helps resolve when the PHY does not transmit a
host resume unless it is placed in suspend state. This bit must be
programmed as a part of initialization at power-on reset, and must not
be dynamically changed afterwards.
with this property specified, this bit is set to be 1.
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Disable busfreq node for AB2 as currently it is
causing "underrun" errors.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Enabled the usbotg ports on imx8qxp lpddr4 val board for uuu download
NAND image.
Signed-off-by: Han Xu <han.xu@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
8DXL have a different IRQ mapping compare to
8QM and 8QxP.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
The irqsteer_lvds1 node's ipg clock source should be
lvds1_lis_lpcg_ipg_clk, instead of lvds0_lis_lpcg_ipg_clk.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
commit 26c4b4758f upstream.
There is only on Ethernet port and one Ethernet PHY on imx8qxp-mek.
Remove the unexisting ethphy1 port.
This fixes a run-time warning:
mdio_bus 5b040000.ethernet-1: MDIO device at address 1 is missing.
Fixes: fdea904e85 ("arm64: dts: imx: add imx8qxp mek support")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Enable CAN on i.MX8QM/QXP validation board for test team requirement.
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Ranges for the security subsystem node is too small and does not include
the caam_sm range.
Fixes: e08b2903ae ("LF-824: arm64: dts: Add seco mu nodes")
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Tested-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
IP module name is AUDIO XCVR, eARC being just one
of the audio interfaces supported by XCVR IP module.
Use IP module name instead of a specific audio interface
in order to avoid confusion.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Remove non-existing ADMA nodes on iMX8DXL, update the edma0 and
enable acm since this parent for some audio lpcg nodes.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
iMX8DXL does not have IMG subsystem, so remove this SS dtsi file
from iMX8DXL
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
iMX8DXL does not have MLB in connectivity subsystem, remove mlb node
and mlb_lpcg node from imx8dxl conn DTSi.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Disable those audio lpcgs which probe failed to avoid below error message during
kernel boot up:
[ 0.322195] imx8qxp-lpcg-clk 59420000.clock-controller: failed to get clock parent names
[ 0.322275] imx8qxp-lpcg-clk: probe of 59420000.clock-controller failed with error -22
[ 0.322400] imx8qxp-lpcg-clk 59440000.clock-controller: failed to get clock parent names
[ 0.322440] imx8qxp-lpcg-clk: probe of 59440000.clock-controller failed with error -22
[ 0.322568] imx8qxp-lpcg-clk 59450000.clock-controller: failed to get clock parent names
[ 0.322605] imx8qxp-lpcg-clk: probe of 59450000.clock-controller failed with error -22
[ 0.322814] imx8qxp-lpcg-clk 59460000.clock-controller: failed to get clock parent names
[ 0.322859] imx8qxp-lpcg-clk: probe of 59460000.clock-controller failed with error -22
[ 0.323022] imx8qxp-lpcg-clk 59470000.clock-controller: failed to get clock parent names
[ 0.323067] imx8qxp-lpcg-clk: probe of 59470000.clock-controller failed with error -22
[ 0.323195] imx8qxp-lpcg-clk 59c50000.clock-controller: failed to get clock parent names
[ 0.323236] imx8qxp-lpcg-clk: probe of 59c50000.clock-controller failed with error -22
[ 0.324090] imx8qxp-lpcg-clk 59d50000.clock-controller: failed to get clock parent names
[ 0.324152] imx8qxp-lpcg-clk: probe of 59d50000.clock-controller failed with error -22
[ 0.324257] imx8qxp-lpcg-clk 59d60000.clock-controller: failed to get clock parent names
[ 0.324296] imx8qxp-lpcg-clk: probe of 59d60000.clock-controller failed with error -22
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
SLSLICE[2] cannot be accessed on 8DXL platform since it is
fixed and locked clock, but can be accessed on 8qm/8qxp platforms
who want to assign the clock to 250Mhz.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Align i.MX 8mm Job ring node naming
with the rest of the i.MX 8 platforms.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Align i.MX 8QXP/QM Job ring node naming
with the rest of the i.MX 8 platforms.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
There is a shared gate clock exists after 'IMX8MP_CLK_MEDIA_
AXI_ROOT' and 'IMX8MP_CLK_MEDIA_AXI_ROOT' clocks according to
the clock tree, so correct clock values for 'mediamix-pd' by
using the corresponding gate clocks.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Tested-by: Liu Ying <victor.liu@nxp.com>
The GPU3D shader clock must be on to make sure that GPU3D can be reset
successfully.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
correct property name. power-active-high
USB OTG2 power pin function set problem is fixed by scfw
848498bf4c6d79b33cc5018969574a5369479bc4
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Fancy Fang