Fix memory out of bounds access.
Change arry type for functopn avi info frame,
Align the arry type and its length.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit 2fc41a88c9da514ae3f377e7cb73f4df886f038e)
The root cause of the on-the-fly switch from tile to linear fb switch issue
is identified, so the full modeset workaround is no more needed.
Patch "MLK-20506 gpu: imx: imx8_dprc: Set CROP_ULC_X/Y to be zero for linear fb"
is the correct fix for this issue.
Revert "MLK-20470 drm/imx: dpu: plane: Do full modeset for tile to linear fb switch"
This reverts commit 9245bbf650fdeb79ebf869d48b6bd1b43c2bcf3b.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 7812bebe9c60a6ce954ce5ad504a6be002835462)
Nonzero CROP_ULC_X/Y are only valid for tile framebuffer cropping.
Thus, we should set them to be zero for linear framebuffer, otherwise,
an on-the-fly switch from tile framebuffer(with cropping enabled) to
linear framebuffer would cause hardware malfunction.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 4fc67aed944526545e6ee44d582b013a6327c8d1)
This is a work-around for the shifted display issue when using DCSS with
the DDR self-refresh disabled.
Also, make sure it works with LCDIF as well.
Increasing VSYNC length gives DCSS more time to fetch the data from RAM
before the next frame kicks in.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit 3c53532c466add234ac3ca2e70cefe80ea308b4f)
When the master imx-drm-core binding fails, component_bind_all()
in imx-drm-core ->bind() callback will unbind all bound components
first and then call drm_mode_config_cleanup(). Since the encoder
and connector(located in imx_ldb.imx_ldb_channel) are freed after
the ldb ->unbind() callback, drm_mode_config_cleanup() would
accidentally access the freed encoder and connector again. To fix
this issue, we should cleanup the encoder and connector, i.e.,
remove them from the global encoder and connector lists, in the
->unbind() callback, so that, drm_mode_config_cleanup() won't find
them again in the lists. However, we have to make sure they exist
before the cleanup in the ->unbind() callback, because imx-drm-core
->unbind() calls drm_mode_config_cleanup() first and then unbinds
all components via component_unbind_all(). Moreover, the connector
isn't created at the first place if a bridge exists, so the check
before the cleanup makes sense for this reason as well.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 6d3fd1316d67ff0e62fae4067b61fd3f2809dfa5)
The dpu_plane is allocated with kzalloc() in dpu_plane_init().
In case, dpu_plane_init() fails after that allocation, the bailout path
should free the dpu_plane, otherwise, there will be memory leakage.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 99cb80f855aafbe524519db635c3d03bd4cc8d85)
When an atomic commit contains an active CRTC with no plane,
it may cause two potential issues:
First, this CRTC will fetch its last attached plane data
or has no data can be fetched depending on the plane
driver's atomic_disable() implementation.
Second, this CRTC's 'plane_changed' will be false during
the whole commit tail stage, and this will make vblank
wait to be bypassed which directly causes the later wait
flip done timeout.
So add this commit case check to the LCDIF CRTC's atomic
check to block this kind of commits.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 67ced65259a4dbf040ce4a931325be6ba97e5131)
When pixel combiner is used, it turns out that on-the-fly switch from
tile framebuffer to linear framebuffer would cause hardware malfunction
- right half display would be missing and master&slave content shadow
load done event won't come. Thus, go for a full modeset as a workaround.
Note that we check if the original framebuffer is tile or not for both
primary and overlay planes. So, this could be over-kill. The issue was
found when we use 32bit GPU super tile as the original framebuffer on the
primary plane(restart Weston frequently). However, since we usually
don't do this kind of switch in real graphics, it should be fine.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 9245bbf650fdeb79ebf869d48b6bd1b43c2bcf3b)
The iMX8QM HDMI voltage swing needs to be increased for HDMI compliance.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit 5ba997eef35fc74653c29bb99dbe4d97292dc6e4)
This addresses Coverity issues related to "Suspicious sign extension"
when an u16 is promoted to int (32bit signed) and then to u64. If the
resulting int is greater than 0x7fffffff the upper bits of the u64 will
all be 1.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The HDMI/DP firmware verison will now be displayed.
Moved firmware handling to common file for HDMI and DisplayPort.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Adobe ARGB gamut was selected even if the output pipe pixel encoding was
YUV. That produced a pink tint on the screen.
This patch will make sure the Adobe ARGB gamut is selected only when the
output pipe pixel encoding is RGB.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
DCSS HDR10 output pipe is always 10-bit. All we need to know to better
setup the LUTs and/or CSC matrices is the output colorspace.
This patch will fetch the CS from adjusted_mode's private_flags, as
indicated in the connector's mode_fixup phase.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The HDMI sink may support different color depths for RGB and/or YUV
colorspaces. Currently, for mscale, 10-bit YUV420 is used only for
2160p@60. For the rest of modes 8-bit RGB is used.
This patch will add a mode_fixup() hook in the hdp_ops struct, allowing
each platform to perform a better handling of the various color depths
and colorspaces.
With the current patch, the RGB output will always be preferred to YUV
colorspaces, given the same color depth, since YUV colorspaces perform
UV subsampling, producing less quality. Also, whenever possible, better
color depth will be preferred (12-bit, 10-bit and, lastly, 8-bit).
The chosen colorspace and color depth will always be based on EDID's
Capability Map Data Block and YUV420 Video Data Block, as well as on
HDMI controller's known clock constraints.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The video mode tmp_m, as a local variable in tcon_cfg_videomode(),
is uninitialized and used to store a copy instance from the real
video mode. tcon_cfg_videomode() would change the timing of it if
side_by_side mode is enabled. Theoretically, there should be no
problem even if we don't initialize tmp_m. However, coverity
reports that tmp_m is an uninitialized scalar variable when the copy
is being done(CID 5233067: Uninitialized scalar variable (UNINIT)).
This patch fixes the issue reported by coverity.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The logic in function h/vscaler_pixengcfg_dynamic_src_sel() to avoid
overrunning array src_sel[i][j] is wrong. The correct one is to check
on the index i which should be less than the array size of h/vs_id_array[].
This patch fixes the potential array overrunning issue, that is,
out-of-bounds array read issue. The issue is reported by coverity -
CID 1477349 and CID 1477345.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The callers of dpu_{unit}_init() might provide an invalid id as
the parameter, it may cause overrunning dpu->{unit}_priv[] and
cf_shdlreqs[] arrays and out-of-bound array access. Although
the current only caller is dpu_submodules_init() and it always
provides valid ids, it would be good to fix the potential issue.
This patch fixes several issues reported by coverity - CID 1477330,
CID 1477335, CID 1477348, CID 1477346, CID 3298619, CID 1477347,
CID 5233021 and CID 1477321.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The function get_xval() returns the C_XVAL and L_XVAL fields of
the CURPIXELCNT and LASTPIXELCNT registers. They are 16bit and
sit in the low 16bit of the registers. This patch fixes the way
we mask the register and read the fields out.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The layerblend units don't contain the CONTROLWORD, CURPIXELCNT,
LASTPIXELCNT and PERFCOUNTER registers, so let's remove them
and their wrappers(no one is calling them), which were introduced
accidentally.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The return value of sc_misc_set_control() should be checked in
ldb_pixel_link_init(), instead of being ignored. This patch
fixes this issue.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
If an RGB buffer is fed to channel-0, the output will have one line
shifted down, with the last line appearing on top.
Using the 7-tap filter will fix the issue. The 5-tap filter code will be
removed completely.
Signed-off-by: Dzung Hoang <dzung.hoang@nxp.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The brightness, when REC709 was used in the configuration of the pipes,
was lower than expected.
The reason was the HDR10 configuration application that was used to
create the tables had a parameter that was wrongly set.
The tables were re-generated with the proper setting.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Currently, the enable of the axi clock return status is ignored, causing
issues when the enable fails then we try to disable it. Therefore, it is
better to check the return status and disable it only when enable
succeeded.
Also, remove the helper functions around clk_axi, since we can directly
use the clk API function for enable/disable the clock. Those functions
are already checking for NULL clk and returning 0 if that's the case.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>i
Acked-by: Leonard Crestez <leonard.crestez@nxp.com>
Patches related to suspend/resume have been backported from upstream
kernel, therefore some of the mxsfb_drm_private members are no longer
needed, so remove them, among with the code around them.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Acked-by: Leonard Crestez <leonard.crestez@nxp.com>
The lcdif block is only powered on when display is active so plane
updates when not enabled are not valid. Writing to an unpowered IP block
is mostly ignored but can trigger bus errors on some chips.
Prevent this situation by switching to drm_atomic_helper_commit_tail_rpm
and having the drm core ensure atomic_plane_update is only called while
the crtc is active. This avoids having to keep track of "enabled" bits
inside the mxsfb driver.
This also requires handling the vblank event for disable from
mxsfb_pipe_disable.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Suggested-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/c19c0c00ed42e8e8f7965aa4821ac295abc5cd05.1537191359.git.leonard.crestez@nxp.com
Add drm_mode_config_helper_suspend/resume() which takes care of
atomic modeset suspend/resume for simple use cases.
The suspend state is stored in struct drm_mode_config.
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20171106191812.38927-3-noralf@tronnes.org
drm_fb_helper is *the* way of doing fbdev emulation so add a pointer to
struct drm_device. This makes it possible to add callback helpers for
.last_close and .output_poll_changed further reducing fbdev emulation
footprint in drivers. The pointer is set by drm_fb_helper_init() and
cleared by drm_fb_helper_fini().
Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20171030153951.56269-3-noralf@tronnes.org
Adding lcdif nodes to a power domain currently results in
black/corrupted screens or hangs because power is not correctly enabled
when required.
Ensure power is on when display is active by adding
pm_runtime_get/put_sync to mxsfb_pipe_enable/disable.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/ee88148399c63494cda4129b05444b0ac331b7a7.1537191359.git.leonard.crestez@nxp.com
LCDIF will repeatedly display data from CUR_BUF and set CUR_BUF to
NEXT_BUF when done. Since we are only ever writing to NEXT_BUF the
display will show an initial corrupt frame.
Fix by writing the FB paddr to both CUR_BUF and NEXT_BUF when
activating the CRTC.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Tested-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/7cdac9c064cc2b8a3d237934f186da98cefe6cb3.1537191359.git.leonard.crestez@nxp.com
The main axi clk is disabled at the end of mxsfb_crtc_mode_set_nofb and
immediately reenabled in mxsfb_enable_controller.
Avoid this by moving the handling of axi clk one level up to
mxsfb_crtc_enable. Do the same for mxsfb_crtc_disable for symmetry.
This shouldn't have any functional effect.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/985c1f1cad250bd9ca154b3e4b3f913c310eeabd.1537191359.git.leonard.crestez@nxp.com
Cadence allow customer release these source code as followed copyright.
* Copyright (C) 2016-2017 Cadence Design Systems, Inc.
* All rights reserved worldwide.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Unlike i.MX6qdl and i.MX53 LDB variants, the i.MX8 LDB variants(i.MX8qxp
and i.MX8qm) in existence don't have frontend mux, thus, we should split
the logic to program the ch0/1_mode for variants w/wo the mux. It turns
out LDB_CH0_MODE_EN_TO_DI0 can be used for channel0 in both LDB single
mode and LDB split mode for the i.MX8 LDB variants. However, based on
test results, for i.MX8qm LDB channel1, LDB_CH1_MODE_EN_TO_DI1 has to be
used in single mode, while, i.MX8qxp may work with LDB_CH1_MODE_EN_TO_DI0
or LDB_CH1_MODE_EN_TO_DI1. With LDB_CH1_MODE_EN_TO_DI0, i.MX8qm LDB
channel1 would output wrong image in single mode(it looks like color
is wrong based on test results). The i.MX8 LDB variants channel1 mode
can still be LDB_CH1_MODE_EN_TO_DI0 in split mode(the patch doesn't
touch this). In essence, this patch fixes the channel1 single mode for
i.MX8qm LDB by correcting the ch1_mode, while all other features
should work as before. Note that due to hardware issue, we didn't test
the channel1 single mode for i.MX8qm. We need to populate several
resistors to enable the connectors driven by channel1 in single mode
for either ARM2 platform or MEK board. Tests are done with IT6263
LVDS to HDMI transmitter driven by LDB0 channel1 after r206, r207, r208
and r209 are populated on the i.MX8qm MEK board.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch contains code-change-only to improve readability
for helper source_to_id(). Less indents are used.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Pixel clock and vrefresh are important information for a video mode.
This patch adds debug information for them in ->mode_set_nofb.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
After link train completes the link status needs to be checked.
If the link is not "good", then link training must be retried.
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
For channel 0 if 1920x1080@NV12 was used when setting a mode would
freeze the scaler. That's because the chroma vertical size was set to
540 (1920 / 2) instead of 544 (which is divisible to 8).
This patch makes sure we round up the chroma vertical size for channel-0
properly.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
When the VIDEO_PLL2 clock code was moved to the DCSS driver, a
regression was introduced and any mode requiring a 27MHz pixel clock
would instantly freeze the platform.
It turns out, after setting the clocks in bypass mode, PLL_CLKE was
never set. Hence, DCSS was not getting any clock. Without a valid clock,
any attempt to access DTG registers will freeze the system.
This patch:
* sets PLL_CLKE when bypass is used;
* simplifies the pll code a little;
* increases the atomic CRTC enable timeout to 500ms to accommodate the
delay after which the clock is available when bypass is used;
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
CC: Oliver Brown <oliver.brown@nxp.com>
RTRM clock reference was saved in apb_clk, instead of rtrm_clk. Hence,
when blanking and clocks go off, APB clock counter was 2, instead of 1.
Because IRQ_STEER controller uses APB clock as well, the APB clock ref
counter will never go to 0. Unless DCSS is never used.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
After PM_QoS was removed by this commit:
f889273 - MLK-19460-2: drm: imx: dcss: remove PM_QoS
interrupt latency increased. Hence, any video playback using tiled
compressed formats will be affected because DTRC uses CTXLD to switch
its register banks. If CTXLD is not armed, at the right time, the DB
trigger moment will be missed. This leads to DTRC not switch to the other
register bank and scaler will be starved, leading to a channel freeze.
This patch will lower the CTXLD trigger time to 90% of frame trace
allowing some more time between arming the context loader and DB trigger
time, in case the latency is too big.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The eLCDIF controller has control pin for the external LCD reset pin.
Add support for it and assert this pin in enable and de-assert it in
disable.
Also, correct the pm_runtime_enable call, since it was made too early in
the probe, causing issues to DRM enable routines.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
This is an adapter card made for the 4.3", 800x480, LCD panel Seiko
43WVFIG. The LCD panel is a 24bit DPI bus, while the adapter card has
two ports: 18-bit and 24-bit data input. For the 18-bit data input, the
adapter card is demuxing some of the data lines, in order to feed all of
the 24 lines needed by the LCD.
This driver handles both this use-cases.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Add driver for Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480)
TFT with Touch-Panel.
Datasheet available at:
http://www.glyn.de/data/glyn/media/doc/43wvf1g-0.pdf
Seiko 43WVF1G panel has two power supplies: avdd and dvdd and they
require a specific power on/down sequence.
For this reason the simple panel driver cannot be used to drive this
panel, so create a new one heavily based on simple panel.
Based on initial patch submission from Breno Lima.
Signed-off-by: Marco Franchi <marco.franchi@nxp.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1500567179-6967-1-git-send-email-marco.franchi@nxp.com
Pixel combiner uses two display streams to drive one single display.
Either one of the two streams can be master stream and the other
slave stream. If we use stream0 as the master stream, the overlay
covers the two streams could be unsynchronized sometimes. It looks
like there is one frame lag between the two streams. However, it
turns out that using stream1 as the master stream can workaround
this issue.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Sandor Yu