Implemented system suspend resume functions to call hwvad enable/disable
then do runtime_force_suspend/resume.
Since hwvad can run independently, when user calls enable/disable, we
will have to increment/decrement usage counter by calling
runtime_*_sync but to avoid doing this when disable/enable is called
from system_suspend/resume since we called pm_runtime functions - this
is why we have added the sync parameter in enable/disable_hwvad.
However, we ignore the busy flag because the module wasn't designed to
work with arecord and hwvad in parralel and we only print a warning.
Since hwvad and recording share the same clock and initialization
procedures require module to be disabled, the busy flag will be set
when having both features enabled.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
We must find a way to no longer touch resources after they are
cleand up.
Now, after a stress test we get the following crash:
[ 2156.863772] fsl-dsp 596e8000.dsp: xf_pool_alloc failed
[ 2156.869337] Unable to handle kernel NULL pointer dereference at
virtual address 00000060
[ 2157.148594] [<ffff000008d8839c>] _raw_spin_lock+0x14/0x48
[ 2157.153995] [<ffff000008b3e0b8>] xf_cmd_send_recv_complete+0x40/0xf0
[ 2157.160354] [<ffff000008b3e470>] xf_close+0x40/0x88
[ 2157.165239] [<ffff000008b3f7a4>] xaf_comp_delete+0x5c/0x70
[ 2157.170730] [<ffff000008b40530>] dsp_platform_compr_free+0xa0/0xe8
[ 2157.176917] [<ffff000008b287fc>] soc_compr_free_fe+0x144/0x1a0
[ 2157.182754] [<ffff000008b11b24>] snd_compr_free+0x64/0x98
This happens because:
1) dsp_platform_process work handler waits in a loop for
messages to arrive.
2) when cplay process finishes it cleans up most of the
resources.
3) when another cplay process starts it reinitializes the
resources including queues for example.
4) a message will be generated and kernel will crash because
dsp_platform_process uses the older queues.
A solution for this is to make sure dsp_platform_process work loop
is stopped at cleanup time.
We use is_active state and signal dsp_platform_process handler to
finish because we are on the cleanup path.
While at it replace cancel_work with cancel_work sync to be sure
that work handler ends before going on with the rest of the cleanup.
Reviewed-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
The alogrithm ecb(arc4) was registered by the CAAM for all
the platforms however the hardware capability for this algo
is no more present (No CHA).
So we skip its registration.
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
- When OPTEE OS is present and if it support the busfreq
for the running the i.MX, the busfreq is executed in
the OPTEE OS by calling a specific SMC function
- Only a WFE function is copied into the OCRAM to
synchronize all Cores in multi-core devices
- OPTEE OS add a DT property 'busfreq=1' in the 'firmware/optee'
node to indicate the busfreq support
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
According to Hardware test result, when config the usdhc pad io drive
strength to high, there are some overshoot on the clock/data signal
when sd/emmc work at SDR104/HS400/HS200 mode. When change the usdhc
data/cmd/clk pad io strength to low, can't see any overshoot, and
data transfer can also work well and pass the stress test.
So change all the usdhc pad io drive strength to low.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
In order to support 44kHz and 48kHz sample rate together, we need to
reconfigure the parent clock of mclk.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Revert "MLK-17344-2: ARM64: dts: add constraint-rate for hdmi of imx8qm"
This reverts commit 86dbbb61cf.
On imx8qm B0 fix the DPLL jitter issue for HDMI module, so the constraint
for sample rate should be removed
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
There is two methods to select different mode for camera sensor, one
is setting mode by VIDIOC_S_PARM ioctl and the other is automatic
selection through resolution. If resolution match one of camera sensor
supported, driver will select the corresponding mode. If not, driver
will select the max resolution supported by sensor and use ISI to
resize to the target resolution.
This patch is for ov10635 camera sensor
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit 21680ebeebbd2deb0430e0e2df82e3b5ec95c08d)
There is two methods to select different mode for camera sensor, one
is setting mode by VIDIOC_S_PARM ioctl and the other is automatic
selection through resolution. If resolution match one of camera sensor
supported, driver will select the corresponding mode. If not, driver
will select the max resolution supported by sensor and use ISI to
resize to the target resolution.
This patch is for parallel interface of ov5640 sensor
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit 8eb46dab84dd589ba0e6f997e28fa9ff3bbbcd63)
There is two methods to select different mode for camera sensor, one
is setting mode by VIDIOC_S_PARM ioctl and the other is automatic
selection through resolution. If resolution match one of camera sensor
supported, driver will select the corresponding mode. If not, driver
will select the max resolution supported by sensor and use ISI to
resize to the target resolution.
This patch is for mipi interface of ov5640 sensor
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit 4c560890906f7df33e68a65372f60778cb1406b7)
According to V4L2 doc, RGB24 and BGR24 should have three bytes
for each pixel rather than four, so correct it.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit 3694f7ffe2443d86ae740f12393edc007c997a98)
Initialize SCL_IMG_CFG to source image width and height when
scale disabled
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit 506b32bb9ad6a3f596510e401b0e8fa16ca8b659)
Return error code when user try to do upscale since isi don't support.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit 59949e29dcd996c50cae43bc5ff3f89907761c1b)
When ISI channel0 is used to recevice camera data, it can
not be used to mem2mem. So return -EBUSY error code when
user try to use them at the same time.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit c6d5bf866819deaaf4900ae47d575c5a36d30a66)
Power off some resource of ISI can't really hardware reset
ISI, because all eight ISI channels share one hardware reset.
For example, if we enable ISI channel 0 and 1 in dts and only
power off and on channel0 domain, it will not really reset and
the value of channel0 register will not change.
Hardware reset was introduced for fixing ISI can't receive data
from CI_PI after system boot in QXP A0 and this is fixed in new
version QXP B0, so remove HW reset in driver.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit df9da83f82c94ca578303b45c60fb17da2d9d1aa)
Because ISI can't restore to default state after software
reset, the status value of exit will be maintained. If not
cleared, ISI will triggle fake interrupt after enableing irq,
but there is not ready for data.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit 932af3df1745f5afb0b9433d3355b2e24b177f4e)
according to the function disable_irq() description, use disable_irq() in
spin lock context may cause deadlock. So change to use disable_irq_nosync().
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
The PMU's interrupt is PPI. Correct the pmu interrupt parent of i.MX8MQ/MM.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
The 100MTS low bus mode can be only supported by i.MX8MQ Rev2.1 and
future TO. So necessary check is added to identify the chip revision
when doing busfreq mode switch.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
This wakeup setting can enable USB wakeup function even the
controller's power is lost, and both A7 and M4 are in VLLS mode.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
After commit 2911e974c8 ("MLK-19098 ARM: dts: imx7ulp-evk: use OTG
ID function instead of GPIO") , the ID pinctrl is set by chipidea
driver, so we need to restore its setting after system resume
due to pinctrl setting is lost at VLLS state.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
The pinctrl setting may lost during the system suspend
(eg, imx7ulp), we need to restore it after system resume.
Meanwhile, some platforms may need to set special pinctrl
for power comsumption.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
In case of vbus_never_low, if source setup a typye-c only session, sink
time out on waiting for source capability message and send soft reset,
the source does not response by goodcrc for the soft reset message, we
don't do hard reset, but keep a non-PD typec session, because the source
maybe PD capable, this hard reset will make the source terminate the
session by turn off vbus, if this type-c port is the system power supply,
the whole system will reboot.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Add one parameter to distinguish the different ref_clk
source, internal pll or the external osc.
NOTE: The value of the ext_osc should be aligned to the one
of the pcie's, since both of them share one ref_clk source.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Add pio spi slave mode support for imx6ul which is based on the patch
cherry-pick from community(71abd29057).
Because the original imx6ul is bound to mx51 in the dts file.
However, in the slave mode, the patch in the community only adds two
functions mx53_ecspi_rx_slave/mx53_ecspi_tx_slave. Therefore, configure
mx51/6ul to use these two functions for data transmission and reception
in slave mode.
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Previously i.MX SPI controller only works in Master mode.
This patch adds support to i.MX51, i.MX53 and i.MX6 ECSPI
controller to work also in Slave mode.
Currently SPI Slave mode support patch has the following limitations:
1. The stale data in RXFIFO will be dropped when the Slave does any new
transfer.
2. One transfer can be finished only after all transfer->len data been
transferred to master device
3. Slave device only accepts transfer->len data. Any data longer than this
from master device will be dropped. Any data shorter than this from
master will cause SPI to stuck due to mentioned HW limitation 2.
4. Only PIO transfer is supported in Slave mode.
5. Dynamic burst size adjust isn't supported in Slave mode.
Following HW limitation applies:
1. ECSPI has a HW issue when works in Slave mode, after 64
words written to TXFIFO, even TXFIFO becomes empty,
ECSPI_TXDATA keeps shift out the last word data,
so we have to disable ECSPI when in slave mode after the
transfer completes
2. Due to Freescale errata ERR003775 "eCSPI: Burst completion by Chip
Select (SS) signal in Slave mode is not functional" burst size must
be set exactly to the size of the transfer. This limit SPI transaction
with maximum 2^12 bits. This errata affects i.MX53 and i.MX6 ECSPI
controllers.
Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add the missing attribute dmas and dma-names for ecspi1~3 to fix the
following error log.
LOG: spi_imx 30820000.ecspi: dma setup error -19, use pio
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
iMX8MM DDR3L validation board uses FPGA to link with SPI NOR flash with
ECSPI1. Add pin configurations and ecspi1 node to enable ECSPI1 to access
SPI NOR.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
iMX8MM DDR3L validation board uses GD25LQ16 as spi-nor chip, but its
id is incorrect in ids table, so add a new id and parameters with the
same name into the ids table. For the same name of the chip info, the
log following we can ignore.
LOG: m25p80 spi0.0: found gd25q16, expected gd25q16
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Flexspi registers cannot be reset to default value, reset all FLASHxCR2
registers to 0 to avoid read data with invalid LUT commands.
Signed-off-by: Han Xu <han.xu@nxp.com>
Create a new dts 'fsl-imx8mm-ddr4-evk-rm67191.dts' to support
panel 'RM67191' display which is attached to DSIM controller
directly on IMX8MM DDR4 board to avoid conflict with ADV7535
display.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Ranjani Vaidyanathan