Instead of fixed pull up super speed mux selection gpio for cc1, use
GPIO_ACTIVE_HIGH/LOW to map the CC1/CC2 orientation via gpiod api, So
for ss-sel-gpios:
GPIO_ACTIVE_HIGH: CC1 <--> GPIO high
GPIO_ACTIVE_LOW : CC1 <--> GPIO low
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
PxP PS engine support YUV420 format, but not YVU420. The difference
between two format is U and V, if we exchange U and V base address,
the PxP driver can also support YVU420 format.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit cbc71da10a)
A component master may have both OF based and non-OF based components to be
bound with. This patch adds a helper drm_of_component_probe_with_match()
similar to drm_of_component_probe() so that the new helper may get an
additional provided match pointer(contains match entries for non-OF based
components) to support this case.
Tested-by: Meng Mingming <mingming.meng@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
No one is using the list in the dpu plane group, so let's remove it and
the mutex lock which protects the list.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
No one is using the list in the dpu plane group to access dpu plane, so let's
take down dpu plane from the list so that we may remove the list entirely
from where it is defined.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
There are five gpt modules on imx8qm (gpt0 .. gpt4).
Of these, gpt2 and gpt4 clock hierarchies are inconsistent with the
rest.
Having the per clocks (gpt_hf_clk and gpt_clk) as children of the
peripheral access clock (ipg_s) and bus sync slave clock (ipg_slv_clk)
ensures that the latter are enabled when the driver enables the gpt_clk
(or hf).
This patch reconciles these two gpt clock trees with the rest.
Before:
gpt_2_div
gpt_2_hf_clk
gpt_2_ipg_s_clk
gpt_2_ipg_slv_clk
gpt_2_clk
gpt_4_div
gpt_4_hf_clk
gpt_4_clk
gpt_4_ipg_s_clk
gpt_4_ipg_slv_clk
After:
gpt_2_div
gpt_2_ipg_s_clk
gpt_2_ipg_slv_clk
gpt_2_hf_clk
gpt_2_clk
gpt_4_div
gpt_4_ipg_s_clk
gpt_4_ipg_slv_clk
gpt_4_hf_clk
gpt_4_clk
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Some gpt clocks are defined twice which results in:
gpt0_div
gpt0_clk
and also:
gpt_0_div
gpt_0_ipg_s_clk
gpt_0_ipg_slv_clk
gpt_0_hf_clk
gpt_0_clk
The second version is correct as per gpt lpcg cell.
This patch removes the first set of clocks.
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
g2d code has different parameter setting about stride parameter.
For compatibility with all cases of using PxP, we need add this
improved feature.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 53c8ffffec)
If pxp use crop x/y valuse as the upper left coordinate in
out buffer, pxp driver only need to write out buffer base
address to pxp out_buf register. If pxp driver use zero as
ps_ulc register value, pxp out_buf register need an offset
added with out buffer base address.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 14c988f1eb)
For i.MX system controller thermal, when some of the thermal
zones are powered off, the get temp will fail, and thermal driver
will return CPU thermal zone's temp instead. But current driver
will return A53 cluster for all cases, and A53 cluster may be
also off when booting up A72 cluster only, so below error message
will come out:
[ 475.606431] read temp sensor:0 failed
[ 475.610107] thermal thermal_zone0: failed to read out thermal zone (-22)
To avoid this error, for the case of thermal zones power off,
thermal driver can return current thread's CPU cluster temperature.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
i.MX8QM/i.MX8QX USDHC pads are dual voltage pads, and the
defiintation of each bit are different. Only bit[0] define
the drive strength slection, bit[4:1] are reserved.
0 means high drive strength
1 means low drive strength
This patch correct these pad setting, setting the usdhc
100mhz/200mhz pin at high drive strength.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Currently, USDHC do not generate transfer complete interrupt
when send a non-data-command with R1b response. But if want
to support DCMD in CMDQ, need to change this, the DCMD IC
logic require the USDHC to enable this function, otherwise
DCMD will never get a CC(command complete) interrupt.
This patch set ESDHC_VEND_SPEC2_EN_BUSY_IRQ and add DCMD support.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Priority use the callback set_timeout() to set the maximum timeout
if the host has.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
This patch adds CMDQ support for command-queue compatible
hosts.
Command queue is added in eMMC-5.1 specification. This
enables the controller to process upto 32 requests at
a time.
Adrian Hunter contributed renaming to cqhci, recovery, suspend
and resume, cqhci_off, cqhci_wait_for_idle, and external timeout
handling.
Signed-off-by: Asutosh Das <asutoshd@codeaurora.org>
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
Signed-off-by: Konstantin Dorfman <kdorfman@codeaurora.org>
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit a4080225f5)
Add CQE support to the block driver, including:
- optionally using DCMD for flush requests
- "manually" issuing discard requests
- issuing read / write requests to the CQE
- supporting block-layer timeouts
- handling recovery
- supporting re-tuning
CQE offers 25% - 50% better random multi-threaded I/O. There is a slight
(e.g. 2%) drop in sequential read speed but no observable change to sequential
write.
CQE automatically sends the commands to complete requests. However it only
supports reads / writes and so-called "direct commands" (DCMD). Furthermore
DCMD is limited to one command at a time, but discards require 3 commands.
That makes issuing discards through CQE very awkward, but some CQE's don't
support DCMD anyway. So for discards, the existing non-CQE approach is
taken, where the mmc core code issues the 3 commands one at a time i.e.
mmc_erase(). Where DCMD is used, is for issuing flushes.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 1e8e55b670)
Define and use a blk-mq queue. Discards and flushes are processed
synchronously, but reads and writes asynchronously. In order to support
slow DMA unmapping, DMA unmapping is not done until after the next request
is started. That means the request is not completed until then. If there is
no next request then the completion is done by queued work.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 81196976ed)
Until mmc has blk-mq support fully implemented and tested, add a parameter
use_blk_mq, set to true if config option MMC_MQ_DEFAULT is selected, which
it is by default.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit c3d53d0da6)
Make mmc_pre_req() and mmc_post_req() available to the card drivers. Later
patches will make use of this.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit afab1bb8b4)
Use blk_cleanup_queue() to shutdown the queue when the driver is removed,
and instead get an extra reference to the queue to prevent the queue being
freed before the final mmc_blk_put().
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 41e3efd07d)
The following functions are needed by the mmc block device driver, once it
converts to blkmq, therefore let's export them.
mmc_start_bkops()
mmc_start_request()
mmc_retune_hold_now()
mmc_retune_release()
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit cb39f61e9b)
Factor out some common code that will also be used with blk-mq.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit c8b5fd031a)
Currently the host can be claimed by a task. Change this so that the host
can be claimed by a context that may or may not be a task. This provides
for the host to be claimed by a block driver queue to support blk-mq, while
maintaining compatibility with the existing use of mmc_claim_host().
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 6c0cedd1ef)
Adjust for small imx changes in debugfs
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Enhance mmc_blk_data_prep() to support CQE requests. That means adding
some things that for non-CQE requests would be encoded into the command
arguments - such as the block address, reliable-write flag, and data tag
flag. Also the request tag is needed to provide the command queue task id,
and a comment is added to explain the future possibility of defining a
priority.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 93482b3d70)
Use local variables in mmc_blk_data_prep() in preparation for adding CQE
support which doesn't use the output variables.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit d3377c012f)
Enable or disable CQE when a card is added or removed respectively.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit f690f4409d)
Enable the Command Queue if the host controller supports a command queue
engine. It is not compatible with Packed Commands, so make a note of that in the
comment.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 98d4f7809d)
Add core support for handling CQE requests, including starting, completing
and recovering.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 72a5af554d)
As the default data role is device mode if the port is not host,
so set the port data role to be device mode after src detach, this
is to fix the issue of port data role still kept to be host while
the port is open.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
The ESAI0 and AMIX SAIs rates need to be the same for the
common and master clocks in the clock tree given the existing
clock rates store/restore functionality and the asynchronous
nature of the drivers "probe" method invocation.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
AMIX SAIs frequency was doubled in order to
support the [98k rate X 8 channels X 32 bit width].
As consequence the criteria to enforce the rates
constrainsts needs to be changed accordingly.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Previous code don't take care about the i.MX6QP revision update of
new TO. So improve the code to include future TO support for i.MX6QP.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
On our i.MX6 SOC, the DIGPROG register is used for represent the
SOC ID and silicon revision. The revision has two part: MAJOR and
MINOR. each is represented in 8 bits in the register.
bits [15:8]: reflect the MAJOR part of the revision;
bits [7:0]: reflect the MINOR part of the revision;
In our linux kernel, the soc revision is represented in 8 bits. MAJOR
part and MINOR each occupy 4 bits.
previous method does NOT take care about the MAJOR part in DIGPROG register.
So reformat the revision read from the HW to compatible the revision format
used in kernel.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
For video layer, the black pixel value is not 0x0,
but (Y: 0x0, U: 128, V: 128). So init the video
layer frame buffer contents to the black pixel
value by default.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
According to the DCSS spec, the DPR has alignment
limitations for the input source image on both 'x'
and 'y' directions of Luma and Chroma planes. The
DPR has different alignment requirements for
different bpp, tile type, rtram buffer lines and
etc.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
DTG is a standard double buffer module which has
shadow registers. So use double buffer to config
its registers via Context Loader.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Add double buffer Context Loader function support in
DCSS, since some of the submodules have shadow reigsters
which are more suitable to use double buffer context
loader to load the reigster values for them, and double
buffer loadding is earlier than single buffer loading.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
For i.MX8MQ, suspend freq can use policy->max after cpu freq
table is validated, so no need to get OPP number and MAX
frequency for suspend freq now, also add necessary resource free
when probe failed.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
For i.MX8QM/8QXP, suspend freq can use policy->max after cpu
freq table is validated, so no need to get OPP number and MAX
frequency for suspend freq now, also add necessary resource free
when probe failed.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Add SIP cpu-freq support, the CPU hardware frequency
scale will be performed by ARM Trusted Firmware,
and add cpu-freq suspend support, MAX frequency will
be used during suspend.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
