In AUDIO IO board for imx8qxp mek, after board reset, the codec
failed to probe, system can't find codec device on i2c bus.
The reason is not clear, but add reset operation in the beginning of
probe can fix this issue.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
add cases to support resetting the hifi4 codec when receiving
HIFI4_RESET_CODEC command from the user space.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
add reset command declaration into mxc_hifi4.h file,
this command is used to reset hifi4 codec when seeking
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
When abnormal situation occurs and the current process terminates
abnormally, the hifi4 driver can't get the HIFI4_CODEC_CLOSE CMD
from user space to release the multi-codec resource, so the current
resource can't be used again.
Have found that the fsl_hifi4_close() function can be called
implicitly when process terminates abnormally, so add a reference
counter in fsl_hifi4_open() and fsl_hifi4_close() to check this
abnormal situation, when the number is same for opening and closing
hifi4 device, the multi-codec should be reinitialized again and
the hifi4 driver should send ICM_EXT_MSG_ADDR CMD to hifi4 framework
to initialize the multi-codec resources too.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
- Init mu power and clk.
- Change the cycles of the pingpong demot refer to
the limitation of M4 side.
When the received data larger than 100, the
pingpong of M4 side would be finished.
BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
enable imx8qm rpmsg support, and validated the
pingpong demo.
add the mu power and clk on imx8qxp.
BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Since commit 3f5780eb4520 ("MLK-16538-2: hdmi api: Relocate hdmi api
soure code") change the api. And hdmi video driver provide a new api
for hdmi audio. Machine driver need to be updated accrodingly
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Add hdmi/dp drm architecture driver.
HDMI and DP driver can work in imx8qm ARM2 board.
The driver support basic hotplug function.
Default working mode is 1080p60.
Acked-by: Robby Cai <robby.cai@nxp.com>
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
-Relocate hdmi api source code from drivers/video/fbdev/mxc/cdn_hdp
to drivers/mxc/hdp.
-Add displayport and hdcp api function.
-Move t28hpc_hdmitx function from api source code folder
to hdmi fb driver folder.
-Update imx8 hdmi fb driver according api source code change.
-Sync api source code with CDN_API_1_0_33 release.
Acked-by: Robby Cai <robby.cai@nxp.com>
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
This patch causes imx8-pd nodes marked with status = "disabled" to be
ignored. This is very common in devicetree handling.
When running with xen the hypervisor will convert all xen,passthrough
properties to status = "disabled" before passing dtb to dom0. This patch
allows power domains to be marked this way and have them be ignored by
the host automatically.
The alternative is to remove the power domain nodes and references using
/delete-node/ and /delete-property/ and that gets messy.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Right now the imx8qm clock provider hardcodes physical addresses. In
virtualization scenarios the intermediate physical addresses visible
from a guest can be different. In theory a 1:1 mapping could be done but
that in xen it would overlap with hardcoded guest ram starting at
0x40000000.
Solve this by adding a property with a common offset for all lpcg
areas. This should be set in the guest dts.
In theory each lpcg block could be remapped with it's own offset but
that is not supported.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
Registering clocks for unowned resources can result in lots of pointless
scfw errors and potential faults when attempting to use LPCG.
Solve this by checking ownership via sc_rm_is_resource_owned and
returning -ENODEV from clock registration functions. The top-level clock
provider is also modified so that it accepts such errors silently.
This is intended for xen but could also be useful for SCFW partitioning.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
All this does is replace the cast from physical address with a macro in
order to make later changes easier.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
This can happen in virtualization scenarios, so just skip registering
the associated clocks instead of failing to boot.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
Adds dt settings for the dpu driver to set the default clock
parents
- PLL1 (dc0_pll0_clk) for dispay0 and PLL2(dc0_pll1_clk) for display1.
Functionality is not changed from dpu driver perspective as the same
parents for the display clocks were used before.
The resulting clock topology for dc0_disp1 is:
dc0_pll1_div 1 1 1188000000 0 0
dc0_pll1_clk 2 2 1188000000 0 0
dc0_disp1_sel 1 1 1188000000 0 0
dc0_disp1_div 1 1 148500000 0 0
dc0_disp1_clk 1 1 148500000 0 0
(BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0)
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Reviewed by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
DC clocks can choose their clock source between PLL1, PLL2 and
bypass input.
This patch introduces a multiplexer in the dc clock topology to
allow this choice and introduces one set of parents that will be used
for both display0 and display1 clocks.
Clock paths tested:
1. PLL2(dc0_pll1_clk)->DC0_DISP1(dc0_disp1_clk)->LVDS
2. BYP(dc0_bypass0_clk)->DC0_DISP1(dc0_disp1_clk)->LVDS
(BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0)
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Reviewed by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
Display clocks can choose their parrent between various clock sources
(ex pll1, pll2, bypass).
This patch adds a new mux type that uses the underlying support in scfw
to set/get a parent.
(BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0)
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Reviewed by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
Use 'struct kref' type for 'refcount' field instead of
'atomic_t' to take advantage of 'kref_*()' interface
series. The benefit to do so can improve the defered
cfifo flush performance, since this defered flush does
not need to wait to be done until next vsync happens.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
After changing the strategy to 'flush cfifo once per frame',
the cfifo wrapping handling should also be changed accordingly.
Now, when it is found that the cfifo has no enough room from 'in'
to the buffer end to hold the current commit, the 'commit_cfifo'
will cancel this commit and flush the cfifo workqueue before
restart the commit again.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
The correct return value for 'dcss_wait_for_vsync()' when
it executes successfully should be '0'. But this current
value now gets from 'wait_event_interruptible_timeout()'
which returns non-zero value when the wait is not timeout.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Change the cfifo flush to be once per frame to combine
possible multiple flush requests in one frame into one
flush to improve performance. And during one frame, only
flush requests from different channels can be combined,
and the different requests from the same channel cannot
be combined into one flush.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
The function 'dtg_irq_mask()' is not used at this
moment which caused gcc compiler generate the build
warning:
"‘dtg_irq_mask’ defined but not used [-Wunused-function]"
So add attribute '__maybe_unused' to 'dtg_irq_mask()'
functon definition to avoid this build warning.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Unmask the 'IRQ_TC_LINE1' when initialize it by default,
since the vsync count can be used as a reference count or
timestamp.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
The variables 'cinfo' and 'chan_info' both refer to the
same 'struct dcss_channel_info' data. So remove 'chan_info'
and its related variables to make code more clean.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
The 'ctxld_list' is more closely related to 'struct ctxld_info'
structure. So moving its definition to this structure is more
reasonable.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Abstract the cfifo workqueue flush operation to a separate
interface 'finish_cfifo()'.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
This commit split the function 'commit_to_fifo' into three
parts: 'alloc_cc()', 'commit_cfifo()' and 'flush_cfifo()'.
So that each of the three parts can be used as required,
but not used all together.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
The 'ctxld_wq' is more closely related to 'struct ctxld_info'
structure. So moving its definition to this structure is more
reasonable.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Abstract the process that copy data from 'cb' to 'cfifo'
to a separate function from 'commit_to_fifo()'. This is
a refinement.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
When doing ctxld config, the 'esize' variable is already
assigned to the value derived from 'kfifo_esize()'. So
using the exsiting value instead of deriving it again.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
The 'esize' is better be got by 'kfifo_esize()'
instead of using 'sizeof' to make the code more
compatible and easier to unserstand.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
The kfifo 'out' points to the first byte of data to be
consumed next time. So use it to get the data offset to
be accessed by CTXLD and remove unused field 'fifo_in'
from 'struct ctxld_commit'.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Both host and device mode are support, and the port is at base board.
Below rework is needed:
Remove R145, R143, R1390, and install R144, R142, R1389.
BuildInfo:
- SCFW 1f59442e, IMX-MKIMAGE fb52c576, ATF
- U-Boot 2017.03-imx_v2017.03+g34be5a2
Acked-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Add TCPCI device NXP PTN5110 as well as USB3 port support, they are
disabled by default due to board rework is needed, it needs to
replace U182 from NTB0104 to NTS0104, please consult hardware team
for detail.
Without rework, but enable USB3 will cause endless of PTN5110 interrupts
due to voltage of ALERN_N from PTN5110 is incorrect.
BuildInfo:
- SCFW 1f59442e, IMX-MKIMAGE fb52c576, ATF
- U-Boot 2017.03-imx_v2017.03+g34be5a2
Acked-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
At probe, the main hcd is added first, then shared_hcd is added later,
so when we tries to remove hcds, the shared_hcd needs to remove first.
BuildInfo:
- SCFW 1f59442e, IMX-MKIMAGE fb52c576, ATF
- U-Boot 2017.03-imx_v2017.03+g34be5a2
Acked-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
When it goes to start new role, the interrupt may be occurred before
role_start returns, but at this time, the cdns->role is still the old
role, so the interrupt handler will make mistake.
In this commit, we set desired role before role_start, if the role_start
has failed and the desired role is different with current one, it tries
to back current role.
BuildInfo:
- SCFW 1f59442e, IMX-MKIMAGE fb52c576, ATF
- U-Boot 2017.03-imx_v2017.03+g34be5a2
Acked-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
This is a change similar to:
'commit 01fdf7bf572b ("MLK-16281-2: clk-imx8qm: Fix GPT clock hierarchy")'
There are five gpt modules on imx8qm (gpt0 .. gpt4).
Of these, gpt2 and gpt4 clock hierarchies are inconsistent
with the rest.
Having the per clocks (gpt_hf_clk and gpt_clk) as children of the
peripheral access clock (ipg_s) and bus sync slave clock
(ipg_slv_clk)
ensures that the latter are enabled when the driver enables the
gpt_clk
(or hf).
This patch reconciles these two gpt clock trees with the rest.
Before:
gpt_2_div
gpt_2_hf_clk
gpt_2_ipg_s_clk
gpt_2_ipg_slv_clk
gpt_2_clk
gpt_4_div
gpt_4_hf_clk
gpt_4_clk
gpt_4_ipg_s_clk
gpt_4_ipg_slv_clk
After:
gpt_2_div
gpt_2_ipg_s_clk
gpt_2_ipg_slv_clk
gpt_2_hf_clk
gpt_2_clk
gpt_4_div
gpt_4_ipg_s_clk
gpt_4_ipg_slv_clk
gpt_4_hf_clk
gpt_4_clk
Apply this change for imx8qxp also which has the same inconsistency
regarding the gpt clocks.
(BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE imx8-mu, ATF 0)
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Shengjiu Wang