In TDM mode with Daisy Chain enabled (CPLD mode 0x04) DAC1 and DAC2
AK4458 codecs on audio board are able to play 16 channels, so extend
the TDM mode constraint to 16 channels.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit bc8b6a74175c2d120383875b00b5a2a44def9dd0)
Enable Daisy Chain if in TDM mode and the number of played
channels is bigger than the maximum supported number of channels.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 5ae97f159bfd9c4a37e7e60cd20aa3437041b251)
Fix memory out of bounds access.
Change arry type for functopn avi info frame,
Align the arry type and its length.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit 2fc41a88c9da514ae3f377e7cb73f4df886f038e)
start code
Adjust update stream function for the format that need add start code
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
(cherry picked from commit 3b29245bc201f1090e46c70ca60e61093e27675e)
firmware commit patch:
1. report uStrBuffWrPtr and uFrameSize
2. don't append any eos nal
driver do some change to adapt the firmware's change
and use scnprintf instread of snprintf
Signed-off-by: ming_qian <ming.qian@nxp.com>
Similar with QXP MEK we switch to ASRC to support
multiple rates.
Thus we introduce:
- asrc clocks
- make asrc PD depend on esai PD
Reviewed-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry picked from commit d804a5cac96d7d6071a2b4808a6ebe262f20952c)
DCSS needs special display timings for MIPI-DSI panel in order to do a
proper display on it.
In order to not break other display controller using this panel, add
custom display-timings for this specific use-case
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The root cause of the on-the-fly switch from tile to linear fb switch issue
is identified, so the full modeset workaround is no more needed.
Patch "MLK-20506 gpu: imx: imx8_dprc: Set CROP_ULC_X/Y to be zero for linear fb"
is the correct fix for this issue.
Revert "MLK-20470 drm/imx: dpu: plane: Do full modeset for tile to linear fb switch"
This reverts commit 9245bbf650fdeb79ebf869d48b6bd1b43c2bcf3b.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 7812bebe9c60a6ce954ce5ad504a6be002835462)
Nonzero CROP_ULC_X/Y are only valid for tile framebuffer cropping.
Thus, we should set them to be zero for linear framebuffer, otherwise,
an on-the-fly switch from tile framebuffer(with cropping enabled) to
linear framebuffer would cause hardware malfunction.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 4fc67aed944526545e6ee44d582b013a6327c8d1)
- Since the l1ss is not enabled yet, configure
the clkreq# as gpio on 8qm/qxp mek boards.
Re-configure the clkreq# as input and open
drain when l1ss is enabled later.
- Correct the perst# configurations of 8qm.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
(cherry picked from commit cb7ec372ae90798a46b11e979243c3f058d8b26f)
Correct the interrupt line for adv7535.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Acked-by: Fancy Fang <chen.fang@nxp.com>
This is a work-around for the shifted display issue when using DCSS with
the DDR self-refresh disabled.
Also, make sure it works with LCDIF as well.
Increasing VSYNC length gives DCSS more time to fetch the data from RAM
before the next frame kicks in.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit 3c53532c466add234ac3ca2e70cefe80ea308b4f)
When the master imx-drm-core binding fails, component_bind_all()
in imx-drm-core ->bind() callback will unbind all bound components
first and then call drm_mode_config_cleanup(). Since the encoder
and connector(located in imx_ldb.imx_ldb_channel) are freed after
the ldb ->unbind() callback, drm_mode_config_cleanup() would
accidentally access the freed encoder and connector again. To fix
this issue, we should cleanup the encoder and connector, i.e.,
remove them from the global encoder and connector lists, in the
->unbind() callback, so that, drm_mode_config_cleanup() won't find
them again in the lists. However, we have to make sure they exist
before the cleanup in the ->unbind() callback, because imx-drm-core
->unbind() calls drm_mode_config_cleanup() first and then unbinds
all components via component_unbind_all(). Moreover, the connector
isn't created at the first place if a bridge exists, so the check
before the cleanup makes sense for this reason as well.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 6d3fd1316d67ff0e62fae4067b61fd3f2809dfa5)
The dpu_plane is allocated with kzalloc() in dpu_plane_init().
In case, dpu_plane_init() fails after that allocation, the bailout path
should free the dpu_plane, otherwise, there will be memory leakage.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 99cb80f855aafbe524519db635c3d03bd4cc8d85)
1.avoid illegal wptr, rptr, start and end.
2.function show_instance_info is too long, split it into several small
functions
3.export dma detail info
Signed-off-by: ming_qian <ming.qian@nxp.com>
We enable the ASRC clocks from CPU side. We only need
the following clocks: "mem", "ipg" and "asrc0..3".
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 586297d7d5855cf75e25f629ca495b8ac5c1bb96)
Because now DSP supports ASRC we need to power up pd_asrc0
each time pd_esai0 is powered up.
Current power domain tree looks like this:
* pd_audio
* pd_audio_clk0
* pd_audio_clk1
* pd_dma0_chan6
* pd_dma0_chan7
* pd_esai0
* pd_dma0_chan0
* pd_dma0_chan1
[....]
* pd_asrc0
We need to make pd_asrc0 dependent on pd_esai0, thus we move
pd_dm0_chan6 node as a child of pd_asrc0.
Thus, the new power domain hierarch will look like this:
* pd_audio
* pd_audio_clk0
* pd_audio_clk1
* pd_dma0_chan0
* pd_dma0_chan1
[....]
* pd_asrc0
* pd_dma0_chan6
* pd_dma0_chan7
* pd_esai0
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 04c4825baad9344e5f3dfa1c69de3957199d3ab0)
We introduce ASRC clocks (only "ipg", "mem", "asrc0..3" are
relevant for us), then remove ASRC related EDMA channels and
interrupts lines because they will be managed by DSP.
There is one more step required: fire up the power domain for ASRC
this is tricky and will be done in the next patch.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit e9e613dc18a732e82227028f1c822862448ddc22)
Once 32Khz low power clock enable for Murata 1CQ module, Bluetooth core
may enter low power idle status that cause HCI communication error when
HCI device is down for 2 seconds after initialization.
Currently, remove the LP 32Khz input for the module.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
The current keep-alive check mechanism uses a static variable
that is initialized to 0. When the function is first called, it may
happen to catch the 8-bit keep-alive counter right when it
overflows, hence returning BUSY.
This patch will keep checking the counter for 10us, every 1us,
but it will immediately return if the keep-alive counter changed.
Signed-off-by: Laurentiu Palcu<laurentiu.palcu@nxp.com>
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit 4ad828b95e78a652f509110688a6f907fc286ea9)
Correct the pad confirations of the pcie perst and epdev_on
on 8qm/qxp platforms.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit 28d5b68c1fa7568a2444915b71fab12e8a2d4350)
hal/kernel/gc_hal_kernel_command.c: In function gckCOMMAND_Commit:
hal/kernel/gc_hal_kernel_command.c:2718:1:
error: the frame size of 2288 bytes is larger than 2048 bytes [-Werror=frame-larger-than=]
removed _commandBufferObject instrance, use kmalloc to avoid kasan error.
Date: Jul 13, 2017
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
(cherry picked from commit d8d57e43a24bd02b375d7c6bd633ed236db19337)
(cherry picked from commit 484e3073adf47d27581482f268b01fe5fe219d18)
Add DRM_VIV_GEM_VIRTUAL_POOL flags.
Switch to virtual pool when this flag is set.
Change-Id: I6e1e799cd0b4f81ed1ffbfdabe8f105325fa9644
Signed-off-by: Ivan.liu <xiaowen.liu@nxp.com>
(cherry picked from commit c4bd0fc803409c54d06e3554f4857922d6640925)
When an atomic commit contains an active CRTC with no plane,
it may cause two potential issues:
First, this CRTC will fetch its last attached plane data
or has no data can be fetched depending on the plane
driver's atomic_disable() implementation.
Second, this CRTC's 'plane_changed' will be false during
the whole commit tail stage, and this will make vblank
wait to be bypassed which directly causes the later wait
flip done timeout.
So add this commit case check to the LCDIF CRTC's atomic
check to block this kind of commits.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 67ced65259a4dbf040ce4a931325be6ba97e5131)
When pixel combiner is used, it turns out that on-the-fly switch from
tile framebuffer to linear framebuffer would cause hardware malfunction
- right half display would be missing and master&slave content shadow
load done event won't come. Thus, go for a full modeset as a workaround.
Note that we check if the original framebuffer is tile or not for both
primary and overlay planes. So, this could be over-kill. The issue was
found when we use 32bit GPU super tile as the original framebuffer on the
primary plane(restart Weston frequently). However, since we usually
don't do this kind of switch in real graphics, it should be fine.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 9245bbf650fdeb79ebf869d48b6bd1b43c2bcf3b)
ISI channel 0,1 or 2,3 could concatenate to support 4K image.
ISI channel 1,2 couldn't support such function,
otherwise image will lost line data.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit 18d3cf890a41ac773aefddd2ebe285d4b0197f5d)
1. get boot size and rpc size from dts file
2. set p[18]=1 in vpu_firmware_download()
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
(cherry picked from commit b859b67f2cc6ea05ece69294a960e85eb198d61e)
Adding more statistic info for debug
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
(cherry picked from commit ebef17b0a54a307a5f98d5912a7848b922bb863d)
1. Add dma memory counting
2. Delay the free of instance file when firmware hang
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
(cherry picked from commit 431eb4f32b31ef82500c2405c690775c6eb87d33)
update function
1. Modified EOS filling size
2. add mb() before function rpc_update_cmd_buffer_ptr and
rpc_update_msg_buffer_ptr
3. modify some log print function
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
(cherry picked from commit b58bbfe0e75568e7f3104589a06519d1eaddb01a)
Register setting for ov5640 30fps is the same with 15fps, so
correct it
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
(cherry picked from commit 80b4f71476ffa3f45de01ccbac88fb131a3c444c)
Keep wlreg_on regulator on during system suspended status due to
external wifi module power requirement. Also keep the old Murata
1CQ M.2 card support.
To set the PIN to "latch" status before the GPIO controller is power
off during suspend, and set the PIN to "PASS" status after GPIO
controller status restored during system resume back.
Reviewed-by: yang.tian <yang.tian@nxp.com>
Tested-by: yang.tian <yang.tian@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit: 015599e40fd5cc942f8f6a8d4b6c3475440a114e)
1.get frame size from uFrameSize reported by frame_done event
2.strip stuff data at the end of frame
3.avoid merging two frames into one
Signed-off-by: ming_qian <ming.qian@nxp.com>
This patch fixes the interrupts used by ADV7535. Initial patch
configured the GPIO0 IO00 as IO pin for the DSI_INT, used by ADV7535,
but the correct one is IO01, since IO00 is used by PWM.
Fixes: c2f1eceb5629 ("arm64: dts: imx8qm/qxp mek: Configure interrupts
for adv7535")
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
The system can be wakeuped only when system is totally suspend, when the
wakeup event comes during suspend will cause the system hang. For the reason
that CAN will not call flexcan_noirq_resume() callback if the wakeup event
comes before noirq suspend stage.
The way to fix the issue is that assure the system to call
flexcan_noirq_suspend() during suspend and then call
flexcan_noirq_resume() during resume.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
When dev->power.can_wakeup set to true, device_prepare() may runtime resume the device:
dpm_suspend_start()
dpm_prepare(state);
dev->driver->pm->prepare()
pm_genpd_prepare()
if (resume_needed(dev, genpd))
pm_runtime_resume(dev);
And imx8qm/qxp power domain driver don't implement the active_wakeup() callback, then
resume_needed() always return "true" when dev->power.can_wakeup is true.
Once CAN device is runtime active status, then CAN's clock's count is 1 during system
suspend. And CAN0/CAN1/CAN2 share the same module clock, so we can say all CAN's module
clock is enabled during system suspended.
flexcan_runtime_resume()
flexcan_clks_enable(priv);
i.MX8QM/QXP SCU code clock logic requires linux kernel clocks should be disabled during
suspend, otherwise SCU don't enable them after system resume back.
There are two ways to fix the issue:
1. CAN driver should check the runtime status to ensure all clocks are disabled during
system suspend.
2. Don't set CAN wakeup capability during probe, move it into flexcan_open().
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
M4 will run flexspi XIP image on iMX8MM. Thus, we have to disable flexspi
in M4 dedicated DTS, otherwise the M4 will crash because flexspi probe
in kernel will re-configure the controller.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
(cherry picked from commit 2a370901a663bb518303ed2d5e774f1faa41f5fd)
Viorel Suman