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Code Packages Releases Activity

Added config files for IP blocks

master
gaurav 2022-07-11 20:56:23 +02:00
parent fb4f9776d1
commit 969b98679d
6 changed files with 35 additions and 0 deletions
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5
FPGA_Firmware/Source/src/csi_dphy.cfg 100644
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{
"CLK_MODE": "DISABLED",
"INT_FREQ": 200.0,
"NUM_LANE": 2
}

4
FPGA_Firmware/Source/src/dphy_dummy.cfg 100644
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{
"CLK_MODE": "DISABLED",
"INT_FREQ": 40.0
}

7
FPGA_Firmware/Source/src/line_ram_dp.cfg 100644
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{
"REGMODE": false,
"WADDR_DEPTH": 2048,
"RDATA_WIDTH": 24,
"WDATA_WIDTH": 24,
"RADDR_DEPTH": 2048
}

7
FPGA_Firmware/Source/src/out_line_ram_dp.cfg 100644
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{
"REGMODE": false,
"WADDR_DEPTH": 2048,
"RDATA_WIDTH": 32,
"WDATA_WIDTH": 32,
"RADDR_DEPTH": 2048
}

6
FPGA_Firmware/Source/src/rom_first.cfg 100644
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{
"REGMODE": false,
"RDATA_WIDTH": 16,
"RADDR_DEPTH": 4096,
"user_init_file": "..\\source\\csi_16_nx\\rom_first.mem"
}

6
FPGA_Firmware/Source/src/rom_sec.cfg 100644
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{
"REGMODE": false,
"RDATA_WIDTH": 16,
"RADDR_DEPTH": 4096,
"user_init_file": "..\\source\\csi_16_nx\\rom_second.mem"
}