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Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
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Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
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Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
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Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
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2022-04-03 03:52:35 -06:00
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Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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2022-04-03 03:52:35 -06:00
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Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
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Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
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Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
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Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
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Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
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Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
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Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
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Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(symbol "power:GND" (power) (pin_names (offset 0)) (in_bom yes) (on_board yes)
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(effects (font (size 1.27 1.27)) hide)
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(effects (font (size 1.27 1.27)) hide)
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(effects (font (size 1.27 1.27)) hide)
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(property "ki_description" "Power symbol creates a global label with name \"GND\" , ground" (id 5) (at 0 0 0)
(effects (font (size 1.27 1.27)) hide)
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(symbol "GND_1_1"
(pin power_in line (at 0 0 270) (length 0) hide
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 39.37 62.23) (diameter 0) (color 0 0 0 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(uuid 09ff8530-714c-45c9-8c7a-26c93d48c5d9)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 118.11 50.8) (diameter 0) (color 0 0 0 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(uuid 0b0331f0-ad6e-45d6-b767-0f62f575797e)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 31.75 132.08) (diameter 0) (color 0 0 0 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid 0d486e1b-ec2a-4c13-b68c-5a8bc7fbed29)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 212.09 87.63) (diameter 0) (color 0 0 0 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(uuid 175a04b6-29eb-4bba-9e0a-ea2dc8a0d5c6)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 147.32 90.17) (diameter 0) (color 0 0 0 0)
(uuid 2167914f-5a09-48d1-bf16-0d85b2aaceb9)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 215.9 87.63) (diameter 0) (color 0 0 0 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(uuid 241141d8-eefb-4ed3-afda-7ac5b7738674)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 31.75 142.24) (diameter 0) (color 0 0 0 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid 29c84d61-59a9-4bce-97ae-96a4ad953873)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 143.51 115.57) (diameter 0) (color 0 0 0 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(uuid 2d2b0ba7-c42a-4ac0-aaa7-6cfe551f55da)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 165.1 95.25) (diameter 0) (color 0 0 0 0)
(uuid 32044e18-85d1-4706-8be5-fb03a25cd02b)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 184.15 45.72) (diameter 0) (color 0 0 0 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(uuid 324e688a-1843-4d60-88cb-75de623baa87)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 148.59 118.11) (diameter 0) (color 0 0 0 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(uuid 356144dc-a0fe-4fdc-8eb3-888b5b3a8703)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 80.01 143.51) (diameter 0) (color 0 0 0 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(uuid 392d2075-8af3-405f-aa66-719b5a8b3345)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 184.15 53.34) (diameter 0) (color 0 0 0 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(uuid 3b8b8703-9053-44ea-a92f-4d0312c39d01)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 69.85 143.51) (diameter 0) (color 0 0 0 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(uuid 3e9126e9-870f-46f4-88af-ab6b54b7d9d4)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 147.32 45.72) (diameter 0) (color 0 0 0 0)
(uuid 427d6d42-73ac-429e-beec-8a00fbbc3672)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 151.13 120.65) (diameter 0) (color 0 0 0 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(uuid 46a8550f-d8e2-43f8-8d59-e9d4f2664656)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 55.88 50.8) (diameter 0) (color 0 0 0 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(uuid 4715e7b9-561c-433a-a8f4-013152e129cb)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 184.15 149.86) (diameter 0) (color 0 0 0 0)
(uuid 4881581d-dd9d-4882-93df-984b5b3f8000)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 80.01 153.67) (diameter 0) (color 0 0 0 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(uuid 4d819a31-f9aa-4662-a958-7d3cc3434aa9)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 46.99 50.8) (diameter 0) (color 0 0 0 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(uuid 53809074-8db8-4e18-a150-120940309410)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 191.77 60.96) (diameter 0) (color 0 0 0 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(uuid 60b9792a-cb51-4b9a-8bbb-65b72527665d)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 266.7 69.85) (diameter 0) (color 0 0 0 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(uuid 667c348a-d139-4b04-acb5-5645964ed3b9)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 31.75 139.7) (diameter 0) (color 0 0 0 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid 7d551cc8-80c5-40d0-a988-3a7d0922c903)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 146.05 90.17) (diameter 0) (color 0 0 0 0)
(uuid 7e1fc2da-0376-4ca7-84ae-1285de9a59db)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 212.09 105.41) (diameter 0) (color 0 0 0 0)
Fix connection of INITN and DONE Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-06 10:10:52 -06:00
(uuid 811cd69f-4dd8-47a7-a303-0ca36cee248f)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 105.41 62.23) (diameter 0) (color 0 0 0 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(uuid 82494344-2f2c-4de0-a7fd-72a6a0647225)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 176.53 68.58) (diameter 0) (color 0 0 0 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(uuid 8a5d9b85-7762-4fea-840d-0540048f2180)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 234.95 45.72) (diameter 0) (color 0 0 0 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(uuid 8ab6a98d-3da8-4eae-b246-010cfaacbb09)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 278.13 81.28) (diameter 0) (color 0 0 0 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(uuid 8c315a62-8d5b-41dc-9589-396ebc61c194)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 39.37 50.8) (diameter 0) (color 0 0 0 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(uuid 900f2a37-e72f-479b-816d-6716ba4b9f27)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 31.75 149.86) (diameter 0) (color 0 0 0 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid 9d835ca6-eab2-430e-8507-201b163d4a71)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 274.32 69.85) (diameter 0) (color 0 0 0 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(uuid 9e618698-f1bc-4f78-9b97-92aace28e15f)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 86.36 137.16) (diameter 0) (color 0 0 0 0)
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(uuid a844a060-e560-4c5a-af7b-0b1046e597fb)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 219.71 102.87) (diameter 0) (color 0 0 0 0)
Fix connection of INITN and DONE Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-06 10:10:52 -06:00
(uuid aa77a0ad-aac3-4734-9015-ed94cd1af9fe)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 69.85 45.72) (diameter 0) (color 0 0 0 0)
(uuid b1287f0b-15dc-4aff-95ca-f8f6761735fc)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 146.05 113.03) (diameter 0) (color 0 0 0 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(uuid b3b4c6a7-8aed-449d-a3f9-7a1bcb3e39ce)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 215.9 45.72) (diameter 0) (color 0 0 0 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(uuid bed2f8e2-b64f-4424-97ef-13e997f59ce2)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 219.71 87.63) (diameter 0) (color 0 0 0 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(uuid caf935bd-1e71-41ca-84e2-5c51f56be8a2)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 208.28 105.41) (diameter 0) (color 0 0 0 0)
Fix connection of INITN and DONE Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-06 10:10:52 -06:00
(uuid cd7a2132-bd59-4811-9e89-d10c1bfed2df)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 185.42 63.5) (diameter 0) (color 0 0 0 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(uuid dd70b6df-d559-40a7-bc3b-c233ac555e02)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 148.59 90.17) (diameter 0) (color 0 0 0 0)
(uuid e8355d78-9231-436c-951b-14a714174e3a)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 91.44 134.62) (diameter 0) (color 0 0 0 0)
(uuid f5d947e0-1a40-4be1-b537-55484539f42b)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 165.1 45.72) (diameter 0) (color 0 0 0 0)
(uuid f6140a48-676c-466c-892d-90e0c1252456)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 109.22 50.8) (diameter 0) (color 0 0 0 0)
(uuid f6e24a42-e21b-4472-a53f-0c68bf5b725c)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 118.11 45.72) (diameter 0) (color 0 0 0 0)
(uuid fcce69bc-33c3-4996-ba5b-c1eda94e7634)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(junction (at 184.15 66.04) (diameter 0) (color 0 0 0 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(uuid fdb404c9-5607-4f4e-961f-aaa1814b16ca)
)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(no_connect (at 43.18 76.2) (uuid 0087fb22-ba0c-4acc-b8bc-9fdd9623d4bf))
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(no_connect (at 43.18 109.22) (uuid 0d616157-6bdf-45aa-bced-1021f97957e2))
(no_connect (at 43.18 101.6) (uuid 0d616157-6bdf-45aa-bced-1021f97957e3))
(no_connect (at 43.18 104.14) (uuid 0d616157-6bdf-45aa-bced-1021f97957e4))
(no_connect (at 43.18 106.68) (uuid 0d616157-6bdf-45aa-bced-1021f97957e5))
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(no_connect (at 43.18 139.7) (uuid 20d1812c-cd35-4c64-908b-bbd37c456360))
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(no_connect (at 105.41 116.84) (uuid 532043c0-7b92-4671-9c04-5a267bef43fd))
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(no_connect (at 43.18 88.9) (uuid 8511434d-1111-416b-b59e-7f7fab3537d6))
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(no_connect (at 43.18 73.66) (uuid 9ec70d98-75ce-4ab7-9e1f-60ef736cb193))
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(no_connect (at 105.41 121.92) (uuid a0a81c39-62ab-483b-92e8-438842cf19fc))
(no_connect (at 43.18 91.44) (uuid a5f92b36-b8f4-4a10-90da-5695567ef3ec))
(no_connect (at 105.41 83.82) (uuid b1011abf-258e-4cab-a44d-332b4651c3f5))
(no_connect (at 254 115.57) (uuid be7de968-33ef-4f91-8b12-f0d3a2050b4c))
(no_connect (at 105.41 93.98) (uuid c5674969-13d8-40d2-99ca-df9adcd5445d))
(no_connect (at 105.41 127) (uuid c6c4013d-3700-4ed7-9261-acfb9c8eeaa7))
(no_connect (at 105.41 88.9) (uuid cdd6a1ea-c980-432f-ae87-d2e371cec527))
(no_connect (at 43.18 121.92) (uuid d2a1dfde-6514-44a0-868d-aeae5393d2b9))
(no_connect (at 254 138.43) (uuid d5984c9f-d7d6-4880-9ccf-8cd0f0739db2))
(no_connect (at 43.18 99.06) (uuid d6e25b57-4f73-4a9e-96e1-2afe3109a444))
(no_connect (at 254 113.03) (uuid dc7a756e-09f4-4e54-84a6-91b102dbd2de))
(no_connect (at 254 118.11) (uuid e08881a7-ea9c-46a7-bd76-7c0809750c00))
(no_connect (at 43.18 78.74) (uuid e3394ed9-1c21-4e5c-bcea-5e971d8a7cf7))
(no_connect (at 254 140.97) (uuid ede8c8b8-df9b-4773-bea5-99eda1e39312))
(no_connect (at 105.41 142.24) (uuid f3e9a2b1-bb51-4ad1-8079-e7d788831e63))
(no_connect (at 43.18 119.38) (uuid f5ab30bd-8933-4d63-90be-5a945f7dcc81))
(no_connect (at 43.18 132.08) (uuid f62364e9-06e8-4878-a9f6-c9fb562d98a1))
(no_connect (at 43.18 111.76) (uuid f76de2de-56c9-4236-84f0-f5b7fc28e87a))
(no_connect (at 105.41 101.6) (uuid fdcc1581-186c-4c19-b4e5-135f15587d55))
(bus_entry (at 243.84 123.19) (size 2.54 2.54)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus_entry (at 132.08 120.65) (size 2.54 -2.54)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus_entry (at 243.84 118.11) (size 2.54 2.54)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus_entry (at 243.84 120.65) (size 2.54 2.54)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus_entry (at 132.08 115.57) (size 2.54 -2.54)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus_entry (at 132.08 118.11) (size 2.54 -2.54)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
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Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus_entry (at 134.62 110.49) (size -2.54 2.54)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
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Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus_entry (at 243.84 133.35) (size 2.54 2.54)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus_entry (at 243.84 90.17) (size 2.54 2.54)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 143.51 90.17) (xy 146.05 90.17))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 165.1 95.25) (xy 166.37 95.25))
(stroke (width 0) (type default) (color 0 0 0 0))
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(wire (pts (xy 26.67 142.24) (xy 31.75 142.24))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 58.42 45.72) (xy 69.85 45.72))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 234.95 45.72) (xy 266.7 45.72))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 246.38 120.65) (xy 256.54 120.65))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 151.13 120.65) (xy 152.4 120.65))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 106.68) (xy 107.95 106.68))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 26.67 132.08) (xy 31.75 132.08))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 0923fc8c-f40c-4491-87fe-a32c6de91bcd)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 227.33 87.63) (xy 219.71 87.63))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 098da118-9076-4855-b433-1fb81c3b9831)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 251.46 95.25) (xy 256.54 95.25))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 0a0efa78-3dbd-44e2-9cac-bbbc1514cb4a)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 175.26 95.25) (xy 175.26 97.79))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 0a428af4-d960-4f7c-a083-504057c1e819)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 191.77 59.69) (xy 191.77 60.96))
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 0d2a10ee-921c-42f5-83bb-425e3bc88b08)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 90.17 161.29) (xy 90.17 162.56))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 0dfd3030-be04-4d31-ab7a-5e9d80308efc)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 151.13 96.52) (xy 151.13 120.65))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 0e475c27-688f-4e55-a388-4c84998966b4)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 148.59 90.17) (xy 148.59 97.79))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 254 138.43) (xy 256.54 138.43))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 10b73343-3a3a-4377-b401-04c4334fea4e)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 80.01 143.51) (xy 80.01 146.05))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 149.86) (xy 45.72 149.86))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 12236ce1-b1d9-4ab2-93b0-cfa25b714ba6)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 143.51 102.87) (xy 143.51 115.57))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 208.28 105.41) (xy 212.09 105.41))
Fix connection of INITN and DONE Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-06 10:10:52 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 148914fb-24cd-4620-8dcf-48009551ad5c)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 227.33 100.33) (xy 227.33 115.57))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 14e5c329-6fc9-49e6-8c2c-39adc3fa7bae)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 212.09 97.79) (xy 212.09 105.41))
Fix connection of INITN and DONE Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-06 10:10:52 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 152.4) (xy 45.72 152.4))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 83.82) (xy 107.95 83.82))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 148.59 90.17) (xy 151.13 90.17))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 212.09 87.63) (xy 215.9 87.63))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 39.37 50.8) (xy 46.99 50.8))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 45.72 147.32) (xy 38.1 147.32))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 69.85 143.51) (xy 80.01 143.51))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 50.8 27.94) (xy 52.07 27.94))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 106.68) (xy 45.72 106.68))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 91.44 134.62) (xy 107.95 134.62))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 109.22) (xy 45.72 109.22))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 165.1 45.72) (xy 184.15 45.72))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus (pts (xy 243.84 90.17) (xy 243.84 118.11))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 146.05 96.52) (xy 146.05 113.03))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 266.7 69.85) (xy 266.7 45.72))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 86.36 137.16) (xy 107.95 137.16))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 175.26 63.5) (xy 185.42 63.5))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 142.24) (xy 107.95 142.24))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 173.99 95.25) (xy 175.26 95.25))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 2b5fd026-7c5e-4b3a-84fd-1a48213683b9)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 101.6) (xy 107.95 101.6))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 2ba91107-8e94-4a22-9b34-e412192b425b)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 129.54) (xy 107.95 129.54))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 2c183096-1d91-4e5e-933c-2e61988f56c9)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 254 110.49) (xy 256.54 110.49))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 2c78c33e-9c1d-4ef7-bd13-b36abcb46a21)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 38.1 137.16) (xy 45.72 137.16))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 303eed21-ede8-45c4-8669-819bec03ed63)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 274.32 81.28) (xy 278.13 81.28))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
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Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 134.62 120.65) (xy 151.13 120.65))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 3138000d-5110-4977-8c17-49d59c01bc07)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 109.22 50.8) (xy 118.11 50.8))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 55.88 50.8) (xy 55.88 58.42))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 90.17 143.51) (xy 90.17 146.05))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 337a187f-8cb5-4e1c-b983-5a07988e10ac)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 177.8 118.11) (xy 179.07 118.11))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 33a7dd22-d797-4de2-ac8e-8fc858d38c2f)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 132.08) (xy 45.72 132.08))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 3627952c-2687-4ccf-8e27-33ef308c544d)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 39.37 50.8) (xy 39.37 52.07))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 377ca77d-fbb8-48f8-af52-92e52b18c916)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 208.28 93.98) (xy 208.28 95.25))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 38c85382-09ad-4577-a706-2fe3f56156f3)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 191.77 53.34) (xy 191.77 54.61))
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 3921a141-d594-4e5d-b607-2e3ed30a4534)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 148.59 102.87) (xy 148.59 118.11))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 3ba20d79-511f-495e-95e8-db41a1710c12)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 219.71 102.87) (xy 256.54 102.87))
Fix connection of INITN and DONE Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-06 10:10:52 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 3e0dffa9-b3d3-4400-957b-783269ff3979)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 124.46) (xy 45.72 124.46))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add pull-down resistor in load switch ON pin Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 10:48:29 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 227.33 93.98) (xy 227.33 95.25))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 22.86 22.86) (xy 24.13 22.86))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 104.14) (xy 45.72 104.14))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 41fc4511-ad21-4276-8888-4e4c322e3b3e)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 101.6 62.23) (xy 105.41 62.23))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 88.9) (xy 45.72 88.9))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 425e667d-5b03-4bed-84d4-639d89cc60fb)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 26.67 139.7) (xy 31.75 139.7))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 42b84440-61ab-4c77-8a15-d8d2fbc938e8)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus (pts (xy 243.84 123.19) (xy 243.84 125.73))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 441ac8c6-66b9-4f55-b9c2-b9a74faec4ef)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 46.99 59.69) (xy 46.99 62.23))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 458adace-cc29-4365-943e-0f083f0a4223)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 204.47 102.87) (xy 219.71 102.87))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 4603a4f0-8cd6-47ce-83a8-696ac92373e1)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 254 140.97) (xy 256.54 140.97))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 4683f639-96fd-4fbc-b6a0-62988337235e)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 165.1 45.72) (xy 165.1 95.25))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 176.53 59.69) (xy 176.53 68.58))
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 47d6ed4a-f75e-4902-a9ba-513872e26a4f)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus (pts (xy 132.08 120.65) (xy 132.08 123.19))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 492cd1a9-4a0d-4e59-a2be-bb74511cf978)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 91.44 127) (xy 91.44 134.62))
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 49420fa1-139d-4750-b447-7b401b61654c)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(polyline (pts (xy 67.31 12.7) (xy 67.31 46.99))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 146.05 113.03) (xy 152.4 113.03))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
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Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 50.8 22.86) (xy 58.42 22.86))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 175.26 66.04) (xy 184.15 66.04))
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid 4d5e4fb8-0bfe-4998-a74b-69f8123087db)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 246.38 135.89) (xy 256.54 135.89))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 4d656316-6b2c-40ae-b2fc-9a4732277fde)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 185.42 63.5) (xy 185.42 69.85))
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 4e135e62-908f-4c73-b16d-09681378a03a)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 38.1 149.86) (xy 31.75 149.86))
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid 4e6687f8-4652-4247-a7d1-669d6a4080c8)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 246.38 92.71) (xy 256.54 92.71))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 4ebf0ab5-6cd6-4fcd-aa91-b4f2346fdc15)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 134.62 115.57) (xy 143.51 115.57))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 506d69f6-45c3-440c-8450-7d80b2b6fc1c)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 85.09 137.16) (xy 86.36 137.16))
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 512f3d52-96a9-4eb7-8cf3-127311d0d270)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 227.33 125.73) (xy 227.33 127))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 5220e5ac-741a-4254-905e-ca28c340aee4)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 109.22 50.8) (xy 109.22 52.07))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
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Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 208.28 87.63) (xy 212.09 87.63))
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
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Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 254 130.81) (xy 256.54 130.81))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
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Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 254 107.95) (xy 256.54 107.95))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
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Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 38.1 132.08) (xy 31.75 132.08))
Add pull-down resistor in load switch ON pin Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 10:48:29 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
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Add pull-down resistor in load switch ON pin Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 10:48:29 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 39.37 62.23) (xy 39.37 59.69))
Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
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Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 208.28 88.9) (xy 208.28 87.63))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 85.09 134.62) (xy 91.44 134.62))
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 254 133.35) (xy 256.54 133.35))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid 5a125c62-c647-4d14-b1eb-4dc28c0971e0)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 99.06 139.7) (xy 99.06 153.67))
Add pull-down resistor in load switch ON pin Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 10:48:29 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Add pull-down resistor in load switch ON pin Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 10:48:29 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 146.05 90.17) (xy 147.32 90.17))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 55.88 25.4) (xy 55.88 50.8))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
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Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 118.11 50.8) (xy 118.11 60.96))
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 58.42 22.86) (xy 58.42 45.72))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 119.38) (xy 107.95 119.38))
Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid 5e7f4ce2-d2f5-4380-8e7b-5660fdfe4130)
Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 134.62 113.03) (xy 146.05 113.03))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 219.71 87.63) (xy 219.71 92.71))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 5f1a6f6d-9bb9-4f7c-aaa0-28a3940c2937)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 274.32 69.85) (xy 274.32 71.12))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 5f3683fc-f62d-485e-93a5-de4a869debec)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 96.52) (xy 107.95 96.52))
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid 61f5f0a5-fb3d-4f9c-9810-a24cf7092c7e)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 69.85 143.51) (xy 69.85 45.72))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 142.24) (xy 45.72 142.24))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid 640af0e2-6f44-4a8d-81c1-8f609be63480)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 208.28 100.33) (xy 208.28 105.41))
Fix connection of INITN and DONE Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-06 10:10:52 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 39.37 62.23) (xy 39.37 63.5))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 124.46) (xy 107.95 124.46))
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
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Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 101.6 50.8) (xy 101.6 52.07))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 69d04ece-5b7b-4b5c-90ad-85e53cdf8e3f)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 111.76) (xy 107.95 111.76))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 6ae9b7d0-1bb7-4a28-9102-bddc232ab8ad)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 109.22 62.23) (xy 105.41 62.23))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
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Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 143.51 97.79) (xy 143.51 90.17))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 127) (xy 45.72 127))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 91.44) (xy 107.95 91.44))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 6d2191e4-1d00-49f1-aa75-bc900ac20065)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 185.42 63.5) (xy 193.04 63.5))
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 6dbde7b2-5cc3-4f54-9fa7-8e9e342f5a44)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 132.08) (xy 107.95 132.08))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 78.74) (xy 107.95 78.74))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 121.92) (xy 45.72 121.92))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 7032a80e-3fc8-4d3b-bb2c-aeffc3aae4f0)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 62.23) (xy 105.41 63.5))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 703d9c9d-64d4-42a1-8e82-8c05da78cbda)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 93.98) (xy 107.95 93.98))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 70c0de17-ee1a-45e6-a7cf-91cf99389c09)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 185.42 74.93) (xy 185.42 76.2))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 71795c7d-c04d-42e2-8fde-c5ca6c2f72b6)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 81.28) (xy 45.72 81.28))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 72494b87-af69-4335-85d7-c0c5df491fc8)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 69.85 45.72) (xy 118.11 45.72))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 72758d95-b405-47c5-9122-5a24de7a38f4)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 204.47 105.41) (xy 208.28 105.41))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 73f95aeb-8766-4d3d-94f7-d626a0133193)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 165.1 95.25) (xy 165.1 102.87))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 7496b5a4-7e4d-481a-aaa5-1d239b10158c)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 227.33 88.9) (xy 227.33 87.63))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 7641f242-279d-4500-93d3-ff3ca7cf16ab)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 266.7 77.47) (xy 266.7 69.85))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 76ac38f6-aad1-4122-8468-fdc4cdb5ca86)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 114.3) (xy 45.72 114.3))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 77a2e314-bda1-4599-ba9a-16f4f9182f93)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 146.05 90.17) (xy 146.05 91.44))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid 78d3d432-89f1-4f1a-b28a-f99ec6aaf72f)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 121.92) (xy 107.95 121.92))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 796e096e-e50f-4d57-806d-e76b646a408a)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 101.6 50.8) (xy 109.22 50.8))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 7b17da54-28fa-4fca-8390-be79f7ba6b84)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 147.32 45.72) (xy 165.1 45.72))
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid 7bd2071e-075c-4610-b99e-efe8c4802ebc)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 99.06) (xy 107.95 99.06))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid 7c29afcd-b1c7-4b0e-9f02-350b448538af)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 116.84) (xy 45.72 116.84))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid 7cdd8274-2ad2-4f30-acda-ff65d4dd97cd)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 31.75 142.24) (xy 38.1 142.24))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 827a1eaf-2007-4a26-a335-771c51d4dcb9)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 99.06 153.67) (xy 97.79 153.67))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 83e24f36-f804-4a69-96dd-fc38e534500b)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 31.75 139.7) (xy 38.1 139.7))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 859fe1c5-adb0-4d3d-accd-70281b69be28)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 148.59 118.11) (xy 152.4 118.11))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 89f4aa2d-0e20-4d68-93ca-df45eeacdf12)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 176.53 54.61) (xy 176.53 53.34))
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 8e401732-311e-42bb-84b7-0de5e052151f)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 251.46 100.33) (xy 256.54 100.33))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 8fc999a0-4a5b-42b3-8087-05923eee24a8)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 184.15 53.34) (xy 191.77 53.34))
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 90c063c2-e76b-4972-8745-8bbd14237db9)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 114.3) (xy 107.95 114.3))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 91092beb-4172-49d2-a8e8-8106e076e21c)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 254 118.11) (xy 256.54 118.11))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 91353dd2-0c7a-4f79-8dc2-36cf587dbcae)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 215.9 45.72) (xy 215.9 87.63))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 91edb109-ecf3-4d6d-b84d-b50394c4effa)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 96.52) (xy 45.72 96.52))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 951116f7-98ca-4637-9a74-f12009047b1b)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 278.13 81.28) (xy 281.94 81.28))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 9591d9ee-dc8a-4f8c-afb4-9b5845d9fed1)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 127) (xy 107.95 127))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 95eef453-f5e3-470d-b384-aaf72f17faff)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 38.1 147.32) (xy 38.1 149.86))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 963a308d-fe28-4bff-a6c4-8cfee26c6f98)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 274.32 78.74) (xy 274.32 81.28))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 96dcaefe-a409-46b2-aaed-155a9ec7d3eb)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 134.62 118.11) (xy 148.59 118.11))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 99ae60fe-660e-41a7-bbda-7519d7b06567)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 191.77 60.96) (xy 193.04 60.96))
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 9b81c7e8-13ff-4a82-b8b9-8de254e56f49)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus (pts (xy 132.08 123.19) (xy 132.08 149.86))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 9c0981f0-f778-42f5-8ccc-e4bd288f8a3b)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 69.85 143.51) (xy 69.85 144.78))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 119.38) (xy 45.72 119.38))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 81.28) (xy 107.95 81.28))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 9d7ef824-8501-4c22-92ef-e4d850c66a9c)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 281.94 69.85) (xy 281.94 71.12))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 38.1 144.78) (xy 45.72 144.78))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 9dd9d31e-dbcc-4953-a28a-2791198e3d5e)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 76.2) (xy 45.72 76.2))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid 9f1611ee-708d-4e10-95fe-cbe04474e348)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 80.01 151.13) (xy 80.01 153.67))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
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Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus (pts (xy 184.15 149.86) (xy 243.84 149.86))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 83.82) (xy 45.72 83.82))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid a4d9c065-5b7a-4d96-be98-bd033fe207ec)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 139.7) (xy 45.72 139.7))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid a54efef6-95da-4111-8b78-594c9e6ef4ee)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 101.6 59.69) (xy 101.6 62.23))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid a5acba60-7502-4670-95cf-597c92945d8b)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 88.9) (xy 107.95 88.9))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid a788e473-84c4-4590-b7d4-fd8ca96d4ed1)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 129.54) (xy 45.72 129.54))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(uuid a81cfea1-96e1-497c-90e8-7dd0e72745b2)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus (pts (xy 132.08 149.86) (xy 184.15 149.86))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
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Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 184.15 66.04) (xy 193.04 66.04))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid ab8c7805-6159-4f04-8fa3-c39f9f102e96)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 80.01 153.67) (xy 80.01 154.94))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid abcb1995-6839-4f5a-b419-3167aa8678f0)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 86.36) (xy 107.95 86.36))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid ad2b3903-a687-4cd6-907b-45d878b4d729)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus (pts (xy 243.84 120.65) (xy 243.84 123.19))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid ad50243b-1435-4b77-b8f6-cffec917f605)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus (pts (xy 132.08 115.57) (xy 132.08 118.11))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid ad8169ce-5295-4b25-8c67-dc1316861c21)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 147.32 90.17) (xy 148.59 90.17))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid b16dfe45-9c37-43bb-8a54-b7bf97016b2b)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 134.62 110.49) (xy 152.4 110.49))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid b1a906ed-d994-497e-95c5-bce919c8badf)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 234.95 97.79) (xy 234.95 85.09))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid b1a96b95-78c9-4a42-bbb1-602de099bd36)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 22.86 27.94) (xy 24.13 27.94))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid b4c52fe9-79ce-496f-a2af-9ced96f5b90b)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 109.22 59.69) (xy 109.22 62.23))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid b6d3cad5-d135-44d0-98ce-bc49b31b586a)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 99.06) (xy 45.72 99.06))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid b7ed0d6a-1169-4eb8-889c-9cc8d2e684bf)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 118.11 45.72) (xy 147.32 45.72))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid b87bfbb0-8241-4a62-bd04-5fe3f98bdffc)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 278.13 81.28) (xy 278.13 82.55))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(uuid ba296f68-b4c8-4cbb-afdb-2974f3106ef8)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 31.75 50.8) (xy 39.37 50.8))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid ba9c6b4f-eb4a-4438-b6fc-7c69a90308d4)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 86.36) (xy 45.72 86.36))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid baa1f67b-8692-4cd5-9861-ff17ab600b75)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 212.09 105.41) (xy 256.54 105.41))
Fix connection of INITN and DONE Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-06 10:10:52 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid bc7ccac9-6e56-4a2c-bf25-4c95c1121299)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus (pts (xy 132.08 118.11) (xy 132.08 120.65))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid bc819fa0-a51f-41c7-9b57-465752134af2)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus (pts (xy 184.15 113.03) (xy 184.15 149.86))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid bc9502f1-4fda-4cf9-a284-845a20b28080)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus (pts (xy 132.08 113.03) (xy 132.08 115.57))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 45.72 134.62) (xy 38.1 134.62))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(uuid bdfa075e-9162-429a-aee8-89b23184e622)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 175.26 60.96) (xy 191.77 60.96))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 274.32 69.85) (xy 281.94 69.85))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid bfa1bbdd-0578-4934-8149-7787314ded2d)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(polyline (pts (xy 130.81 46.99) (xy 130.81 198.12))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid c0826a2f-22c5-46a7-aa4a-fc10205904e2)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 241.3 100.33) (xy 246.38 100.33))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid c3272cb7-0efd-4ecd-b8fc-74d964e15522)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 76.2) (xy 107.95 76.2))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid c36a760f-c84f-4885-a9c7-50d7c7b36572)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 101.6) (xy 45.72 101.6))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid c460c725-b6ce-4e1c-99a7-006f0a3dde9e)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 78.74) (xy 45.72 78.74))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid c47acb1e-e140-45cd-8dbd-15602d22d620)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 69.85 152.4) (xy 69.85 153.67))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid c539c843-c72a-4336-b68c-adc444c74957)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 212.09 87.63) (xy 212.09 92.71))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid c6a56205-e259-48cc-a3a6-f3c01345b5a6)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 147.32 45.72) (xy 147.32 90.17))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid c7fddc0a-55de-4e8b-817a-6503338dc4e4)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 46.99 50.8) (xy 46.99 52.07))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid c94ce249-32f2-4516-8d25-46e0bc831eb6)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 176.53 53.34) (xy 184.15 53.34))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(uuid c97d99dc-0162-4557-bdd7-f7c084db7f69)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 184.15 59.69) (xy 184.15 66.04))
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid cad8fd90-43f3-487f-a19e-9dde95baffba)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 38.1 142.24) (xy 38.1 144.78))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid cd43760f-d0ac-400b-984c-c9078c85c08f)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 38.1 139.7) (xy 38.1 137.16))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid ce2ccb11-067d-4749-987e-dd3778e74fa3)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 86.36 127) (xy 86.36 137.16))
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid ce3e0d4b-a956-4127-8d18-2d4bbf239ef4)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 165.1 128.27) (xy 165.1 129.54))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid d15c9497-c878-40d3-8099-276bb3f77ce0)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(polyline (pts (xy 67.31 46.99) (xy 67.31 198.12))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid d250439a-1782-4f72-a424-584e66fef6ee)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 73.66) (xy 45.72 73.66))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid d2520269-945f-43d5-b38a-9ea66b2bdc7c)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 254 115.57) (xy 256.54 115.57))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid d25ed519-b48f-44a3-8980-7b1f1116e51c)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 111.76) (xy 45.72 111.76))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid d5dc7aa6-6ea1-43b6-8e19-bf7ab62948ca)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(polyline (pts (xy 12.7 46.99) (xy 284.48 46.99))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid d5df3928-a4ee-4c12-8d85-f361fb1101d7)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 31.75 52.07) (xy 31.75 50.8))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid d7141b75-a55d-467b-bedf-84d2ecec1089)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 46.99 62.23) (xy 39.37 62.23))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid d80a2930-2f65-4357-9b71-d219681c39ad)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 215.9 45.72) (xy 234.95 45.72))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid d85d3125-37d5-46c5-9bfc-5440e5410e29)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 246.38 128.27) (xy 256.54 128.27))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid d876dfea-3b52-4ae5-8eda-6a467f9fcb48)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 143.51 115.57) (xy 152.4 115.57))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid d90fee16-0df0-46ba-bcd6-ba88eb79053e)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 184.15 45.72) (xy 215.9 45.72))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid d99a789a-c7b5-49a1-9cfb-f672e655a9ba)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 219.71 97.79) (xy 219.71 102.87))
Fix connection of INITN and DONE Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-06 10:10:52 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid da0d627a-94fc-401e-9881-ff33fa833818)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 81.28 127) (xy 81.28 128.27))
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid da11b0b1-01e0-4106-84f6-0c2e8b2aaabc)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 31.75 59.69) (xy 31.75 62.23))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid dad756eb-f75f-4ef1-bc3e-5d8e0a0b6e92)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus (pts (xy 243.84 118.11) (xy 243.84 120.65))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid dc58e3e6-2275-4b6f-9592-ab2e5b972c35)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 176.53 68.58) (xy 193.04 68.58))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid dcb55796-40c6-4b84-974c-d304ee963c7c)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus (pts (xy 243.84 125.73) (xy 243.84 133.35))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid e0633f8e-5405-471d-b2a4-ddfe58956bcd)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 219.71 102.87) (xy 219.71 120.65))
Fix connection of INITN and DONE Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-06 10:10:52 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid e0bea588-f2fa-44b2-9e35-7664383fa06b)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 26.67 149.86) (xy 31.75 149.86))
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid e1ca422e-d6f7-4f80-93b6-0b1a8a20ff79)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 246.38 125.73) (xy 256.54 125.73))
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid e2b85417-a801-4435-aa11-e52fa16ba115)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 246.38 123.19) (xy 256.54 123.19))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid e31bdcb0-9776-45c4-9702-9cc1cb964381)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 99.06 139.7) (xy 107.95 139.7))
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid e495a726-d4db-4387-a775-0f820e33a6c3)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 234.95 97.79) (xy 256.54 97.79))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid e5c8c536-abad-4dbb-a28d-1d01617fbdae)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 38.1 134.62) (xy 38.1 132.08))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid e60e3f73-8244-4260-a4f3-4d353f6979ab)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 177.8 110.49) (xy 181.61 110.49))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid ea474acc-61ea-481a-a515-97eaffc1041d)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 151.13 90.17) (xy 151.13 91.44))
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid ea892f4e-97ab-4f98-8514-53e00e170ef7)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(bus (pts (xy 243.84 133.35) (xy 243.84 149.86))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid ef29eb8f-6c74-4b05-abb4-d286d400a307)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 82.55 153.67) (xy 80.01 153.67))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid ef54c43e-ad97-442c-a77e-b33ce3b95c4b)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 215.9 87.63) (xy 219.71 87.63))
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid f03ea3b8-55e4-4f61-93ee-b8cd0aeb1e7c)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 281.94 78.74) (xy 281.94 81.28))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid f12fd8ea-ef81-4758-95d0-1db2c05fcc83)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 241.3 95.25) (xy 246.38 95.25))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(uuid f45a96de-98de-46cc-8468-9b50b6d696e9)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 80.01 143.51) (xy 90.17 143.51))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid f5814c1f-4daf-45f6-8e26-f5e43c1589f6)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 184.15 53.34) (xy 184.15 54.61))
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid f5a092b8-a5e0-4e2d-ae38-54eb71081c5f)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 104.14) (xy 107.95 104.14))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid f5f5ba58-ea8c-4d24-a492-ee6395e3b222)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 175.26 68.58) (xy 176.53 68.58))
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid f6510757-5c52-44ab-a1cc-ba4efd7fbaf3)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 254 113.03) (xy 256.54 113.03))
Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid f7814227-1ec2-4cd5-b025-2a9824cdfe52)
Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 109.22) (xy 107.95 109.22))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid f79b2074-3090-484e-a41e-d233ebaa14ab)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 50.8 25.4) (xy 55.88 25.4))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid f8deda28-3230-4858-9a8a-2b1e25de6448)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 105.41 116.84) (xy 107.95 116.84))
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid fa8802c1-4002-4793-8cfc-d0885041f8c4)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 234.95 45.72) (xy 234.95 80.01))
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid fa9183e5-4cb1-4367-a05f-6c4c6d66e10c)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 184.15 45.72) (xy 184.15 53.34))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid fb22f284-8383-4e7b-9a94-c2a394437fb9)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 118.11 45.72) (xy 118.11 50.8))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid fd59b25f-b399-4385-b70a-3ce3a4e5521b)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 46.99 50.8) (xy 55.88 50.8))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid fda0d028-a0ec-4f75-9fa5-1d1ea69cbe42)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 93.98) (xy 45.72 93.98))
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid fdaf153c-52b5-4a4a-ada2-5743fc66dda9)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 274.32 69.85) (xy 266.7 69.85))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid fdcec003-ded1-4ce5-a867-c92acd65c664)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 31.75 62.23) (xy 39.37 62.23))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
(uuid fe24c50c-455f-4fdf-b9bf-b272f6060195)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(wire (pts (xy 43.18 91.44) (xy 45.72 91.44))
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(stroke (width 0) (type default) (color 0 0 0 0))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(uuid fec12e8a-1901-4ec2-bf58-3e459c2eddf1)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(text "~{INITN} (lights) goes low:\nthis indicates an error\nwith the configuration\nprocess. \nCheck sysCONFIG TN."
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(at 191.77 129.54 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 1fc7b0bc-c75a-4f5c-9849-13ba805f1b83)
)
Clean up the FPGA schematic from comments Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:29:00 -06:00
(text "* Active read current with QSPI\nat 133MHz is 27mA(max).\n* Power-down and standby current\nis 50uA and 15uA(max)"
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(at 134.62 143.51 0)
Clean up the FPGA schematic from comments Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:29:00 -06:00
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 2a869d09-c5f6-4766-b123-4893c037c54f)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(text "FPGA TRX" (at 67.31 115.57 90)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 3.4036 3.4036) (thickness 0.6807) bold) (justify left bottom))
(uuid 2bec34f5-8f16-4dda-ae07-a54c3fb30eec)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(text "Alternative: W25Q32JVSFIQ" (at 134.62 130.81 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify left bottom))
Clean up the FPGA schematic from comments Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:29:00 -06:00
(uuid 48e62fd4-ea15-4c3f-81bd-76444d919ec3)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(text "FPGA PWR" (at 67.31 43.18 90)
(effects (font (size 3.4036 3.4036) (thickness 0.6807) bold) (justify left bottom))
(uuid 550b6265-610e-4e04-b40a-74a99a6f1ac9)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
)
(text "CFG[2:0] = 010\nBoot from SPI Flash.\nCheck sysCONFIG TN."
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(at 236.22 77.47 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 642761d4-6b2a-47b1-bd0d-edaa6239ed5f)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(text "Current Consumption: 3.8mA" (at 92.71 163.83 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify left bottom))
Clean up the FPGA schematic from comments Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:29:00 -06:00
(uuid 7a7d5b76-ae7c-4a63-992f-e5560ff6d5de)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(text "FPGA DEBUG/SPI" (at 130.81 123.19 90)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 3.4036 3.4036) (thickness 0.6807) bold) (justify left bottom))
(uuid 8ada0eaa-3244-4c1e-893a-788f9dbf683f)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(text "FPGA CONFIGURATION" (at 283.21 146.05 90)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 3.4036 3.4036) (thickness 0.6807) bold) (justify left bottom))
(uuid e2416b2e-f191-40db-a0a3-64649bc9f155)
)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(text "DONE (lights) goes High:\nthis indicates that FPGA\nenters user mode.\nCheck sysCONFIG TN."
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(at 191.77 118.11 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid f7609145-7680-487c-b45e-73108a33c279)
)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(label "CFG_IO2" (at 255.27 123.19 180)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid 1fa05512-5fd6-4833-94af-64f9f1185217)
)
(label "{CFG_IO0 CFG_IO1 CFG_IO2 CFG_IO3 CFG_CLK ~{CFG_CS}}"
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(at 139.7 149.86 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 3375ec27-59b9-4b44-abd5-17835209557d)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(label "CFG_CLK" (at 255.27 92.71 180)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid 39debd70-bd18-4adf-b74f-e76a8ba24046)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(label "~{CFG_CS}" (at 255.27 135.89 180)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid 44dce111-a7fa-4c56-a8ab-6d3d01d7d8bc)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(label "CFG_CLK" (at 142.24 113.03 180)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid 520b1415-9245-4b93-ba6b-5bd118f3c7bc)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(label "CFG_IO3" (at 142.24 120.65 180)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid 5f9c17fb-517a-4a26-b1c7-9cc06f8af2b4)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(label "CFG_IO1" (at 177.8 110.49 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify left bottom))
(uuid 7044e974-913a-4f7f-a98b-7257da0fa296)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(label "CFG_IO1" (at 255.27 125.73 180)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid 869debe2-c652-4c04-bf1d-1614b50ee3ae)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(label "CFG_IO3" (at 255.27 120.65 180)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid a0ea42a7-261d-4e76-80ee-43f51a2dcb92)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(label "CFG_IO0" (at 255.27 128.27 180)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid b1c0787b-4105-489c-ab15-a5a33a17a9a9)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(label "FPGA_CLK_IN" (at 105.41 139.7 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid bab9f37e-b9aa-434d-ae21-8877a4b4669c)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(label "~{CFG_CS}" (at 142.24 115.57 180)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid cb122e25-34a1-46df-8607-a2d613de228d)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(label "CFG_IO2" (at 142.24 118.11 180)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid f1a4cfd4-09cc-4c7f-8893-4f404a317073)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(label "CFG_IO0" (at 142.24 110.49 180)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify right bottom))
(uuid fa3cab35-4a7b-468e-8444-535770e3eecf)
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Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(global_label "3V3" (shape input) (at 22.86 22.86 180) (fields_autoplaced)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid c7dd09a5-c9ee-4fa6-9cb6-061e4e161941)
(property "Intersheet References" "${INTERSHEET_REFS}" (id 0) (at 16.9393 22.9394 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right) hide)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "SPI_MISO" (shape input) (at 105.41 106.68 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid 07bb3c7a-2690-402d-b0f8-533cc6fe84ce)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "SPI_MOSI" (shape input) (at 105.41 109.22 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid 0921c614-3aba-4814-a792-3e77da4d559a)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "RXDATAP" (shape input) (at 26.67 132.08 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid 112a2f65-ff43-425e-8d70-ac618d7c7ed5)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "FPGA_IO0" (shape input) (at 85.09 134.62 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid 2b9eea51-7036-44d5-84ce-6c3adc278715)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "FPGA_INIT" (shape input) (at 204.47 105.41 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid 2f236aee-57ee-47c4-814f-49ffc21e9f63)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "FPGA_PROG" (shape input) (at 204.47 107.95 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid 34a387fd-dbac-48bd-b174-37b9d2d1b368)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "JTDO" (shape input) (at 175.26 60.96 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid 46cc5564-14ef-4ee5-aa8d-4b05b98fda25)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "RXCLOCKP" (shape input) (at 26.67 142.24 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid 476483c7-ae07-4782-b465-a561719e3442)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "SPI_CLK" (shape input) (at 105.41 129.54 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid 5aaaf7b3-3dab-4fdd-a264-90953e117367)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "TXDATAN" (shape input) (at 43.18 127 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid 5dd00749-f60e-4d21-a16d-b232da737a18)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "JTDI" (shape input) (at 175.26 66.04 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid 76ef1cc8-22b9-4c03-bc65-01f5ba1027b8)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "JTCK" (shape input) (at 175.26 63.5 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid 79c60a3b-d402-4aa4-a47b-f8fac740bcf3)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "TXDATAP" (shape input) (at 43.18 124.46 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid 86af934b-4b93-462b-8c97-8989d6eb9525)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "JTMS" (shape input) (at 175.26 68.58 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid 8c8aca9a-3d42-45bf-83bf-80cd13620ea5)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "RXDATAN" (shape input) (at 26.67 139.7 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid 94b25601-eaf6-4e79-a998-7f1160c1d660)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "TXCLOCKN" (shape input) (at 43.18 116.84 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid abd7d190-aa51-4b05-8df8-890befb5093b)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "FPGA_DONE" (shape input) (at 204.47 102.87 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid b0bb26b8-3df3-4c53-b596-0e8bf9cd3466)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "TXCLOCKP" (shape input) (at 43.18 114.3 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid b8dfba22-f82a-47d2-97e5-98668677a930)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "RXCLOCKN" (shape input) (at 26.67 149.86 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid d8ec481b-c08f-49ba-8e54-1d9415f9f61a)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "FPGA_IO1" (shape input) (at 85.09 137.16 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(uuid e1323b14-4a81-4d1b-be23-9e0510430791)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "FPGA_EN" (shape input) (at 22.86 27.94 180)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid e8817aec-0526-496e-8828-c0b43dc59f5e)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(hierarchical_label "SPI_CS" (shape input) (at 105.41 76.2 180)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
(effects (font (size 1.27 1.27)) (justify right))
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid eaaf9451-9bb7-4950-bea8-9a600067bf7e)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:C") (at 109.22 55.88 0) (unit 1)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(in_bom yes) (on_board yes)
(uuid 0080fc64-8a49-485b-9a40-b39c02149a47)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "C609" (id 0) (at 107.95 60.7314 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "100n" (id 1) (at 107.95 58.42 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "Capacitor_SMD:C_0402_1005Metric" (id 2) (at 110.1852 59.69 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 109.22 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "KEMET" (id 4) (at 109.22 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Capacitor, 0402, 10%, 16V, X7R" (id 5) (at 109.22 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "C0402C104K4RACTU" (id 6) (at 109.22 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 606f5c9b-78fe-44c4-b546-78451519f58f))
(pin "2" (uuid ca55545a-4469-4ad7-b5a7-f9939eb0ed98))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "power:GND") (at 105.41 63.5 0) (unit 1)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(in_bom yes) (on_board yes)
(uuid 04a4cb43-3430-4099-8cd6-124df4ba20be)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "#PWR0620" (id 0) (at 105.41 69.85 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "GND" (id 1) (at 105.537 67.8942 0))
(property "Footprint" "" (id 2) (at 105.41 63.5 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "" (id 3) (at 105.41 63.5 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 801d565e-1ba1-4c9b-a717-fa50001782d1))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:Q_NMOS_GSD") (at 224.79 120.65 0) (unit 1)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(in_bom yes) (on_board yes) (fields_autoplaced)
(uuid 117817db-7422-46b9-88c0-38af53c73d1f)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "Q601" (id 0) (at 231.14 119.3799 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) (justify left))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "Q_NMOS_GSD" (id 1) (at 231.14 121.9199 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) (justify left))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "" (id 2) (at 229.87 118.11 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 224.79 120.65 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "BSS138PW,115" (id 4) (at 224.79 120.65 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "Nexperia" (id 5) (at 224.79 120.65 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid ab6b7b36-e380-41e6-83c0-048f5c48e8ac))
(pin "2" (uuid 839b1ed2-126e-4e03-8307-c68d0dfad444))
(pin "3" (uuid 38b11dab-7dc4-492e-b2a4-b50d96263580))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 143.51 100.33 180) (unit 1)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(in_bom yes) (on_board yes)
(uuid 26d440d2-986b-424a-9f38-2d34dbde8186)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "R620" (id 0) (at 139.7 101.6 0))
(property "Value" "4.7k" (id 1) (at 139.7 99.06 0))
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 143.51 100.33 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 143.51 100.33 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 143.51 100.33 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "Vishay" (id 5) (at 143.51 100.33 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "CRCW04024K70FKEDC" (id 6) (at 143.51 100.33 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid c93023ee-6bf3-458e-b6cb-796854f82572))
(pin "2" (uuid e538596b-fc26-4045-a6a2-e8f728585986))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:LED_Small") (at 208.28 97.79 90) (unit 1)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(in_bom yes) (on_board yes)
(uuid 2b56563e-0e12-4baf-b355-75c24f5fba2a)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "D601" (id 0) (at 200.66 96.52 90)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "RED" (id 1) (at 200.66 99.06 90)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "" (id 2) (at 208.28 97.79 90)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 208.28 97.79 90)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid ae748604-4589-4bf9-9096-fd892f2de20b))
(pin "2" (uuid 528cfa5c-df31-4377-89d6-c07aee6ce572))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:C") (at 170.18 95.25 90) (unit 1)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(in_bom yes) (on_board yes)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "C606" (id 0) (at 171.3484 98.1456 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "100n" (id 1) (at 169.037 98.1456 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "Capacitor_SMD:C_0402_1005Metric" (id 2) (at 173.99 94.2848 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 170.18 95.25 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "KEMET" (id 4) (at 170.18 95.25 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Capacitor, 0402, 10%, 16V, X7R" (id 5) (at 170.18 95.25 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "C0402C104K4RACTU" (id 6) (at 170.18 95.25 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 658b9864-78d2-4e4d-8e0e-197fda84f1e2))
(pin "2" (uuid cc1b928e-9ef1-41da-883d-c7ca579a4541))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "lsf-kicad:LFE5UM-45F-6BG381x") (at 266.7 115.57 0) (unit 8)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(in_bom yes) (on_board yes)
(uuid 30b1edbe-055a-4b96-902d-62c96aa7e53d)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "U604" (id 0) (at 261.62 149.86 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify left))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "~" (id 1) (at 256.54 153.67 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify left))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "" (id 2) (at 266.7 115.57 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "https://www.latticesemi.com/view_document?document_id=50461" (id 3) (at 266.7 115.57 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
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)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 248.92 95.25 90) (unit 1)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid 3f6df2d0-d8ce-4c4d-874e-02f0769555a1)
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Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 248.92 95.25 0)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 248.92 95.25 0)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "Vishay" (id 5) (at 248.92 95.25 0)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "CRCW04024K70FKEDC" (id 6) (at 248.92 95.25 0)
Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid 65747be1-1521-4ffb-9491-3757797a19e2))
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Add PSU for FPGA Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 03:19:58 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "lsf-kicad:LFE5UM-45F-6BG381x") (at 203.2 66.04 0) (unit 9)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
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(effects (font (size 1.27 1.27)) (justify left))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "~" (id 1) (at 209.55 83.8199 0)
(effects (font (size 1.27 1.27)) (justify left))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "" (id 2) (at 203.2 66.04 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "https://www.latticesemi.com/view_document?document_id=50461" (id 3) (at 203.2 66.04 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
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(pin "Y7" (uuid 45310ec0-5353-4b8f-be59-2d2516c80f3b))
(pin "Y8" (uuid 6cdaa852-b9bf-422b-997f-585fbe563d4f))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "power:GND") (at 241.3 100.33 270) (unit 1)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(in_bom yes) (on_board yes)
(uuid 4258d610-1ff6-4aa8-b511-96320fe3dd00)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "#PWR0615" (id 0) (at 234.95 100.33 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "GND" (id 1) (at 237.49 100.33 0))
(property "Footprint" "" (id 2) (at 241.3 100.33 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "" (id 3) (at 241.3 100.33 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
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(pin "1" (uuid b559122e-51f4-4ddf-b5c4-ded7397ef57c))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:C") (at 281.94 74.93 0) (unit 1)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(in_bom yes) (on_board yes)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "C625" (id 0) (at 280.67 79.7814 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "100n" (id 1) (at 280.67 77.47 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "Capacitor_SMD:C_0402_1005Metric" (id 2) (at 282.9052 78.74 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 281.94 74.93 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "KEMET" (id 4) (at 281.94 74.93 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Capacitor, 0402, 10%, 16V, X7R" (id 5) (at 281.94 74.93 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "C0402C104K4RACTU" (id 6) (at 281.94 74.93 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid d67faff8-6886-486d-8ba6-14ccb4c65cb7))
(pin "2" (uuid c475e851-af19-402b-89a5-299dc634fcfc))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "power:GND") (at 227.33 127 0) (unit 1)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(in_bom yes) (on_board yes)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "#PWR0611" (id 0) (at 227.33 133.35 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "GND" (id 1) (at 227.457 131.3942 0))
(property "Footprint" "" (id 2) (at 227.33 127 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "" (id 3) (at 227.33 127 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 5ba47861-d882-4e07-9924-27cd02f812d4))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 208.28 91.44 0) (mirror x) (unit 1)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(in_bom yes) (on_board yes)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "R612" (id 0) (at 206.7814 90.2716 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "TBD" (id 1) (at 206.7814 92.583 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 208.28 91.44 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 208.28 91.44 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 208.28 91.44 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "" (id 5) (at 208.28 91.44 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "" (id 6) (at 208.28 91.44 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 2a2146eb-85f6-4c87-8571-2f05d5b75191))
(pin "2" (uuid 90c22dfe-892c-4e64-9398-b126c4f34633))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 191.77 57.15 180) (unit 1)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(in_bom yes) (on_board yes)
(uuid 4cef2dba-0800-470b-bf8c-4a1d00eb3449)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "R611" (id 0) (at 186.69 57.15 90))
(property "Value" "4.7k" (id 1) (at 189.23 57.15 90))
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 191.77 57.15 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 191.77 57.15 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 191.77 57.15 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "Vishay" (id 5) (at 191.77 57.15 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "CRCW04024K70FKEDC" (id 6) (at 191.77 57.15 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 5ad6eca2-af1e-4fcd-8dd3-1fcab4a6da70))
(pin "2" (uuid f472d64b-b0b6-44d9-93fd-9ace698920f6))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "power:GND") (at 241.3 95.25 270) (unit 1)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(in_bom yes) (on_board yes)
(uuid 4dff0a8e-15b6-4ad4-9af2-e1592dfea4bc)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "#PWR0614" (id 0) (at 234.95 95.25 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "GND" (id 1) (at 237.49 95.25 0))
(property "Footprint" "" (id 2) (at 241.3 95.25 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "" (id 3) (at 241.3 95.25 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid bb5c7952-60ac-4e51-bfcd-8e864568160c))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "power:GND") (at 165.1 129.54 0) (unit 1)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(in_bom yes) (on_board yes)
(uuid 5050a159-db2a-44fd-9cb7-b23f924f1275)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "#PWR0613" (id 0) (at 165.1 135.89 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "GND" (id 1) (at 165.227 133.9342 0))
(property "Footprint" "" (id 2) (at 165.1 129.54 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "" (id 3) (at 165.1 129.54 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid b7ac6a21-99c4-4dbf-b3d6-ceaf11ff976e))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:C") (at 69.85 148.59 0) (unit 1)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(in_bom yes) (on_board yes)
(uuid 50e85761-696c-43cf-a30a-bd0ef3b7a5ca)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "C607" (id 0) (at 73.66 149.86 90)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "100n" (id 1) (at 71.12 149.86 90)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "Capacitor_SMD:C_0402_1005Metric" (id 2) (at 70.8152 152.4 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 69.85 148.59 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "KEMET" (id 4) (at 69.85 148.59 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Capacitor, 0402, 10%, 16V, X7R" (id 5) (at 69.85 148.59 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "C0402C104K4RACTU" (id 6) (at 69.85 148.59 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 1ed36375-299a-4d10-b0c0-b9d56bf27bd0))
(pin "2" (uuid c65545c3-f8c9-4ce0-895b-963418b5b4f7))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 212.09 95.25 0) (unit 1)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(in_bom yes) (on_board yes)
(uuid 5170f994-716a-4a91-a691-8551abc5b42c)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "R613" (id 0) (at 217.17 95.25 90))
(property "Value" "10k" (id 1) (at 214.63 95.25 90))
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 212.09 95.25 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 212.09 95.25 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 212.09 95.25 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "Vishay" (id 5) (at 212.09 95.25 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "CRCW040210K0FKEDC " (id 6) (at 212.09 95.25 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 2edd3189-83ca-4a50-82ae-53e956392299))
(pin "2" (uuid 03b11f6b-9c82-412b-99bf-8612da70977a))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:C") (at 31.75 55.88 0) (unit 1)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(in_bom yes) (on_board yes)
(uuid 55f95a5f-346b-40e7-9d47-3d3b43f40ad6)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "C602" (id 0) (at 30.48 60.7314 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "100n" (id 1) (at 30.48 58.42 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "Capacitor_SMD:C_0402_1005Metric" (id 2) (at 32.7152 59.69 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 31.75 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "KEMET" (id 4) (at 31.75 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Capacitor, 0402, 10%, 16V, X7R" (id 5) (at 31.75 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "C0402C104K4RACTU" (id 6) (at 31.75 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid ddce3e29-7f67-4d40-872a-048bc20a9ace))
(pin "2" (uuid 7490de49-5350-4b96-a88d-a0eefbf04697))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "power:GND") (at 185.42 76.2 0) (unit 1)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(in_bom yes) (on_board yes)
(uuid 5a4d6bfd-f8b3-4981-8668-0ea5d63394c6)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "#PWR0610" (id 0) (at 185.42 82.55 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "GND" (id 1) (at 185.42 80.01 0))
(property "Footprint" "" (id 2) (at 185.42 76.2 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "" (id 3) (at 185.42 76.2 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 85dc366c-aced-4db7-994a-f59e7019ab3f))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "power:GND") (at 69.85 153.67 0) (unit 1)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(in_bom yes) (on_board yes)
(uuid 6207a4a4-c02f-415b-8c6f-114d9f4776c5)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "#PWR0617" (id 0) (at 69.85 160.02 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "GND" (id 1) (at 69.977 158.0642 0))
(property "Footprint" "" (id 2) (at 69.85 153.67 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "" (id 3) (at 69.85 153.67 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 3be91be7-acf7-4349-b79d-7710de765c53))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 176.53 57.15 180) (unit 1)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(in_bom yes) (on_board yes)
(uuid 63bf093a-bb92-4b04-b4f5-2d98729eae5c)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "R608" (id 0) (at 171.45 57.15 90))
(property "Value" "4.7k" (id 1) (at 173.99 57.15 90))
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 176.53 57.15 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 176.53 57.15 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 176.53 57.15 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "Vishay" (id 5) (at 176.53 57.15 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "CRCW04024K70FKEDC" (id 6) (at 176.53 57.15 0)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
(effects (font (size 1.27 1.27)) hide)
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(pin "1" (uuid 6cb70f82-fc57-4c2a-afba-be7e994a9484))
(pin "2" (uuid 4c96ae47-776f-46f9-a25a-1b5dc96766d3))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "lsf-kicad:SiT1602BI-71-33E-26.000000E") (at 90.17 153.67 0) (unit 1)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(in_bom yes) (on_board yes)
(uuid 6d8f3070-08b4-44bb-8a98-c3753cd21cad)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "U606" (id 0) (at 93.98 147.32 0))
(property "Value" "SiT1602BI-71-33E-26.000000E" (id 1) (at 107.95 160.02 0))
(property "Footprint" "Crystal:Crystal_SMD_2016-4Pin_2.0x1.6mm" (id 2) (at 95.25 170.18 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "https://www.sitime.com/support/resource-library/datasheets/sit1602-datasheet" (id 3) (at 87.63 153.67 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid cd0489c1-95cf-4700-abc7-76d449d92f4c))
(pin "2" (uuid 0b54b345-9a53-4674-9845-b3cc18589955))
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(pin "4" (uuid ea6ccf7c-821b-47a5-83af-2320a7de6ed7))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "lsf-kicad:LFE5UM-45F-6BG381x") (at 55.88 111.76 0) (unit 4)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(in_bom yes) (on_board yes)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "U604" (id 0) (at 50.8 161.29 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify left))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "~" (id 1) (at 44.45 166.37 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify left))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "" (id 2) (at 55.88 111.76 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "https://www.latticesemi.com/view_document?document_id=50461" (id 3) (at 55.88 111.76 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
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(pin "T11" (uuid 1dd7e11e-43e2-490d-b80a-72ae7a1e8bc8))
(pin "T12" (uuid c43cbf1b-8636-4086-a009-2ead27837232))
(pin "T13" (uuid eafafa71-871e-4e08-a0ad-415cc5927655))
(pin "T14" (uuid 5012e427-2605-4ef6-8acf-e8763ef0a984))
(pin "T7" (uuid 7f280c56-2afd-45c5-b3ee-e6225c105eda))
(pin "T8" (uuid c1344181-1d9e-48c4-b279-ab0e274e51f6))
(pin "T9" (uuid c358d6d3-3fc1-4255-889b-dd8456b5bf5d))
(pin "W13" (uuid b0901133-9ac8-4fae-b1c3-23a5c59648f4))
(pin "W14" (uuid 76f0ae03-8a81-4e03-82cc-697b8a2d3dc9))
(pin "W17" (uuid 4a6f7f58-ffa1-4ce0-84a4-a43028bdaf25))
(pin "W18" (uuid 50b3c388-70c2-40f0-bcab-91360d921fbd))
(pin "W20" (uuid 56d30706-3bc3-4351-80e6-e342c04c34e6))
(pin "W4" (uuid 6ff6dbdb-8494-4d96-9edf-cb4316c92b89))
(pin "W5" (uuid a3299ab5-3dc3-46bd-84ec-03bef122851b))
(pin "W8" (uuid 1c359650-9720-4ff5-b7eb-b9ba37db5887))
(pin "W9" (uuid 9608f371-5068-4dfe-bc11-cbcdf54d5e25))
(pin "Y11" (uuid d9ecd9ae-ef0a-439f-b17a-557e46b82925))
(pin "Y12" (uuid de88ea3f-d699-4a70-9d06-d3f653a880a1))
(pin "Y14" (uuid e408af70-9a3d-4b30-a91f-1a69c4a24a80))
(pin "Y15" (uuid c5d90d50-8815-42b3-bdfe-855c387da089))
(pin "Y16" (uuid 63622b85-ffc5-43a3-94fb-f01b29a8acd4))
(pin "Y17" (uuid 66bacf32-932b-40ed-a996-33703e38cc32))
(pin "Y19" (uuid 0963774c-b376-4594-a90e-ed8e9692b9ea))
(pin "Y5" (uuid aa662617-353d-45f8-8bab-007a7f6b3467))
(pin "Y6" (uuid de853116-f19f-4819-861d-91762ab22b12))
(pin "Y7" (uuid c7c0e390-c203-4145-83d2-d45b2a38bf27))
(pin "Y8" (uuid 482345a1-5db6-4976-998d-99689809f8b9))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R") (at 31.75 135.89 0) (unit 1)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid 75eb803c-de21-4f39-b6ec-834a97f286aa)
(property "Reference" "R605" (id 0) (at 29.9974 134.7216 0)
(effects (font (size 1.27 1.27)) (justify right))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "100" (id 1) (at 29.9974 137.033 0)
(effects (font (size 1.27 1.27)) (justify right))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 29.972 135.89 90)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 31.75 135.89 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "RT0402FRE07100RL" (id 4) (at 31.75 135.89 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid 20a41452-cbb0-4999-afeb-8df19eebcf58))
(pin "2" (uuid b9364dd5-c75a-4f46-9892-3c28f2ac60da))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 185.42 72.39 180) (unit 1)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid 79db9f14-e4bb-4d45-8004-9f20fe2a7f5b)
(property "Reference" "R610" (id 0) (at 180.34 72.39 90))
(property "Value" "10k" (id 1) (at 182.88 72.39 90))
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 185.42 72.39 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 185.42 72.39 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 185.42 72.39 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "Vishay" (id 5) (at 185.42 72.39 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "CRCW040210K0FKEDC " (id 6) (at 185.42 72.39 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid 3f03bc9e-df58-44a4-baf6-9b95afdddb95))
(pin "2" (uuid 0b7b6b80-ae94-4b1b-a38e-a90a7895e1d0))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "power:GND") (at 39.37 63.5 0) (unit 1)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid 7cb3efc2-a96a-4d2a-bca6-3122b07363fc)
(property "Reference" "#PWR0619" (id 0) (at 39.37 69.85 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "GND" (id 1) (at 39.497 67.8942 0))
(property "Footprint" "" (id 2) (at 39.37 63.5 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "" (id 3) (at 39.37 63.5 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid 2a7c5bbf-76dd-41f2-8b01-256a7292c833))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 151.13 93.98 0) (unit 1)
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid 81987ca7-ed98-4877-a955-3899028a47b1)
(property "Reference" "R623" (id 0) (at 154.94 92.71 0))
(property "Value" "4.7k" (id 1) (at 154.94 95.25 0))
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 151.13 93.98 0)
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 151.13 93.98 0)
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 151.13 93.98 0)
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "Vishay" (id 5) (at 151.13 93.98 0)
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "CRCW04024K70FKEDC" (id 6) (at 151.13 93.98 0)
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid 2c18ef70-4883-45b1-afdc-fff9d1c23435))
(pin "2" (uuid ea90fc18-9ee9-41fd-a807-e35c9a729a74))
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:LED_Small") (at 227.33 97.79 90) (unit 1)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid 84dbf505-ea44-4872-be2e-3ed18d10cdee)
(property "Reference" "D602" (id 0) (at 228.6 96.52 90)
(effects (font (size 1.27 1.27)) (justify right))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "GREEN" (id 1) (at 228.6 99.06 90)
(effects (font (size 1.27 1.27)) (justify right))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "" (id 2) (at 227.33 97.79 90)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 227.33 97.79 90)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid c86c0baf-ced5-47ce-b986-8dc1782793dd))
(pin "2" (uuid 655582de-ae4a-457e-8626-61db16562dfe))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:C") (at 101.6 55.88 0) (unit 1)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid 92cc2291-9e82-4dd8-9a9f-28825ad7b077)
(property "Reference" "C608" (id 0) (at 100.33 60.7314 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "100n" (id 1) (at 100.33 58.42 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "Capacitor_SMD:C_0402_1005Metric" (id 2) (at 102.5652 59.69 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 101.6 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "KEMET" (id 4) (at 101.6 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Capacitor, 0402, 10%, 16V, X7R" (id 5) (at 101.6 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "C0402C104K4RACTU" (id 6) (at 101.6 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid 91275d79-3e54-480c-8cb1-e84c077446c6))
(pin "2" (uuid 1870733b-b4e9-4000-b0e5-e82c1ddc055b))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Connector:TestPoint") (at 81.28 127 0) (unit 1)
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(in_bom no) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid 9325ef7e-3998-4a98-843a-4004f259ce47)
(property "Reference" "TP606" (id 0) (at 80.01 121.92 90)
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(effects (font (size 1.27 1.27)) (justify left))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "GND" (id 1) (at 82.55 121.92 90)
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(effects (font (size 1.27 1.27)) (justify left))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "TestPoint:TestPoint_Pad_D1.0mm" (id 2) (at 86.36 127 0)
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 86.36 127 0)
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid f1c1b548-eb31-41a2-8aa5-c1b00b8e5ee9))
Add test points for GPIOs Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 08:55:38 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:C") (at 274.32 74.93 0) (unit 1)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid a451943c-d1be-409f-af01-78785c59a4b8)
(property "Reference" "C624" (id 0) (at 273.05 79.7814 0)
(effects (font (size 1.27 1.27)) (justify right))
)
(property "Value" "100n" (id 1) (at 273.05 77.47 0)
(effects (font (size 1.27 1.27)) (justify right))
)
(property "Footprint" "Capacitor_SMD:C_0402_1005Metric" (id 2) (at 275.2852 78.74 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 274.32 74.93 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "KEMET" (id 4) (at 274.32 74.93 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Capacitor, 0402, 10%, 16V, X7R" (id 5) (at 274.32 74.93 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "C0402C104K4RACTU" (id 6) (at 274.32 74.93 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid a94cfd74-0a2f-49c1-9e5e-0e875dd3cd31))
(pin "2" (uuid 3d73976b-f564-4346-803f-475354d6b72f))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "power:GND") (at 81.28 128.27 0) (unit 1)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid b34c095e-0a33-4dc4-a957-421ea1d68830)
(property "Reference" "#PWR0616" (id 0) (at 81.28 134.62 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "GND" (id 1) (at 81.407 132.6642 0))
(property "Footprint" "" (id 2) (at 81.28 128.27 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "" (id 3) (at 81.28 128.27 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid a2c5feaa-8471-4775-9f46-bf32f3985a86))
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Connector:TestPoint") (at 86.36 127 0) (unit 1)
(in_bom no) (on_board yes)
(uuid b44fc5e5-cbc9-4f84-b155-32189c4dd57c)
(property "Reference" "TP604" (id 0) (at 85.09 121.92 90)
Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
(effects (font (size 1.27 1.27)) (justify left))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "IO1" (id 1) (at 87.63 121.92 90)
Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
(effects (font (size 1.27 1.27)) (justify left))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "TestPoint:TestPoint_Pad_D1.0mm" (id 2) (at 91.44 127 0)
Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 91.44 127 0)
Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid a8e9d866-2896-4e7c-8a7a-142673ce988a))
Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:C") (at 39.37 55.88 0) (unit 1)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid b505a834-86dd-4b6b-b361-b19a1551eee9)
(property "Reference" "C603" (id 0) (at 38.1 60.7314 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "100n" (id 1) (at 38.1 58.42 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "Capacitor_SMD:C_0402_1005Metric" (id 2) (at 40.3352 59.69 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 39.37 55.88 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "KEMET" (id 4) (at 39.37 55.88 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Capacitor, 0402, 10%, 16V, X7R" (id 5) (at 39.37 55.88 0)
(effects (font (size 1.27 1.27)) hide)
)
(property "PartNumber" "C0402C104K4RACTU" (id 6) (at 39.37 55.88 0)
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid c93ed652-1527-472d-8908-c9366cd8d3ae))
(pin "2" (uuid ee221db8-c58c-4e0b-bbcd-1251d99baadc))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Connector:TestPoint") (at 91.44 127 0) (unit 1)
(in_bom no) (on_board yes)
(uuid b6f1da83-c72b-4591-9bbd-22fdf79b7095)
(property "Reference" "TP605" (id 0) (at 90.17 121.92 90)
(effects (font (size 1.27 1.27)) (justify left))
Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "IO0" (id 1) (at 92.71 121.92 90)
Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
(effects (font (size 1.27 1.27)) (justify left))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "TestPoint:TestPoint_Pad_D1.0mm" (id 2) (at 96.52 127 0)
Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 96.52 127 0)
Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid b64dff2c-407a-4d31-8a71-09f0f5fc893b))
Fixes in FPGA power schematic - Add ferrite bead part number - Fixes ERC error in PG of 1.1V pin - Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-29 08:08:21 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 80.01 148.59 180) (unit 1)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid ba62a079-2ddd-41c4-923f-29aceb1a13e9)
(property "Reference" "R619" (id 0) (at 83.82 146.05 90))
(property "Value" "10k" (id 1) (at 86.36 146.05 90))
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 80.01 148.59 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 80.01 148.59 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 80.01 148.59 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "Vishay" (id 5) (at 80.01 148.59 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "CRCW040210K0FKEDC " (id 6) (at 80.01 148.59 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid dc2d37af-a536-45cd-9b58-89aac457fdad))
(pin "2" (uuid dab0ee5a-a5f8-4a1a-97e3-2022395125be))
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R") (at 31.75 146.05 0) (unit 1)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid c075e025-58fd-45d1-8a69-af7a9ca099d5)
(property "Reference" "R604" (id 0) (at 29.9974 144.8816 0)
(effects (font (size 1.27 1.27)) (justify right))
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(property "Value" "100" (id 1) (at 29.9974 147.193 0)
(effects (font (size 1.27 1.27)) (justify right))
)
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 29.972 146.05 90)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 31.75 146.05 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "RT0402FRE07100RL" (id 4) (at 31.75 146.05 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid fa45ae4e-b394-486c-8e37-0c386bba235d))
(pin "2" (uuid 90f36d9e-5ac2-402e-9876-8b5aead8f308))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 146.05 93.98 0) (unit 1)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid c2f168e7-1d61-4706-946e-287606204505)
(property "Reference" "R621" (id 0) (at 142.24 95.25 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "1k" (id 1) (at 142.24 92.71 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) (justify right))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 146.05 93.98 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 146.05 93.98 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 146.05 93.98 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "Vishay" (id 5) (at 146.05 93.98 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "CRCW04021K00FKEDC" (id 6) (at 146.05 93.98 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid f9cebe2c-53f4-44bc-9972-631a005389db))
(pin "2" (uuid c583ec0b-a5b3-4a0f-9a27-2735bec38052))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "power:GND") (at 278.13 82.55 0) (unit 1)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid cb56eb0a-be33-4e4c-bbd9-cf0920244ab1)
(property "Reference" "#PWR0624" (id 0) (at 278.13 88.9 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "GND" (id 1) (at 278.257 86.9442 0))
(property "Footprint" "" (id 2) (at 278.13 82.55 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "" (id 3) (at 278.13 82.55 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid 7398eb26-91e1-4799-84f0-0a9ccc0d8f6a))
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "power:GND") (at 175.26 97.79 0) (unit 1)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(in_bom yes) (on_board yes)
(uuid d8abf568-bed0-48d8-a24e-fc44bedff660)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "#PWR0612" (id 0) (at 175.26 104.14 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "GND" (id 1) (at 175.387 102.1842 0))
(property "Footprint" "" (id 2) (at 175.26 97.79 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "" (id 3) (at 175.26 97.79 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 61ebdbe2-12ec-4265-8291-e599b2fb0415))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 219.71 95.25 0) (unit 1)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(in_bom yes) (on_board yes)
(uuid dabc1824-456b-4501-a26e-49cbc8763810)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "R614" (id 0) (at 224.79 95.25 90))
(property "Value" "10k" (id 1) (at 222.25 95.25 90))
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 219.71 95.25 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 219.71 95.25 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 219.71 95.25 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "Vishay" (id 5) (at 219.71 95.25 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "CRCW040210K0FKEDC " (id 6) (at 219.71 95.25 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 9742a9fa-313b-4917-879e-18a7623841cc))
(pin "2" (uuid b0f6d345-9f24-4b6b-a80f-6afa1b953491))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 148.59 100.33 0) (unit 1)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(in_bom yes) (on_board yes)
(uuid db030005-b299-4d6c-8655-d1d380caed4d)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "R622" (id 0) (at 154.94 99.06 0))
(property "Value" "4.7k" (id 1) (at 154.94 101.6 0))
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 148.59 100.33 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 148.59 100.33 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 148.59 100.33 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "Vishay" (id 5) (at 148.59 100.33 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "CRCW04024K70FKEDC" (id 6) (at 148.59 100.33 0)
Add missing pull-up resistor Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 08:56:27 -06:00
(effects (font (size 1.27 1.27)) hide)
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(pin "1" (uuid 6ff85454-b31b-46fb-8291-8152f5d197c4))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "lsf-kicad:LFE5UM-45F-6BG381x") (at 118.11 106.68 0) (unit 2)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(in_bom yes) (on_board yes)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "U604" (id 0) (at 113.03 148.59 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify left))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "~" (id 1) (at 93.98 161.29 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) (justify left))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "" (id 2) (at 118.11 106.68 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "https://www.latticesemi.com/view_document?document_id=50461" (id 3) (at 118.11 106.68 0)
Place I/Q and SPI of FPGA Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-03 03:52:35 -06:00
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)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 227.33 91.44 180) (unit 1)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(in_bom yes) (on_board yes)
(uuid ea6b3fde-7307-470a-a8b8-e20791d5965a)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "R615" (id 0) (at 228.8286 90.2716 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "TBD" (id 1) (at 228.8286 92.583 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) (justify right))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 227.33 91.44 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 227.33 91.44 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 227.33 91.44 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "" (id 5) (at 227.33 91.44 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "" (id 6) (at 227.33 91.44 0)
Add LED indicators for DONE and INITN Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 06:21:31 -06:00
(effects (font (size 1.27 1.27)) hide)
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(pin "1" (uuid 4bd19295-2e80-4a6e-bf14-731e2478c083))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "lsf-kicad:IS25LE512M-xM") (at 165.1 115.57 0) (unit 1)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(in_bom yes) (on_board yes)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "U605" (id 0) (at 162.56 115.57 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "IS25LE512M-xM" (id 1) (at 146.05 127 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) (justify left))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm" (id 2) (at 166.37 100.33 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "https://www.issi.com/WW/pdf/IS25LE-WE-512M.pdf" (id 3) (at 166.37 128.27 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "power:GND") (at 90.17 162.56 0) (unit 1)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(in_bom yes) (on_board yes)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "#PWR0618" (id 0) (at 90.17 168.91 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "GND" (id 1) (at 90.297 166.9542 0))
(property "Footprint" "" (id 2) (at 90.17 162.56 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "" (id 3) (at 90.17 162.56 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
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(pin "1" (uuid 93bcc241-c156-4264-85fd-101c336260c7))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:C") (at 46.99 55.88 0) (unit 1)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(in_bom yes) (on_board yes)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "C604" (id 0) (at 45.72 60.7314 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) (justify right))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "100n" (id 1) (at 45.72 58.42 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) (justify right))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "Capacitor_SMD:C_0402_1005Metric" (id 2) (at 47.9552 59.69 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 46.99 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "KEMET" (id 4) (at 46.99 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Capacitor, 0402, 10%, 16V, X7R" (id 5) (at 46.99 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "C0402C104K4RACTU" (id 6) (at 46.99 55.88 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
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(pin "1" (uuid fe076478-9e3b-49aa-85dc-994042a14c28))
(pin "2" (uuid 3132de00-6e12-4b5f-9a4c-a5581308d4b8))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Connector:TestPoint") (at 80.01 154.94 180) (unit 1)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(in_bom no) (on_board yes)
(uuid f515255d-bc47-4a30-814e-db03d3b02c27)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "TP607" (id 0) (at 81.28 160.02 90)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) (justify left))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Value" "OSC_OE" (id 1) (at 78.74 160.02 90)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) (justify left))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Footprint" "TestPoint:TestPoint_Pad_D1.0mm" (id 2) (at 74.93 154.94 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 74.93 154.94 0)
Add oscillator in FPGA Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 10:22:44 -06:00
(effects (font (size 1.27 1.27)) hide)
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(pin "1" (uuid 9006b172-4c3d-415b-85a5-99635b5afe48))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 248.92 100.33 90) (unit 1)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(in_bom yes) (on_board yes)
(uuid f58f6b7a-5abe-42d5-92a7-6524c54ddb0f)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "R618" (id 0) (at 254 99.06 90))
(property "Value" "4.7k" (id 1) (at 254 101.6 90))
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 248.92 100.33 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 248.92 100.33 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 248.92 100.33 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "Vishay" (id 5) (at 248.92 100.33 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "CRCW04024K70FKEDC" (id 6) (at 248.92 100.33 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
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(pin "1" (uuid d6e39149-647d-449e-a197-23585c70f750))
(pin "2" (uuid 18498b78-8ec6-488c-9162-4b0143139a76))
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 234.95 82.55 0) (unit 1)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(in_bom yes) (on_board yes)
(uuid f78a285b-be9e-4741-b9e9-60bd01559d0b)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Reference" "R616" (id 0) (at 240.03 82.55 90))
(property "Value" "4.7k" (id 1) (at 237.49 82.55 90))
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 234.95 82.55 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
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Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 234.95 82.55 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 234.95 82.55 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "Vishay" (id 5) (at 234.95 82.55 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "CRCW04024K70FKEDC" (id 6) (at 234.95 82.55 0)
Add MSPI as default boot mode and NOR flash Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 07:50:18 -06:00
(effects (font (size 1.27 1.27)) hide)
)
(pin "1" (uuid 6dd08b5a-4213-4f7f-afa8-9530f9f48524))
(pin "2" (uuid 90fd1613-9cb0-45b0-87c4-169fbe752a92))
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(symbol (lib_id "Device:R_Small") (at 184.15 57.15 180) (unit 1)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(in_bom yes) (on_board yes)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(uuid ffde7cb4-b100-4ba4-8cd0-4659c9559f84)
(property "Reference" "R609" (id 0) (at 179.07 57.15 90))
(property "Value" "4.7k" (id 1) (at 181.61 57.15 90))
(property "Footprint" "Resistor_SMD:R_0402_1005Metric" (id 2) (at 184.15 57.15 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Datasheet" "~" (id 3) (at 184.15 57.15 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Description" "Resistor, 0402, 1%, 1/16W" (id 4) (at 184.15 57.15 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Mnf." "Vishay" (id 5) (at 184.15 57.15 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "PartNumber" "CRCW04024K70FKEDC" (id 6) (at 184.15 57.15 0)
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
(effects (font (size 1.27 1.27)) hide)
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "1" (uuid 53d70dd2-f3d1-43e1-8370-6e1f3bbc5b81))
(pin "2" (uuid 1b6c5d8a-e42f-49e4-b553-9c074161b328))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(sheet (at 24.13 19.05) (size 26.67 12.7) (fields_autoplaced)
(stroke (width 0.1524) (type solid) (color 0 0 0 0))
(fill (color 0 0 0 0.0000))
(uuid acd01b4f-6f7e-4d4f-91ea-ff659dfaed5c)
(property "Sheet name" "fpga-power" (id 0) (at 24.13 18.3384 0)
(effects (font (size 1.27 1.27)) (justify left bottom))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(property "Sheet file" "fpga-power.kicad_sch" (id 1) (at 24.13 32.3346 0)
(effects (font (size 1.27 1.27)) (justify left top))
Add decoupling capacitors in FPGA schematic Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22 Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-05 07:31:59 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "FPGA_EN" input (at 24.13 27.94 180)
(effects (font (size 1.27 1.27)) (justify left))
(uuid 2ac3e55b-fbb3-44b7-a6a6-9505e87ba332)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "FPGA_ΙΝ_3V3" input (at 24.13 22.86 180)
(effects (font (size 1.27 1.27)) (justify left))
(uuid 36377777-88c6-42aa-9889-59ff9e24273b)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "FPGA_1V1" output (at 50.8 27.94 0)
(effects (font (size 1.27 1.27)) (justify right))
(uuid 1335d16d-23a9-4f5a-b14e-d6bb3e61d87a)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "FPGA_2V5" output (at 50.8 25.4 0)
(effects (font (size 1.27 1.27)) (justify right))
(uuid b86d2c36-5ce5-4728-abd9-deee1efd85ea)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
)
Add SERDES bank and connect supply voltaged to GND * Add a fpga-power sheet * Add auto updated kicad files Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 02:28:44 -06:00
(pin "FPGA_3V3" output (at 50.8 22.86 0)
(effects (font (size 1.27 1.27)) (justify right))
(uuid 5c1abfda-5568-428d-af87-03da21cf1883)
Implement FPGA JTAG Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-04 05:01:09 -06:00
)
)
Add interfaces between modules (closes #1) Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 12:03:01 -06:00
)