Agis Zisimatos
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0ea9754b22
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Fix FPGA symbol anotation and footprint
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-08 18:07:34 +03:00 |
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Agis Zisimatos
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62e9a7579b
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Add SERDES bank and connect supply voltaged to GND
* Add a fpga-power sheet
* Add auto updated kicad files
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-08 11:28:44 +03:00 |
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Papadeas Pierros
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bd4ef8fe52
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Expose PV as top level sheet
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
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2022-04-01 10:46:44 +03:00 |
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Papadeas Pierros
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046229765a
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Add interfaces between modules (closes #1)
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
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2022-03-16 20:03:26 +02:00 |
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Ilias Daradimos
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5af3e504fc
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Add PV charging
Added bus charging
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-03-16 15:26:59 +02:00 |
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Ilias Daradimos
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cec9c42157
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Add 3.3V PSU
Add Battery monitor
Add 2.5V regulator
Add 1.1V regulator
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-03-16 15:26:05 +02:00 |
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Papadeas Pierros
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d98f5d08a7
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Add MCU module schematic
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
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2022-03-15 19:25:35 +02:00 |
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Vasilis Tsiligiannis
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3c07252fae
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Add initial KiCad project
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
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2022-02-21 13:11:33 +02:00 |