Commit Graph

17 Commits (12a4feb2ed742054e66abb9879d81292b5c994fd)

Author SHA1 Message Date
Vasilis Tsiligiannis 12a4feb2ed Add LSF contribution guide
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
2022-03-28 10:27:31 +03:00
Agis Zisimatos e73022566e Select ferrite bead for TRX
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-23 17:24:58 +02:00
Agis Zisimatos f03aa75813 Select I limit resistor
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-23 16:53:05 +02:00
Ilias Daradimos 055c01d8fa Move GND power flag to top sheet
Update symbols

Signed-off-by: Ilias Daradimos <ilias@libre.space>
2022-03-22 13:23:56 +02:00
Ilias Daradimos b8ad60e557 Reanotate sheets
Update symbol and port direction

Signed-off-by: Ilias Daradimos <ilias@libre.space>
2022-03-22 12:29:50 +02:00
Agis Zisimatos 57d5d87f9f Fixes uuid, maybe it is bug from previous version
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 11:21:57 +02:00
Agis Zisimatos 9d3e6155ef Add PSU for FPGA
Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 11:19:58 +02:00
Agis Zisimatos 0c57d0fecc Add ferrite bead in 3V3 supply voltage
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-22 11:19:06 +02:00
Agis Zisimatos 334406da80 Add initial transceiver schematic
Fixes #https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/5

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-03-17 21:17:23 +02:00
Papadeas Pierros 046229765a Add interfaces between modules (closes #1)
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-16 20:03:26 +02:00
Ilias Daradimos 5af3e504fc Add PV charging
Added bus charging

Signed-off-by: Ilias Daradimos <ilias@libre.space>
2022-03-16 15:26:59 +02:00
Ilias Daradimos cec9c42157 Add 3.3V PSU
Add Battery monitor
Add 2.5V regulator
Add 1.1V regulator

Signed-off-by: Ilias Daradimos <ilias@libre.space>
2022-03-16 15:26:05 +02:00
Ilias Daradimos 767a1432b2 Update battery-monitor.kicad_sch 2022-03-16 14:34:04 +02:00
Papadeas Pierros d98f5d08a7 Add MCU module schematic
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
2022-03-15 19:25:35 +02:00
Vasilis Tsiligiannis 7308bbf9eb Fix license to CERN-OHL-S
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
2022-03-02 16:17:38 +02:00
Vasilis Tsiligiannis 3c07252fae Add initial KiCad project
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
2022-02-21 13:11:33 +02:00
Vasilis Tsiligiannis e20713c1de Add license file
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
2022-02-21 10:38:44 +02:00