Commit Graph

8 Commits (65c1553f29907856e97f745ebbb7eb38dd968755)

Author SHA1 Message Date
Agis Zisimatos 65c1553f29 Add SPI routing of FPGA
* Route pull-up resistors of NOR flash
* Small fixes in AT86RF215, fixes #30
* Route pull-up and down resistors of JTAG

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-19 19:27:25 +03:00
Agis Zisimatos d22b3f5865 Route AT86RF215M, fixes #30
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-18 22:12:15 +03:00
Agis Zisimatos 1230dde0f7 Place and route NOR flash
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-12 18:01:06 +03:00
Agis Zisimatos 12dd47cf35 Define stack-up and manufacturer rules
* Define also net classes and pre-define traces and vias
* Fixes #2

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-12 16:31:58 +03:00
Agis Zisimatos bbb8da9459 Initial part placement
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-11 19:07:49 +03:00
Agis Zisimatos 0f946970ff Assign footprints
Use PQ9ish template

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 22:09:47 +03:00
Agis Zisimatos b4a8816f07 Add PQ9ish template
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-07 13:42:06 +03:00
Vasilis Tsiligiannis 1f24b26fbe Initialize empty KiCad project
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
2022-03-15 18:35:16 +02:00