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  • 6ce0099984 Ignore kicad tmp files spacecruft root 2022-07-31 15:22:20 -0600
  • 6c24d9bc60 Merge branch 'add-b2b-connector' into 'master' Agis Zisimatos 2022-07-29 13:26:35 +0000
  • d09ddc44bc Add B2B connector add-b2b-connector Agis Zisimatos 2022-07-29 16:16:39 +0300
  • 1a883289e1 Merge branch 'master' into 'master' Vasilis Tsiligiannis 2022-07-27 11:49:49 +0000
  • 8ba0aa0137 gitlab-ci: Introduce sign-off check master Vasilis Tsiligiannis 2022-07-06 21:31:16 +0300
  • 352116cbdc Merge branch 'fix-net-names' into 'master' Agis Zisimatos 2022-07-19 15:52:45 +0000
  • 7dd800fd65 Fix net names, PN and add connector for FE Agis Zisimatos 2022-07-19 18:49:46 +0300
  • 761591edfd Merge branch 'add-logo' into 'master' Agis Zisimatos 2022-07-19 10:39:30 +0000
  • df8add0c12 Add LSF logo and fix egde GND via Agis Zisimatos 2022-07-19 13:36:43 +0300
  • 15b31fcfbf Merge branch 'power-fixes' into 'master' Agis Zisimatos 2022-07-19 10:10:43 +0000
  • 9efb3758c7 Fixes in power part, #54 and #64 Agis Zisimatos 2022-07-19 13:08:57 +0300
  • e038c91c19 Merge branch 'missing-via' into 'master' Agis Zisimatos 2022-05-03 09:47:29 +0000
  • bb1401747f Add missing via in core power supply 0.1-production-1 Agis Zisimatos 2022-05-03 12:41:16 +0300
  • 9c9f711b7e Merge branch 'update-bom' into 'master' Agis Zisimatos 2022-05-02 11:39:10 +0000
  • 6780198daf Update BOM and create iBOM Agis Zisimatos 2022-04-30 20:36:18 +0300
  • 626c78dc9c Merge branch 'board-review' into 'master' Agis Zisimatos 2022-04-30 16:06:38 +0000
  • 5f59684ccc Fix mask leyer clearance Agis Zisimatos 2022-04-30 19:03:22 +0300
  • ca58d73eb6 Add more vias in power planes Agis Zisimatos 2022-04-30 18:41:48 +0300
  • 538108bb67 Fix TPS22950 footprint Agis Zisimatos 2022-04-30 17:48:22 +0300
  • f97d888e83 Fix via in pad in JTAG connector Agis Zisimatos 2022-04-30 14:52:25 +0300
  • cc07c2347f Add in-series resistors in FPGA-SPI Agis Zisimatos 2022-04-30 14:29:44 +0300
  • 77dad4e17f Fix clock-in in FPGA pins Agis Zisimatos 2022-04-30 13:13:09 +0300
  • 56630ed95c Merge branch 'add-silscreen' into 'master' Agis Zisimatos 2022-04-27 17:11:26 +0000
  • 5f79558cec Fix CLK test point Agis Zisimatos 2022-04-27 20:08:42 +0300
  • 077a05bce5 Fix small silkscreen clarity issues Papadeas Pierros 2022-04-27 15:20:17 +0300
  • fa98f4d20a Add silkscreen Agis Zisimatos 2022-04-26 18:31:39 +0300
  • 224eca08f6 Merge branch 'pcb-fixes' into 'master' Agis Zisimatos 2022-04-26 14:08:38 +0000
  • 8fc3b2df0d Update in PCB from sidloc schematic Agis Zisimatos 2022-04-26 17:04:15 +0300
  • 80b76fb00f Merge branch 'power-routing' into 'master' Agis Zisimatos 2022-04-26 10:17:20 +0000
  • aa2a8d5806 Route power of FPGA and finalize I/Q connections Agis Zisimatos 2022-04-26 13:13:08 +0300
  • 3e70c80cda Merge branch 'add-debug-fpga-led' into 'master' Agis Zisimatos 2022-04-19 16:58:54 +0000
  • ecf17cc8eb Add debug LED for FPGA in PCB Agis Zisimatos 2022-04-19 19:57:11 +0300
  • 3b20fc349b Merge branch 'routing-pcb' into 'master' Agis Zisimatos 2022-04-19 16:29:59 +0000
  • 65c1553f29 Add SPI routing of FPGA Agis Zisimatos 2022-04-19 19:27:25 +0300
  • d22b3f5865 Route AT86RF215M, fixes #30 Agis Zisimatos 2022-04-18 22:12:15 +0300
  • 961e955dbd Fix SPI_CLK connection Agis Zisimatos 2022-04-18 21:10:33 +0300
  • bfd78ef8b0 Merge branch 'define-manufacturer-rules' into 'master' Agis Zisimatos 2022-04-12 15:15:11 +0000
  • 1230dde0f7 Place and route NOR flash Agis Zisimatos 2022-04-12 18:01:06 +0300
  • 68d8f38590 Merge branch 'define-manufacturer-rules' into 'master' Agis Zisimatos 2022-04-12 13:32:37 +0000
  • 12dd47cf35 Define stack-up and manufacturer rules Agis Zisimatos 2022-04-12 16:02:42 +0300
  • d02659df74 Merge branch 'initial-placement' into 'master' Agis Zisimatos 2022-04-11 16:08:56 +0000
  • bbb8da9459 Initial part placement Agis Zisimatos 2022-04-11 19:07:49 +0300
  • ccf931d488 Merge branch 'assign-footprint' into 'master' Agis Zisimatos 2022-04-08 19:11:29 +0000
  • 0f946970ff Assign footprints Agis Zisimatos 2022-04-08 22:09:47 +0300
  • b49ed7b829 Merge branch 'select-connectors' into 'master' Agis Zisimatos 2022-04-07 16:02:20 +0000
  • c9c6807e57 Fix interface with MCU breadboard Agis Zisimatos 2022-04-07 19:01:15 +0300
  • b4a8816f07 Add PQ9ish template Agis Zisimatos 2022-04-07 13:42:06 +0300
  • 751f54fc0b Initialize schematics and define connectors Agis Zisimatos 2022-04-06 19:44:37 +0300
  • 34e13a7c39 Merge branch 'master' into 'master' Vasilis Tsiligiannis 2022-03-28 08:25:20 +0000
  • e14ddaa453 Add LSF contribution guide Vasilis Tsiligiannis 2022-03-28 10:28:46 +0300
  • a7ba62b326 Merge branch 'master' into 'master' Vasilis Tsiligiannis 2022-03-15 16:38:08 +0000
  • a097141eab Add SIDLOC schematic as a submodule Vasilis Tsiligiannis 2022-03-15 18:37:42 +0200
  • 3c54342cee Merge branch 'master' into 'master' Vasilis Tsiligiannis 2022-03-15 16:35:32 +0000
  • 1f24b26fbe Initialize empty KiCad project Vasilis Tsiligiannis 2022-03-15 18:35:16 +0200
  • 38b7e0ee2e Add license file Vasilis Tsiligiannis 2022-03-15 18:30:30 +0200