2009-06-05 06:42:42 -06:00
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/console.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2009-06-05 06:42:42 -06:00
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/radeon_drm.h>
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2016-06-08 10:47:27 -06:00
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#include <linux/pm_runtime.h>
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2009-09-20 22:33:58 -06:00
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#include <linux/vgaarb.h>
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2010-01-31 22:38:10 -07:00
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#include <linux/vga_switcheroo.h>
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2011-08-08 10:21:16 -06:00
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#include <linux/efi.h>
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2009-06-05 06:42:42 -06:00
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "atom.h"
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2010-04-12 14:21:53 -06:00
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static const char radeon_family_name[][16] = {
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"R100",
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"RV100",
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"RS100",
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"RV200",
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"RS200",
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"R200",
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"RV250",
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"RS300",
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"RV280",
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"R300",
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"R350",
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"RV350",
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"RV380",
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"R420",
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"R423",
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"RV410",
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"RS400",
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"RS480",
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"RS600",
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"RS690",
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"RS740",
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"RV515",
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"R520",
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"RV530",
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"RV560",
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"RV570",
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"R580",
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"R600",
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"RV610",
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"RV630",
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"RV670",
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"RV620",
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"RV635",
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"RS780",
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"RS880",
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"RV770",
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"RV730",
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"RV710",
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"RV740",
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"CEDAR",
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"REDWOOD",
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"JUNIPER",
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"CYPRESS",
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"HEMLOCK",
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2010-12-03 13:34:16 -07:00
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"PALM",
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2011-05-31 13:42:46 -06:00
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"SUMO",
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"SUMO2",
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2011-01-06 19:19:12 -07:00
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"BARTS",
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"TURKS",
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"CAICOS",
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2011-03-02 18:07:27 -07:00
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"CAYMAN",
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2012-03-20 15:18:28 -06:00
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"ARUBA",
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2012-03-20 15:17:59 -06:00
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"TAHITI",
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"PITCAIRN",
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"VERDE",
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2012-12-18 15:01:35 -07:00
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"OLAND",
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2012-07-26 16:53:55 -06:00
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"HAINAN",
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2013-06-07 09:36:11 -06:00
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"BONAIRE",
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"KAVERI",
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"KABINI",
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2013-08-06 13:13:36 -06:00
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"HAWAII",
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2014-04-30 16:40:48 -06:00
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"MULLINS",
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2010-04-12 14:21:53 -06:00
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"LAST",
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};
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2016-10-31 08:41:49 -06:00
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#if defined(CONFIG_VGA_SWITCHEROO)
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bool radeon_has_atpx_dgpu_power_cntl(void);
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bool radeon_is_atpx_hybrid(void);
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#else
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static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
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static inline bool radeon_is_atpx_hybrid(void) { return false; }
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#endif
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2014-07-18 09:54:20 -06:00
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#define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
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#define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1)
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struct radeon_px_quirk {
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u32 chip_vendor;
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u32 chip_device;
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u32 subsys_vendor;
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u32 subsys_device;
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u32 px_quirk_flags;
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};
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static struct radeon_px_quirk radeon_px_quirk_list[] = {
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/* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m)
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* https://bugzilla.kernel.org/show_bug.cgi?id=74551
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*/
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{ PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },
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/* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU
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* https://bugzilla.kernel.org/show_bug.cgi?id=51381
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*/
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{ PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },
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2014-09-22 15:28:29 -06:00
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/* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU
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* https://bugzilla.kernel.org/show_bug.cgi?id=51381
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*/
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{ PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
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2014-07-18 09:54:20 -06:00
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/* macbook pro 8.2 */
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{ PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP },
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{ 0, 0, 0, 0, 0 },
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};
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2014-04-10 20:29:01 -06:00
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bool radeon_is_px(struct drm_device *dev)
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{
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struct radeon_device *rdev = dev->dev_private;
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if (rdev->flags & RADEON_IS_PX)
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return true;
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return false;
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}
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2012-09-16 22:40:31 -06:00
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2014-07-18 09:54:20 -06:00
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static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
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{
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struct radeon_px_quirk *p = radeon_px_quirk_list;
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/* Apply PX quirks */
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while (p && p->chip_device != 0) {
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if (rdev->pdev->vendor == p->chip_vendor &&
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rdev->pdev->device == p->chip_device &&
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rdev->pdev->subsystem_vendor == p->subsys_vendor &&
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rdev->pdev->subsystem_device == p->subsys_device) {
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rdev->px_quirk_flags = p->px_quirk_flags;
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break;
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}
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++p;
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}
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if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
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rdev->flags &= ~RADEON_IS_PX;
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2016-10-31 08:41:49 -06:00
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/* disable PX is the system doesn't support dGPU power control or hybrid gfx */
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if (!radeon_is_atpx_hybrid() &&
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!radeon_has_atpx_dgpu_power_cntl())
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rdev->flags &= ~RADEON_IS_PX;
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2014-07-18 09:54:20 -06:00
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}
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2013-02-26 09:26:51 -07:00
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/**
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* radeon_program_register_sequence - program an array of registers.
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*
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* @rdev: radeon_device pointer
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* @registers: pointer to the register array
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* @array_size: size of the register array
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*
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* Programs an array or registers with and and or masks.
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* This is a helper for setting golden registers.
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*/
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void radeon_program_register_sequence(struct radeon_device *rdev,
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const u32 *registers,
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const u32 array_size)
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{
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u32 tmp, reg, and_mask, or_mask;
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int i;
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if (array_size % 3)
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return;
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for (i = 0; i < array_size; i +=3) {
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reg = registers[i + 0];
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and_mask = registers[i + 1];
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or_mask = registers[i + 2];
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if (and_mask == 0xffffffff) {
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tmp = or_mask;
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} else {
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tmp = RREG32(reg);
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tmp &= ~and_mask;
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tmp |= or_mask;
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}
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WREG32(reg, tmp);
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}
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}
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2013-10-02 11:01:36 -06:00
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void radeon_pci_config_reset(struct radeon_device *rdev)
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{
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pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
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}
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2012-07-17 12:02:33 -06:00
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/**
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* radeon_surface_init - Clear GPU surface registers.
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*
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* @rdev: radeon_device pointer
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*
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* Clear GPU surface registers (r1xx-r5xx).
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2009-06-23 08:12:54 -06:00
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*/
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2009-09-07 18:10:24 -06:00
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void radeon_surface_init(struct radeon_device *rdev)
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2009-06-23 08:12:54 -06:00
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{
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/* FIXME: check this out */
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if (rdev->family < CHIP_R600) {
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int i;
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2009-12-08 21:15:38 -07:00
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for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
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if (rdev->surface_regs[i].bo)
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radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
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else
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radeon_clear_surface_reg(rdev, i);
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2009-06-23 08:12:54 -06:00
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}
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2009-06-23 17:48:08 -06:00
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/* enable surfaces */
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WREG32(RADEON_SURFACE_CNTL, 0);
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2009-06-23 08:12:54 -06:00
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}
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}
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2009-06-05 06:42:42 -06:00
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/*
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* GPU scratch registers helpers function.
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*/
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2012-07-17 12:02:33 -06:00
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/**
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* radeon_scratch_init - Init scratch register driver information.
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*
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* @rdev: radeon_device pointer
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*
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* Init CP scratch register driver information (r1xx-r5xx)
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*/
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2009-09-07 18:10:24 -06:00
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void radeon_scratch_init(struct radeon_device *rdev)
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2009-06-05 06:42:42 -06:00
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{
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int i;
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/* FIXME: check this out */
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if (rdev->family < CHIP_R300) {
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rdev->scratch.num_reg = 5;
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} else {
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rdev->scratch.num_reg = 7;
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}
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2010-08-27 16:25:25 -06:00
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rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
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2009-06-05 06:42:42 -06:00
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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rdev->scratch.free[i] = true;
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2010-08-27 16:25:25 -06:00
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rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
|
2009-06-05 06:42:42 -06:00
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}
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}
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|
2012-07-17 12:02:33 -06:00
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/**
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* radeon_scratch_get - Allocate a scratch register
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*
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* @rdev: radeon_device pointer
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* @reg: scratch register mmio offset
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*
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* Allocate a CP scratch register for use by the driver (all asics).
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* Returns 0 on success or -EINVAL on failure.
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*/
|
2009-06-05 06:42:42 -06:00
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int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
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{
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int i;
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for (i = 0; i < rdev->scratch.num_reg; i++) {
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|
if (rdev->scratch.free[i]) {
|
|
|
|
rdev->scratch.free[i] = false;
|
|
|
|
*reg = rdev->scratch.reg[i];
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_scratch_free - Free a scratch register
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
* @reg: scratch register mmio offset
|
|
|
|
*
|
|
|
|
* Free a CP scratch register allocated for use by the driver (all asics)
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < rdev->scratch.num_reg; i++) {
|
|
|
|
if (rdev->scratch.reg[i] == reg) {
|
|
|
|
rdev->scratch.free[i] = true;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-03-04 10:47:46 -07:00
|
|
|
/*
|
|
|
|
* GPU doorbell aperture helpers function.
|
|
|
|
*/
|
|
|
|
/**
|
|
|
|
* radeon_doorbell_init - Init doorbell driver information.
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Init doorbell driver information (CIK)
|
|
|
|
* Returns 0 on success, error on failure.
|
|
|
|
*/
|
2014-01-06 08:21:40 -07:00
|
|
|
static int radeon_doorbell_init(struct radeon_device *rdev)
|
2013-03-04 10:47:46 -07:00
|
|
|
{
|
|
|
|
/* doorbell bar mapping */
|
|
|
|
rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
|
|
|
|
rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
|
|
|
|
|
2013-11-13 13:54:17 -07:00
|
|
|
rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
|
|
|
|
if (rdev->doorbell.num_doorbells == 0)
|
|
|
|
return -EINVAL;
|
2013-03-04 10:47:46 -07:00
|
|
|
|
2013-11-13 13:54:17 -07:00
|
|
|
rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
|
2013-03-04 10:47:46 -07:00
|
|
|
if (rdev->doorbell.ptr == NULL) {
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
|
|
|
|
DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
|
|
|
|
|
2013-11-13 13:54:17 -07:00
|
|
|
memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
|
2013-03-04 10:47:46 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* radeon_doorbell_fini - Tear down doorbell driver information.
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Tear down doorbell driver information (CIK)
|
|
|
|
*/
|
2014-01-06 08:21:40 -07:00
|
|
|
static void radeon_doorbell_fini(struct radeon_device *rdev)
|
2013-03-04 10:47:46 -07:00
|
|
|
{
|
|
|
|
iounmap(rdev->doorbell.ptr);
|
|
|
|
rdev->doorbell.ptr = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2013-11-13 13:54:17 -07:00
|
|
|
* radeon_doorbell_get - Allocate a doorbell entry
|
2013-03-04 10:47:46 -07:00
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
2013-11-13 13:54:17 -07:00
|
|
|
* @doorbell: doorbell index
|
2013-03-04 10:47:46 -07:00
|
|
|
*
|
2013-11-13 13:54:17 -07:00
|
|
|
* Allocate a doorbell for use by the driver (all asics).
|
2013-03-04 10:47:46 -07:00
|
|
|
* Returns 0 on success or -EINVAL on failure.
|
|
|
|
*/
|
|
|
|
int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
|
|
|
|
{
|
2013-11-13 13:54:17 -07:00
|
|
|
unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
|
|
|
|
if (offset < rdev->doorbell.num_doorbells) {
|
|
|
|
__set_bit(offset, rdev->doorbell.used);
|
|
|
|
*doorbell = offset;
|
|
|
|
return 0;
|
|
|
|
} else {
|
|
|
|
return -EINVAL;
|
2013-03-04 10:47:46 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
2013-11-13 13:54:17 -07:00
|
|
|
* radeon_doorbell_free - Free a doorbell entry
|
2013-03-04 10:47:46 -07:00
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
2013-11-13 13:54:17 -07:00
|
|
|
* @doorbell: doorbell index
|
2013-03-04 10:47:46 -07:00
|
|
|
*
|
2013-11-13 13:54:17 -07:00
|
|
|
* Free a doorbell allocated for use by the driver (all asics)
|
2013-03-04 10:47:46 -07:00
|
|
|
*/
|
|
|
|
void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
|
|
|
|
{
|
2013-11-13 13:54:17 -07:00
|
|
|
if (doorbell < rdev->doorbell.num_doorbells)
|
|
|
|
__clear_bit(doorbell, rdev->doorbell.used);
|
2013-03-04 10:47:46 -07:00
|
|
|
}
|
|
|
|
|
2014-01-28 05:43:19 -07:00
|
|
|
/**
|
|
|
|
* radeon_doorbell_get_kfd_info - Report doorbell configuration required to
|
|
|
|
* setup KFD
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
* @aperture_base: output returning doorbell aperture base physical address
|
|
|
|
* @aperture_size: output returning doorbell aperture size in bytes
|
|
|
|
* @start_offset: output returning # of doorbell bytes reserved for radeon.
|
|
|
|
*
|
|
|
|
* Radeon and the KFD share the doorbell aperture. Radeon sets it up,
|
|
|
|
* takes doorbells required for its own rings and reports the setup to KFD.
|
|
|
|
* Radeon reserved doorbells are at the start of the doorbell aperture.
|
|
|
|
*/
|
|
|
|
void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
|
|
|
|
phys_addr_t *aperture_base,
|
|
|
|
size_t *aperture_size,
|
|
|
|
size_t *start_offset)
|
|
|
|
{
|
|
|
|
/* The first num_doorbells are used by radeon.
|
|
|
|
* KFD takes whatever's left in the aperture. */
|
|
|
|
if (rdev->doorbell.size > rdev->doorbell.num_doorbells * sizeof(u32)) {
|
|
|
|
*aperture_base = rdev->doorbell.base;
|
|
|
|
*aperture_size = rdev->doorbell.size;
|
|
|
|
*start_offset = rdev->doorbell.num_doorbells * sizeof(u32);
|
|
|
|
} else {
|
|
|
|
*aperture_base = 0;
|
|
|
|
*aperture_size = 0;
|
|
|
|
*start_offset = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/*
|
|
|
|
* radeon_wb_*()
|
|
|
|
* Writeback is the the method by which the the GPU updates special pages
|
|
|
|
* in memory with the status of certain GPU events (fences, ring pointers,
|
|
|
|
* etc.).
|
|
|
|
*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* radeon_wb_disable - Disable Writeback
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Disables Writeback (all asics). Used for suspend.
|
|
|
|
*/
|
2010-08-27 16:25:25 -06:00
|
|
|
void radeon_wb_disable(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
rdev->wb.enabled = false;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_wb_fini - Disable Writeback and free memory
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Disables Writeback and frees the Writeback memory (all asics).
|
|
|
|
* Used at driver shutdown.
|
|
|
|
*/
|
2010-08-27 16:25:25 -06:00
|
|
|
void radeon_wb_fini(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
radeon_wb_disable(rdev);
|
|
|
|
if (rdev->wb.wb_obj) {
|
2013-06-06 15:51:21 -06:00
|
|
|
if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
|
|
|
|
radeon_bo_kunmap(rdev->wb.wb_obj);
|
|
|
|
radeon_bo_unpin(rdev->wb.wb_obj);
|
|
|
|
radeon_bo_unreserve(rdev->wb.wb_obj);
|
|
|
|
}
|
2010-08-27 16:25:25 -06:00
|
|
|
radeon_bo_unref(&rdev->wb.wb_obj);
|
|
|
|
rdev->wb.wb = NULL;
|
|
|
|
rdev->wb.wb_obj = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_wb_init- Init Writeback driver info and allocate memory
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Disables Writeback and frees the Writeback memory (all asics).
|
|
|
|
* Used at driver startup.
|
|
|
|
* Returns 0 on success or an -error on failure.
|
|
|
|
*/
|
2010-08-27 16:25:25 -06:00
|
|
|
int radeon_wb_init(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
int r;
|
|
|
|
|
|
|
|
if (rdev->wb.wb_obj == NULL) {
|
2011-02-18 09:59:16 -07:00
|
|
|
r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
|
2014-09-18 06:11:56 -06:00
|
|
|
RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
|
2014-07-17 04:01:08 -06:00
|
|
|
&rdev->wb.wb_obj);
|
2010-08-27 16:25:25 -06:00
|
|
|
if (r) {
|
|
|
|
dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
|
|
|
|
return r;
|
|
|
|
}
|
2013-06-06 15:51:21 -06:00
|
|
|
r = radeon_bo_reserve(rdev->wb.wb_obj, false);
|
|
|
|
if (unlikely(r != 0)) {
|
|
|
|
radeon_wb_fini(rdev);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
|
|
|
|
&rdev->wb.gpu_addr);
|
|
|
|
if (r) {
|
|
|
|
radeon_bo_unreserve(rdev->wb.wb_obj);
|
|
|
|
dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
|
|
|
|
radeon_wb_fini(rdev);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
|
2010-08-27 16:25:25 -06:00
|
|
|
radeon_bo_unreserve(rdev->wb.wb_obj);
|
2013-06-06 15:51:21 -06:00
|
|
|
if (r) {
|
|
|
|
dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
|
|
|
|
radeon_wb_fini(rdev);
|
|
|
|
return r;
|
|
|
|
}
|
2010-08-27 16:25:25 -06:00
|
|
|
}
|
|
|
|
|
2011-06-13 16:02:51 -06:00
|
|
|
/* clear wb memory */
|
|
|
|
memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
|
2010-09-04 03:04:34 -06:00
|
|
|
/* disable event_write fences */
|
|
|
|
rdev->wb.use_event = false;
|
2010-08-27 16:25:25 -06:00
|
|
|
/* disabled via module param */
|
2012-05-09 07:34:47 -06:00
|
|
|
if (radeon_no_wb == 1) {
|
2010-08-27 16:25:25 -06:00
|
|
|
rdev->wb.enabled = false;
|
2012-05-09 07:34:47 -06:00
|
|
|
} else {
|
2010-08-27 16:25:25 -06:00
|
|
|
if (rdev->flags & RADEON_IS_AGP) {
|
2012-01-03 07:48:38 -07:00
|
|
|
/* often unreliable on AGP */
|
|
|
|
rdev->wb.enabled = false;
|
|
|
|
} else if (rdev->family < CHIP_R300) {
|
|
|
|
/* often unreliable on pre-r300 */
|
2010-08-27 16:25:25 -06:00
|
|
|
rdev->wb.enabled = false;
|
2010-09-04 03:04:34 -06:00
|
|
|
} else {
|
2010-08-27 16:25:25 -06:00
|
|
|
rdev->wb.enabled = true;
|
2010-09-04 03:04:34 -06:00
|
|
|
/* event_write fences are only available on r600+ */
|
2012-05-09 07:34:47 -06:00
|
|
|
if (rdev->family >= CHIP_R600) {
|
2010-09-04 03:04:34 -06:00
|
|
|
rdev->wb.use_event = true;
|
2012-05-09 07:34:47 -06:00
|
|
|
}
|
2010-09-04 03:04:34 -06:00
|
|
|
}
|
2010-08-27 16:25:25 -06:00
|
|
|
}
|
2012-05-03 15:06:28 -06:00
|
|
|
/* always use writeback/events on NI, APUs */
|
|
|
|
if (rdev->family >= CHIP_PALM) {
|
2011-01-06 19:19:27 -07:00
|
|
|
rdev->wb.enabled = true;
|
|
|
|
rdev->wb.use_event = true;
|
|
|
|
}
|
2010-08-27 16:25:25 -06:00
|
|
|
|
|
|
|
dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
/**
|
|
|
|
* radeon_vram_location - try to find VRAM location
|
|
|
|
* @rdev: radeon device structure holding all necessary informations
|
|
|
|
* @mc: memory controller structure holding memory informations
|
|
|
|
* @base: base address at which to put VRAM
|
|
|
|
*
|
|
|
|
* Function will place try to place VRAM at base address provided
|
|
|
|
* as parameter (which is so far either PCI aperture address or
|
|
|
|
* for IGP TOM base address).
|
|
|
|
*
|
|
|
|
* If there is not enough space to fit the unvisible VRAM in the 32bits
|
|
|
|
* address space then we limit the VRAM size to the aperture.
|
|
|
|
*
|
|
|
|
* If we are using AGP and if the AGP aperture doesn't allow us to have
|
|
|
|
* room for all the VRAM than we restrict the VRAM to the PCI aperture
|
|
|
|
* size and print a warning.
|
|
|
|
*
|
|
|
|
* This function will never fails, worst case are limiting VRAM.
|
|
|
|
*
|
|
|
|
* Note: GTT start, end, size should be initialized before calling this
|
|
|
|
* function on AGP platform.
|
|
|
|
*
|
2011-03-30 19:57:33 -06:00
|
|
|
* Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
* this shouldn't be a problem as we are using the PCI aperture as a reference.
|
|
|
|
* Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
|
|
|
|
* not IGP.
|
|
|
|
*
|
|
|
|
* Note: we use mc_vram_size as on some board we need to program the mc to
|
|
|
|
* cover the whole aperture even if VRAM size is inferior to aperture size
|
|
|
|
* Novell bug 204882 + along with lots of ubuntu ones
|
|
|
|
*
|
|
|
|
* Note: when limiting vram it's safe to overwritte real_vram_size because
|
|
|
|
* we are not in case where real_vram_size is inferior to mc_vram_size (ie
|
|
|
|
* note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
|
|
|
|
* ones)
|
|
|
|
*
|
|
|
|
* Note: IGP TOM addr should be the same as the aperture addr, we don't
|
|
|
|
* explicitly check for that thought.
|
|
|
|
*
|
|
|
|
* FIXME: when reducing VRAM size align new size on power of 2.
|
2009-06-05 06:42:42 -06:00
|
|
|
*/
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
2012-10-23 07:53:16 -06:00
|
|
|
uint64_t limit = (uint64_t)radeon_vram_limit << 20;
|
|
|
|
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
mc->vram_start = base;
|
2013-04-08 09:13:01 -06:00
|
|
|
if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
|
|
|
|
mc->real_vram_size = mc->aper_size;
|
|
|
|
mc->mc_vram_size = mc->aper_size;
|
|
|
|
}
|
|
|
|
mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
|
2010-08-16 09:54:36 -06:00
|
|
|
if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
|
|
|
|
mc->real_vram_size = mc->aper_size;
|
|
|
|
mc->mc_vram_size = mc->aper_size;
|
|
|
|
}
|
|
|
|
mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
|
2012-10-23 07:53:16 -06:00
|
|
|
if (limit && limit < mc->real_vram_size)
|
|
|
|
mc->real_vram_size = limit;
|
2010-12-03 12:37:21 -07:00
|
|
|
dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
mc->mc_vram_size >> 20, mc->vram_start,
|
|
|
|
mc->vram_end, mc->real_vram_size >> 20);
|
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
/**
|
|
|
|
* radeon_gtt_location - try to find GTT location
|
|
|
|
* @rdev: radeon device structure holding all necessary informations
|
|
|
|
* @mc: memory controller structure holding memory informations
|
|
|
|
*
|
|
|
|
* Function will place try to place GTT before or after VRAM.
|
|
|
|
*
|
|
|
|
* If GTT size is bigger than space left then we ajust GTT size.
|
|
|
|
* Thus function will never fails.
|
|
|
|
*
|
|
|
|
* FIXME: when reducing GTT size align new size on power of 2.
|
|
|
|
*/
|
|
|
|
void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
|
|
|
|
{
|
|
|
|
u64 size_af, size_bf;
|
|
|
|
|
2013-04-08 09:13:01 -06:00
|
|
|
size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
|
2010-07-15 08:51:10 -06:00
|
|
|
size_bf = mc->vram_start & ~mc->gtt_base_align;
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
if (size_bf > size_af) {
|
|
|
|
if (mc->gtt_size > size_bf) {
|
|
|
|
dev_warn(rdev->dev, "limiting GTT\n");
|
|
|
|
mc->gtt_size = size_bf;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
2010-07-15 08:51:10 -06:00
|
|
|
mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
|
2009-06-05 06:42:42 -06:00
|
|
|
} else {
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
if (mc->gtt_size > size_af) {
|
|
|
|
dev_warn(rdev->dev, "limiting GTT\n");
|
|
|
|
mc->gtt_size = size_af;
|
|
|
|
}
|
2010-07-15 08:51:10 -06:00
|
|
|
mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
|
2010-12-03 12:37:21 -07:00
|
|
|
dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
|
drm/radeon/kms: simplify memory controller setup V2
Get rid of _location and use _start/_end also simplify the
computation of vram_start|end & gtt_start|end. For R1XX-R2XX
we place VRAM at the same address of PCI aperture, those GPU
shouldn't have much memory and seems to behave better when
setup that way. For R3XX and newer we place VRAM at 0. For
R6XX-R7XX AGP we place VRAM before or after AGP aperture this
might limit to limit the VRAM size but it's very unlikely.
For IGP we don't change the VRAM placement.
Tested on (compiz,quake3,suspend/resume):
PCI/PCIE:RV280,R420,RV515,RV570,RV610,RV710
AGP:RV100,RV280,R420,RV350,RV620(RPB*),RV730
IGP:RS480(RPB*),RS690,RS780(RPB*),RS880
RPB: resume previously broken
V2 correct commit message to reflect more accurately the bug
and move VRAM placement to 0 for most of the GPU to avoid
limiting VRAM.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-02-17 14:54:29 -07:00
|
|
|
mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* GPU helpers function.
|
|
|
|
*/
|
2016-06-13 13:37:34 -06:00
|
|
|
|
|
|
|
/**
|
|
|
|
* radeon_device_is_virtual - check if we are running is a virtual environment
|
|
|
|
*
|
|
|
|
* Check if the asic has been passed through to a VM (all asics).
|
|
|
|
* Used at driver startup.
|
|
|
|
* Returns true if virtual or false if not.
|
|
|
|
*/
|
2016-08-22 12:29:44 -06:00
|
|
|
bool radeon_device_is_virtual(void)
|
2016-06-13 13:37:34 -06:00
|
|
|
{
|
|
|
|
#ifdef CONFIG_X86
|
|
|
|
return boot_cpu_has(X86_FEATURE_HYPERVISOR);
|
|
|
|
#else
|
|
|
|
return false;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_card_posted - check if the hw has already been initialized
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Check if the asic has been initialized (all asics).
|
|
|
|
* Used at driver startup.
|
|
|
|
* Returns true if initialized or false if not.
|
|
|
|
*/
|
2009-09-11 07:35:22 -06:00
|
|
|
bool radeon_card_posted(struct radeon_device *rdev)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
|
|
|
uint32_t reg;
|
|
|
|
|
2016-09-19 10:35:22 -06:00
|
|
|
/* for pass through, always force asic_init for CI */
|
|
|
|
if (rdev->family >= CHIP_BONAIRE &&
|
|
|
|
radeon_device_is_virtual())
|
2016-06-13 13:37:34 -06:00
|
|
|
return false;
|
|
|
|
|
2013-05-22 11:29:33 -06:00
|
|
|
/* required for EFI mode on macbook2,1 which uses an r5xx asic */
|
2012-11-14 02:42:35 -07:00
|
|
|
if (efi_enabled(EFI_BOOT) &&
|
2013-05-22 11:29:33 -06:00
|
|
|
(rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
|
|
|
|
(rdev->family < CHIP_R600))
|
2011-08-08 10:21:16 -06:00
|
|
|
return false;
|
|
|
|
|
2013-05-22 09:30:34 -06:00
|
|
|
if (ASIC_IS_NODCE(rdev))
|
|
|
|
goto check_memsize;
|
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
/* first check CRTCs */
|
2013-05-22 09:22:51 -06:00
|
|
|
if (ASIC_IS_DCE4(rdev)) {
|
2010-11-22 15:56:28 -07:00
|
|
|
reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
|
|
|
|
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
|
2013-05-22 09:22:51 -06:00
|
|
|
if (rdev->num_crtc >= 4) {
|
|
|
|
reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
|
|
|
|
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
|
|
|
|
}
|
|
|
|
if (rdev->num_crtc >= 6) {
|
|
|
|
reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
|
|
|
|
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
|
|
|
|
}
|
2010-01-12 15:54:34 -07:00
|
|
|
if (reg & EVERGREEN_CRTC_MASTER_EN)
|
|
|
|
return true;
|
|
|
|
} else if (ASIC_IS_AVIVO(rdev)) {
|
2009-06-05 06:42:42 -06:00
|
|
|
reg = RREG32(AVIVO_D1CRTC_CONTROL) |
|
|
|
|
RREG32(AVIVO_D2CRTC_CONTROL);
|
|
|
|
if (reg & AVIVO_CRTC_EN) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
reg = RREG32(RADEON_CRTC_GEN_CNTL) |
|
|
|
|
RREG32(RADEON_CRTC2_GEN_CNTL);
|
|
|
|
if (reg & RADEON_CRTC_EN) {
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-05-22 09:30:34 -06:00
|
|
|
check_memsize:
|
2009-06-05 06:42:42 -06:00
|
|
|
/* then check MEM_SIZE, in case the crtcs are off */
|
|
|
|
if (rdev->family >= CHIP_R600)
|
|
|
|
reg = RREG32(R600_CONFIG_MEMSIZE);
|
|
|
|
else
|
|
|
|
reg = RREG32(RADEON_CONFIG_MEMSIZE);
|
|
|
|
|
|
|
|
if (reg)
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_update_bandwidth_info - update display bandwidth params
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Used when sclk/mclk are switched or display modes are set.
|
|
|
|
* params are used to calculate display watermarks (all asics)
|
|
|
|
*/
|
2010-03-16 18:54:38 -06:00
|
|
|
void radeon_update_bandwidth_info(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
fixed20_12 a;
|
2010-08-10 10:33:20 -06:00
|
|
|
u32 sclk = rdev->pm.current_sclk;
|
|
|
|
u32 mclk = rdev->pm.current_mclk;
|
2010-03-16 18:54:38 -06:00
|
|
|
|
2010-08-10 10:33:20 -06:00
|
|
|
/* sclk/mclk in Mhz */
|
|
|
|
a.full = dfixed_const(100);
|
|
|
|
rdev->pm.sclk.full = dfixed_const(sclk);
|
|
|
|
rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
|
|
|
|
rdev->pm.mclk.full = dfixed_const(mclk);
|
|
|
|
rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
|
2010-03-16 18:54:38 -06:00
|
|
|
|
2010-08-10 10:33:20 -06:00
|
|
|
if (rdev->flags & RADEON_IS_IGP) {
|
2010-04-27 19:46:42 -06:00
|
|
|
a.full = dfixed_const(16);
|
2010-03-16 18:54:38 -06:00
|
|
|
/* core_bandwidth = sclk(Mhz) * 16 */
|
2010-04-27 19:46:42 -06:00
|
|
|
rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
|
2010-03-16 18:54:38 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_boot_test_post_card - check and possibly initialize the hw
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Check if the asic is initialized and if not, attempt to initialize
|
|
|
|
* it (all asics).
|
|
|
|
* Returns true if initialized or false if not.
|
|
|
|
*/
|
2009-11-30 21:06:31 -07:00
|
|
|
bool radeon_boot_test_post_card(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
if (radeon_card_posted(rdev))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
if (rdev->bios) {
|
|
|
|
DRM_INFO("GPU not posted. posting now...\n");
|
|
|
|
if (rdev->is_atom_bios)
|
|
|
|
atom_asic_init(rdev->mode_info.atom_context);
|
|
|
|
else
|
|
|
|
radeon_combios_asic_init(rdev->ddev);
|
|
|
|
return true;
|
|
|
|
} else {
|
|
|
|
dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_dummy_page_init - init dummy page used by the driver
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Allocate the dummy page used by the driver (all asics).
|
|
|
|
* This dummy page is used by the driver as a filler for gart entries
|
|
|
|
* when pages are taken out of the GART
|
|
|
|
* Returns 0 on sucess, -ENOMEM on failure.
|
|
|
|
*/
|
2009-09-07 18:10:24 -06:00
|
|
|
int radeon_dummy_page_init(struct radeon_device *rdev)
|
|
|
|
{
|
2010-02-04 23:00:07 -07:00
|
|
|
if (rdev->dummy_page.page)
|
|
|
|
return 0;
|
2009-09-07 18:10:24 -06:00
|
|
|
rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
|
|
|
|
if (rdev->dummy_page.page == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
|
|
|
|
0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
|
2010-08-09 22:48:58 -06:00
|
|
|
if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
|
|
|
|
dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
|
2009-09-07 18:10:24 -06:00
|
|
|
__free_page(rdev->dummy_page.page);
|
|
|
|
rdev->dummy_page.page = NULL;
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2015-01-21 01:36:35 -07:00
|
|
|
rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr,
|
|
|
|
RADEON_GART_PAGE_DUMMY);
|
2009-09-07 18:10:24 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_dummy_page_fini - free dummy page used by the driver
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Frees the dummy page used by the driver (all asics).
|
|
|
|
*/
|
2009-09-07 18:10:24 -06:00
|
|
|
void radeon_dummy_page_fini(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
if (rdev->dummy_page.page == NULL)
|
|
|
|
return;
|
|
|
|
pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
|
|
|
|
PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
|
|
|
|
__free_page(rdev->dummy_page.page);
|
|
|
|
rdev->dummy_page.page = NULL;
|
|
|
|
}
|
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
|
|
|
|
/* ATOM accessor methods */
|
2012-07-17 12:02:33 -06:00
|
|
|
/*
|
|
|
|
* ATOM is an interpreted byte code stored in tables in the vbios. The
|
|
|
|
* driver registers callbacks to access registers and the interpreter
|
|
|
|
* in the driver parses the tables and executes then to program specific
|
|
|
|
* actions (set display modes, asic init, etc.). See radeon_atombios.c,
|
|
|
|
* atombios.h, and atom.c
|
|
|
|
*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* cail_pll_read - read PLL register
|
|
|
|
*
|
|
|
|
* @info: atom card_info pointer
|
|
|
|
* @reg: PLL register offset
|
|
|
|
*
|
|
|
|
* Provides a PLL register accessor for the atom interpreter (r4xx+).
|
|
|
|
* Returns the value of the PLL register.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
uint32_t r;
|
|
|
|
|
|
|
|
r = rdev->pll_rreg(rdev, reg);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* cail_pll_write - write PLL register
|
|
|
|
*
|
|
|
|
* @info: atom card_info pointer
|
|
|
|
* @reg: PLL register offset
|
|
|
|
* @val: value to write to the pll register
|
|
|
|
*
|
|
|
|
* Provides a PLL register accessor for the atom interpreter (r4xx+).
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
|
|
|
|
rdev->pll_wreg(rdev, reg, val);
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* cail_mc_read - read MC (Memory Controller) register
|
|
|
|
*
|
|
|
|
* @info: atom card_info pointer
|
|
|
|
* @reg: MC register offset
|
|
|
|
*
|
|
|
|
* Provides an MC register accessor for the atom interpreter (r4xx+).
|
|
|
|
* Returns the value of the MC register.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
uint32_t r;
|
|
|
|
|
|
|
|
r = rdev->mc_rreg(rdev, reg);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* cail_mc_write - write MC (Memory Controller) register
|
|
|
|
*
|
|
|
|
* @info: atom card_info pointer
|
|
|
|
* @reg: MC register offset
|
|
|
|
* @val: value to write to the pll register
|
|
|
|
*
|
|
|
|
* Provides a MC register accessor for the atom interpreter (r4xx+).
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
|
|
|
|
rdev->mc_wreg(rdev, reg, val);
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* cail_reg_write - write MMIO register
|
|
|
|
*
|
|
|
|
* @info: atom card_info pointer
|
|
|
|
* @reg: MMIO register offset
|
|
|
|
* @val: value to write to the pll register
|
|
|
|
*
|
|
|
|
* Provides a MMIO register accessor for the atom interpreter (r4xx+).
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
|
|
|
|
WREG32(reg*4, val);
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* cail_reg_read - read MMIO register
|
|
|
|
*
|
|
|
|
* @info: atom card_info pointer
|
|
|
|
* @reg: MMIO register offset
|
|
|
|
*
|
|
|
|
* Provides an MMIO register accessor for the atom interpreter (r4xx+).
|
|
|
|
* Returns the value of the MMIO register.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
uint32_t r;
|
|
|
|
|
|
|
|
r = RREG32(reg*4);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* cail_ioreg_write - write IO register
|
|
|
|
*
|
|
|
|
* @info: atom card_info pointer
|
|
|
|
* @reg: IO register offset
|
|
|
|
* @val: value to write to the pll register
|
|
|
|
*
|
|
|
|
* Provides a IO register accessor for the atom interpreter (r4xx+).
|
|
|
|
*/
|
2010-06-30 09:52:50 -06:00
|
|
|
static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
|
|
|
|
WREG32_IO(reg*4, val);
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* cail_ioreg_read - read IO register
|
|
|
|
*
|
|
|
|
* @info: atom card_info pointer
|
|
|
|
* @reg: IO register offset
|
|
|
|
*
|
|
|
|
* Provides an IO register accessor for the atom interpreter (r4xx+).
|
|
|
|
* Returns the value of the IO register.
|
|
|
|
*/
|
2010-06-30 09:52:50 -06:00
|
|
|
static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = info->dev->dev_private;
|
|
|
|
uint32_t r;
|
|
|
|
|
|
|
|
r = RREG32_IO(reg*4);
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_atombios_init - init the driver info and callbacks for atombios
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Initializes the driver info and register access callbacks for the
|
|
|
|
* ATOM interpreter (r4xx+).
|
|
|
|
* Returns 0 on sucess, -ENOMEM on failure.
|
|
|
|
* Called at driver startup.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
int radeon_atombios_init(struct radeon_device *rdev)
|
|
|
|
{
|
2009-10-27 13:08:01 -06:00
|
|
|
struct card_info *atom_card_info =
|
|
|
|
kzalloc(sizeof(struct card_info), GFP_KERNEL);
|
|
|
|
|
|
|
|
if (!atom_card_info)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
rdev->mode_info.atom_card_info = atom_card_info;
|
|
|
|
atom_card_info->dev = rdev->ddev;
|
|
|
|
atom_card_info->reg_read = cail_reg_read;
|
|
|
|
atom_card_info->reg_write = cail_reg_write;
|
2010-06-30 09:52:50 -06:00
|
|
|
/* needed for iio ops */
|
|
|
|
if (rdev->rio_mem) {
|
|
|
|
atom_card_info->ioreg_read = cail_ioreg_read;
|
|
|
|
atom_card_info->ioreg_write = cail_ioreg_write;
|
|
|
|
} else {
|
|
|
|
DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
|
|
|
|
atom_card_info->ioreg_read = cail_reg_read;
|
|
|
|
atom_card_info->ioreg_write = cail_reg_write;
|
|
|
|
}
|
2009-10-27 13:08:01 -06:00
|
|
|
atom_card_info->mc_read = cail_mc_read;
|
|
|
|
atom_card_info->mc_write = cail_mc_write;
|
|
|
|
atom_card_info->pll_read = cail_pll_read;
|
|
|
|
atom_card_info->pll_write = cail_pll_write;
|
|
|
|
|
|
|
|
rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
|
2013-02-11 14:34:32 -07:00
|
|
|
if (!rdev->mode_info.atom_context) {
|
|
|
|
radeon_atombios_fini(rdev);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
2009-12-16 16:00:46 -07:00
|
|
|
mutex_init(&rdev->mode_info.atom_context->mutex);
|
2014-11-10 16:16:15 -07:00
|
|
|
mutex_init(&rdev->mode_info.atom_context->scratch_mutex);
|
2009-06-05 06:42:42 -06:00
|
|
|
radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
|
2009-11-16 13:29:46 -07:00
|
|
|
atom_allocate_fb_scratch(rdev->mode_info.atom_context);
|
2009-06-05 06:42:42 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_atombios_fini - free the driver info and callbacks for atombios
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Frees the driver info and register access callbacks for the ATOM
|
|
|
|
* interpreter (r4xx+).
|
|
|
|
* Called at driver shutdown.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
void radeon_atombios_fini(struct radeon_device *rdev)
|
|
|
|
{
|
2009-12-09 09:39:16 -07:00
|
|
|
if (rdev->mode_info.atom_context) {
|
|
|
|
kfree(rdev->mode_info.atom_context->scratch);
|
|
|
|
}
|
2013-02-11 14:34:32 -07:00
|
|
|
kfree(rdev->mode_info.atom_context);
|
|
|
|
rdev->mode_info.atom_context = NULL;
|
2009-10-27 13:08:01 -06:00
|
|
|
kfree(rdev->mode_info.atom_card_info);
|
2013-02-11 14:34:32 -07:00
|
|
|
rdev->mode_info.atom_card_info = NULL;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/* COMBIOS */
|
|
|
|
/*
|
|
|
|
* COMBIOS is the bios format prior to ATOM. It provides
|
|
|
|
* command tables similar to ATOM, but doesn't have a unified
|
|
|
|
* parser. See radeon_combios.c
|
|
|
|
*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* radeon_combios_init - init the driver info for combios
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Initializes the driver info for combios (r1xx-r3xx).
|
|
|
|
* Returns 0 on sucess.
|
|
|
|
* Called at driver startup.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
int radeon_combios_init(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_combios_fini - free the driver info for combios
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Frees the driver info for combios (r1xx-r3xx).
|
|
|
|
* Called at driver shutdown.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
void radeon_combios_fini(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/* if we get transitioned to only one device, take VGA back */
|
|
|
|
/**
|
|
|
|
* radeon_vga_set_decode - enable/disable vga decode
|
|
|
|
*
|
|
|
|
* @cookie: radeon_device pointer
|
|
|
|
* @state: enable/disable vga decode
|
|
|
|
*
|
|
|
|
* Enable/disable vga decode (all asics).
|
|
|
|
* Returns VGA resource flags.
|
|
|
|
*/
|
2009-09-20 22:33:58 -06:00
|
|
|
static unsigned int radeon_vga_set_decode(void *cookie, bool state)
|
|
|
|
{
|
|
|
|
struct radeon_device *rdev = cookie;
|
|
|
|
radeon_vga_set_state(rdev, state);
|
|
|
|
if (state)
|
|
|
|
return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
|
|
|
|
VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
|
|
|
|
else
|
|
|
|
return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
|
|
|
|
}
|
2009-10-07 22:03:05 -06:00
|
|
|
|
2012-10-23 07:53:16 -06:00
|
|
|
/**
|
|
|
|
* radeon_check_pot_argument - check that argument is a power of two
|
|
|
|
*
|
|
|
|
* @arg: value to check
|
|
|
|
*
|
|
|
|
* Validates that a certain argument is a power of two (all asics).
|
|
|
|
* Returns true if argument is valid.
|
|
|
|
*/
|
|
|
|
static bool radeon_check_pot_argument(int arg)
|
|
|
|
{
|
|
|
|
return (arg & (arg - 1)) == 0;
|
|
|
|
}
|
|
|
|
|
2015-07-02 17:54:12 -06:00
|
|
|
/**
|
|
|
|
* Determine a sensible default GART size according to ASIC family.
|
|
|
|
*
|
|
|
|
* @family ASIC family name
|
|
|
|
*/
|
|
|
|
static int radeon_gart_size_auto(enum radeon_family family)
|
|
|
|
{
|
|
|
|
/* default to a larger gart size on newer asics */
|
|
|
|
if (family >= CHIP_TAHITI)
|
|
|
|
return 2048;
|
|
|
|
else if (family >= CHIP_RV770)
|
|
|
|
return 1024;
|
|
|
|
else
|
|
|
|
return 512;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_check_arguments - validate module params
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Validates certain module parameters and updates
|
|
|
|
* the associated values used by the driver (all asics).
|
|
|
|
*/
|
2012-08-31 11:43:50 -06:00
|
|
|
static void radeon_check_arguments(struct radeon_device *rdev)
|
2009-12-11 13:18:34 -07:00
|
|
|
{
|
|
|
|
/* vramlimit must be a power of two */
|
2012-10-23 07:53:16 -06:00
|
|
|
if (!radeon_check_pot_argument(radeon_vram_limit)) {
|
2009-12-11 13:18:34 -07:00
|
|
|
dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
|
|
|
|
radeon_vram_limit);
|
|
|
|
radeon_vram_limit = 0;
|
|
|
|
}
|
2012-10-23 07:53:16 -06:00
|
|
|
|
2013-07-05 15:16:51 -06:00
|
|
|
if (radeon_gart_size == -1) {
|
2015-07-02 17:54:12 -06:00
|
|
|
radeon_gart_size = radeon_gart_size_auto(rdev->family);
|
2013-07-05 15:16:51 -06:00
|
|
|
}
|
2009-12-11 13:18:34 -07:00
|
|
|
/* gtt size must be power of two and greater or equal to 32M */
|
2012-10-23 07:53:16 -06:00
|
|
|
if (radeon_gart_size < 32) {
|
2013-07-05 15:16:51 -06:00
|
|
|
dev_warn(rdev->dev, "gart size (%d) too small\n",
|
2009-12-11 13:18:34 -07:00
|
|
|
radeon_gart_size);
|
2015-07-02 17:54:12 -06:00
|
|
|
radeon_gart_size = radeon_gart_size_auto(rdev->family);
|
2012-10-23 07:53:16 -06:00
|
|
|
} else if (!radeon_check_pot_argument(radeon_gart_size)) {
|
2009-12-11 13:18:34 -07:00
|
|
|
dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
|
|
|
|
radeon_gart_size);
|
2015-07-02 17:54:12 -06:00
|
|
|
radeon_gart_size = radeon_gart_size_auto(rdev->family);
|
2009-12-11 13:18:34 -07:00
|
|
|
}
|
2012-10-23 07:53:16 -06:00
|
|
|
rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
|
|
|
|
|
2009-12-11 13:18:34 -07:00
|
|
|
/* AGP mode can only be -1, 1, 2, 4, 8 */
|
|
|
|
switch (radeon_agpmode) {
|
|
|
|
case -1:
|
|
|
|
case 0:
|
|
|
|
case 1:
|
|
|
|
case 2:
|
|
|
|
case 4:
|
|
|
|
case 8:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
|
|
|
|
"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
|
|
|
|
radeon_agpmode = 0;
|
|
|
|
break;
|
|
|
|
}
|
2014-06-05 21:47:32 -06:00
|
|
|
|
|
|
|
if (!radeon_check_pot_argument(radeon_vm_size)) {
|
|
|
|
dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
|
|
|
|
radeon_vm_size);
|
2014-07-18 05:56:56 -06:00
|
|
|
radeon_vm_size = 4;
|
2014-06-05 21:47:32 -06:00
|
|
|
}
|
|
|
|
|
2014-07-18 05:56:56 -06:00
|
|
|
if (radeon_vm_size < 1) {
|
2016-01-07 17:22:44 -07:00
|
|
|
dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n",
|
2014-06-05 21:47:32 -06:00
|
|
|
radeon_vm_size);
|
2014-07-18 05:56:56 -06:00
|
|
|
radeon_vm_size = 4;
|
2014-06-05 21:47:32 -06:00
|
|
|
}
|
|
|
|
|
2016-03-16 05:56:45 -06:00
|
|
|
/*
|
|
|
|
* Max GPUVM size for Cayman, SI and CI are 40 bits.
|
|
|
|
*/
|
2014-07-18 05:56:56 -06:00
|
|
|
if (radeon_vm_size > 1024) {
|
|
|
|
dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
|
2014-06-05 21:47:32 -06:00
|
|
|
radeon_vm_size);
|
2014-07-18 05:56:56 -06:00
|
|
|
radeon_vm_size = 4;
|
2014-06-05 21:47:32 -06:00
|
|
|
}
|
2014-06-05 21:56:50 -06:00
|
|
|
|
|
|
|
/* defines number of bits in page table versus page directory,
|
|
|
|
* a page is 4KB so we have 12 bits offset, minimum 9 bits in the
|
|
|
|
* page table and the remaining bits are in the page directory */
|
2014-07-19 05:55:58 -06:00
|
|
|
if (radeon_vm_block_size == -1) {
|
|
|
|
|
|
|
|
/* Total bits covered by PD + PTs */
|
2014-10-15 15:20:55 -06:00
|
|
|
unsigned bits = ilog2(radeon_vm_size) + 18;
|
2014-07-19 05:55:58 -06:00
|
|
|
|
|
|
|
/* Make sure the PD is 4K in size up to 8GB address space.
|
|
|
|
Above that split equal between PD and PTs */
|
|
|
|
if (radeon_vm_size <= 8)
|
|
|
|
radeon_vm_block_size = bits - 9;
|
|
|
|
else
|
|
|
|
radeon_vm_block_size = (bits + 3) / 2;
|
|
|
|
|
|
|
|
} else if (radeon_vm_block_size < 9) {
|
2014-07-18 05:56:56 -06:00
|
|
|
dev_warn(rdev->dev, "VM page table size (%d) too small\n",
|
2014-06-05 21:56:50 -06:00
|
|
|
radeon_vm_block_size);
|
|
|
|
radeon_vm_block_size = 9;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (radeon_vm_block_size > 24 ||
|
2014-07-18 05:56:56 -06:00
|
|
|
(radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
|
|
|
|
dev_warn(rdev->dev, "VM page table size (%d) too large\n",
|
2014-06-05 21:56:50 -06:00
|
|
|
radeon_vm_block_size);
|
|
|
|
radeon_vm_block_size = 9;
|
|
|
|
}
|
2009-12-11 13:18:34 -07:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_switcheroo_set_state - set switcheroo state
|
|
|
|
*
|
|
|
|
* @pdev: pci dev pointer
|
2015-09-05 03:14:43 -06:00
|
|
|
* @state: vga_switcheroo state
|
2012-07-17 12:02:33 -06:00
|
|
|
*
|
|
|
|
* Callback for the switcheroo driver. Suspends or resumes the
|
|
|
|
* the asics before or after it is powered up using ACPI methods.
|
|
|
|
*/
|
2010-01-31 22:38:10 -07:00
|
|
|
static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
2014-07-18 09:54:20 -06:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
2012-09-16 22:40:31 -06:00
|
|
|
|
2014-04-10 20:29:01 -06:00
|
|
|
if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
|
2012-09-16 22:40:31 -06:00
|
|
|
return;
|
|
|
|
|
2010-01-31 22:38:10 -07:00
|
|
|
if (state == VGA_SWITCHEROO_ON) {
|
2013-01-07 07:18:47 -07:00
|
|
|
unsigned d3_delay = dev->pdev->d3_delay;
|
|
|
|
|
2017-02-28 05:55:52 -07:00
|
|
|
pr_info("radeon: switched on\n");
|
2010-01-31 22:38:10 -07:00
|
|
|
/* don't suspend or resume card normally */
|
2010-12-06 16:20:40 -07:00
|
|
|
dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
|
2013-01-07 07:18:47 -07:00
|
|
|
|
2014-07-18 09:54:20 -06:00
|
|
|
if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP))
|
2013-01-07 07:18:47 -07:00
|
|
|
dev->pdev->d3_delay = 20;
|
|
|
|
|
2012-09-16 22:40:31 -06:00
|
|
|
radeon_resume_kms(dev, true, true);
|
2013-01-07 07:18:47 -07:00
|
|
|
|
|
|
|
dev->pdev->d3_delay = d3_delay;
|
|
|
|
|
2010-12-06 16:20:40 -07:00
|
|
|
dev->switch_power_state = DRM_SWITCH_POWER_ON;
|
2010-05-31 17:09:06 -06:00
|
|
|
drm_kms_helper_poll_enable(dev);
|
2010-01-31 22:38:10 -07:00
|
|
|
} else {
|
2017-02-28 05:55:52 -07:00
|
|
|
pr_info("radeon: switched off\n");
|
2010-05-31 17:09:06 -06:00
|
|
|
drm_kms_helper_poll_disable(dev);
|
2010-12-06 16:20:40 -07:00
|
|
|
dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
|
2016-03-18 09:58:39 -06:00
|
|
|
radeon_suspend_kms(dev, true, true, false);
|
2010-12-06 16:20:40 -07:00
|
|
|
dev->switch_power_state = DRM_SWITCH_POWER_OFF;
|
2010-01-31 22:38:10 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_switcheroo_can_switch - see if switcheroo state can change
|
|
|
|
*
|
|
|
|
* @pdev: pci dev pointer
|
|
|
|
*
|
|
|
|
* Callback for the switcheroo driver. Check of the switcheroo
|
|
|
|
* state can be changed.
|
|
|
|
* Returns true if the state can be changed, false if not.
|
|
|
|
*/
|
2010-01-31 22:38:10 -07:00
|
|
|
static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
|
|
|
2013-11-03 12:46:34 -07:00
|
|
|
/*
|
|
|
|
* FIXME: open_count is protected by drm_global_mutex but that would lead to
|
|
|
|
* locking inversion with the driver load path. And the access here is
|
|
|
|
* completely racy anyway. So don't bother with locking for now.
|
|
|
|
*/
|
|
|
|
return dev->open_count == 0;
|
2010-01-31 22:38:10 -07:00
|
|
|
}
|
|
|
|
|
2012-05-10 23:51:17 -06:00
|
|
|
static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
|
|
|
|
.set_gpu_state = radeon_switcheroo_set_state,
|
|
|
|
.reprobe = NULL,
|
|
|
|
.can_switch = radeon_switcheroo_can_switch,
|
|
|
|
};
|
2010-01-31 22:38:10 -07:00
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_device_init - initialize the driver
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
* @pdev: drm dev pointer
|
|
|
|
* @pdev: pci dev pointer
|
|
|
|
* @flags: driver flags
|
|
|
|
*
|
|
|
|
* Initializes the driver info and hw (all asics).
|
|
|
|
* Returns 0 for success or an error on failure.
|
|
|
|
* Called at driver startup.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
int radeon_device_init(struct radeon_device *rdev,
|
|
|
|
struct drm_device *ddev,
|
|
|
|
struct pci_dev *pdev,
|
|
|
|
uint32_t flags)
|
|
|
|
{
|
2010-06-30 09:52:50 -06:00
|
|
|
int r, i;
|
2009-07-10 06:36:26 -06:00
|
|
|
int dma_bits;
|
2012-09-16 22:40:31 -06:00
|
|
|
bool runtime = false;
|
2009-06-05 06:42:42 -06:00
|
|
|
|
|
|
|
rdev->shutdown = false;
|
2009-09-11 07:35:22 -06:00
|
|
|
rdev->dev = &pdev->dev;
|
2009-06-05 06:42:42 -06:00
|
|
|
rdev->ddev = ddev;
|
|
|
|
rdev->pdev = pdev;
|
|
|
|
rdev->flags = flags;
|
|
|
|
rdev->family = flags & RADEON_FAMILY_MASK;
|
|
|
|
rdev->is_atom_bios = false;
|
|
|
|
rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
|
2013-07-05 15:16:51 -06:00
|
|
|
rdev->mc.gtt_size = 512 * 1024 * 1024;
|
2009-09-16 07:24:21 -06:00
|
|
|
rdev->accel_working = false;
|
2012-07-17 12:02:30 -06:00
|
|
|
/* set up ring ids */
|
|
|
|
for (i = 0; i < RADEON_NUM_RINGS; i++) {
|
|
|
|
rdev->ring[i].idx = i;
|
|
|
|
}
|
2016-10-25 06:00:45 -06:00
|
|
|
rdev->fence_context = dma_fence_context_alloc(RADEON_NUM_RINGS);
|
2010-04-12 14:21:53 -06:00
|
|
|
|
2016-04-14 11:16:35 -06:00
|
|
|
DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
|
|
|
|
radeon_family_name[rdev->family], pdev->vendor, pdev->device,
|
|
|
|
pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
|
2010-04-12 14:21:53 -06:00
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
/* mutex initialization are all done here so we
|
|
|
|
* can recall function without having locking issues */
|
2012-05-09 07:34:45 -06:00
|
|
|
mutex_init(&rdev->ring_lock);
|
2009-12-23 01:23:21 -07:00
|
|
|
mutex_init(&rdev->dc_hw_i2c_mutex);
|
2012-05-16 13:45:24 -06:00
|
|
|
atomic_set(&rdev->ih.lock, 0);
|
2009-11-20 06:29:23 -07:00
|
|
|
mutex_init(&rdev->gem.mutex);
|
2009-12-22 15:02:16 -07:00
|
|
|
mutex_init(&rdev->pm.mutex);
|
2012-08-09 08:34:17 -06:00
|
|
|
mutex_init(&rdev->gpu_clock_mutex);
|
2013-08-06 10:40:16 -06:00
|
|
|
mutex_init(&rdev->srbm_mutex);
|
2014-07-14 06:36:08 -06:00
|
|
|
mutex_init(&rdev->grbm_idx_mutex);
|
2012-05-11 06:57:18 -06:00
|
|
|
init_rwsem(&rdev->pm.mclk_lock);
|
2012-07-02 10:45:19 -06:00
|
|
|
init_rwsem(&rdev->exclusive_lock);
|
2010-01-07 16:22:47 -07:00
|
|
|
init_waitqueue_head(&rdev->irq.vblank_queue);
|
2014-08-07 01:36:03 -06:00
|
|
|
mutex_init(&rdev->mn_lock);
|
|
|
|
hash_init(rdev->mn_hash);
|
2012-05-10 11:00:06 -06:00
|
|
|
r = radeon_gem_init(rdev);
|
|
|
|
if (r)
|
|
|
|
return r;
|
2014-02-20 11:33:15 -07:00
|
|
|
|
2014-06-05 21:47:32 -06:00
|
|
|
radeon_check_arguments(rdev);
|
2012-10-08 07:45:46 -06:00
|
|
|
/* Adjust VM size here.
|
2014-06-05 21:47:32 -06:00
|
|
|
* Max GPUVM size for cayman+ is 40 bits.
|
2012-10-08 07:45:46 -06:00
|
|
|
*/
|
2014-07-18 05:56:56 -06:00
|
|
|
rdev->vm_manager.max_pfn = radeon_vm_size << 18;
|
2009-06-05 06:42:42 -06:00
|
|
|
|
2009-09-14 10:29:49 -06:00
|
|
|
/* Set asic functions */
|
|
|
|
r = radeon_asic_init(rdev);
|
2009-12-11 13:18:34 -07:00
|
|
|
if (r)
|
2009-09-14 10:29:49 -06:00
|
|
|
return r;
|
|
|
|
|
2010-03-21 12:02:25 -06:00
|
|
|
/* all of the newer IGP chips have an internal gart
|
|
|
|
* However some rs4xx report as AGP, so remove that here.
|
|
|
|
*/
|
|
|
|
if ((rdev->family >= CHIP_RS400) &&
|
|
|
|
(rdev->flags & RADEON_IS_IGP)) {
|
|
|
|
rdev->flags &= ~RADEON_IS_AGP;
|
|
|
|
}
|
|
|
|
|
2009-11-30 09:47:59 -07:00
|
|
|
if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
|
2009-10-06 11:04:29 -06:00
|
|
|
radeon_agp_disable(rdev);
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2013-04-08 09:13:01 -06:00
|
|
|
/* Set the internal MC address mask
|
|
|
|
* This is the max address of the GPU's
|
|
|
|
* internal address space.
|
|
|
|
*/
|
|
|
|
if (rdev->family >= CHIP_CAYMAN)
|
|
|
|
rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
|
|
|
|
else if (rdev->family >= CHIP_CEDAR)
|
|
|
|
rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */
|
|
|
|
else
|
|
|
|
rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */
|
|
|
|
|
2009-07-10 06:36:26 -06:00
|
|
|
/* set DMA mask + need_dma32 flags.
|
|
|
|
* PCIE - can handle 40-bits.
|
2011-10-05 08:02:57 -06:00
|
|
|
* IGP - can handle 40-bits
|
2009-07-10 06:36:26 -06:00
|
|
|
* AGP - generally dma32 is safest
|
2011-10-05 08:02:57 -06:00
|
|
|
* PCI - dma32 for legacy pci gart, 40 bits on newer asics
|
2009-07-10 06:36:26 -06:00
|
|
|
*/
|
|
|
|
rdev->need_dma32 = false;
|
|
|
|
if (rdev->flags & RADEON_IS_AGP)
|
|
|
|
rdev->need_dma32 = true;
|
2011-10-05 08:02:57 -06:00
|
|
|
if ((rdev->flags & RADEON_IS_PCI) &&
|
2012-08-28 14:50:22 -06:00
|
|
|
(rdev->family <= CHIP_RS740))
|
2009-07-10 06:36:26 -06:00
|
|
|
rdev->need_dma32 = true;
|
|
|
|
|
|
|
|
dma_bits = rdev->need_dma32 ? 32 : 40;
|
|
|
|
r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
|
2009-06-05 06:42:42 -06:00
|
|
|
if (r) {
|
2011-06-08 04:04:45 -06:00
|
|
|
rdev->need_dma32 = true;
|
2011-10-17 15:15:08 -06:00
|
|
|
dma_bits = 32;
|
2017-02-28 05:55:52 -07:00
|
|
|
pr_warn("radeon: No suitable DMA available\n");
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
2011-10-17 15:15:08 -06:00
|
|
|
r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
|
|
|
|
if (r) {
|
|
|
|
pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
|
2017-02-28 05:55:52 -07:00
|
|
|
pr_warn("radeon: No coherent DMA available\n");
|
2011-10-17 15:15:08 -06:00
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
|
|
|
|
/* Registers mapping */
|
|
|
|
/* TODO: block userspace mapping of io register */
|
2012-12-02 06:06:15 -07:00
|
|
|
spin_lock_init(&rdev->mmio_idx_lock);
|
2013-09-03 16:19:42 -06:00
|
|
|
spin_lock_init(&rdev->smc_idx_lock);
|
2013-09-03 17:00:09 -06:00
|
|
|
spin_lock_init(&rdev->pll_idx_lock);
|
|
|
|
spin_lock_init(&rdev->mc_idx_lock);
|
|
|
|
spin_lock_init(&rdev->pcie_idx_lock);
|
|
|
|
spin_lock_init(&rdev->pciep_idx_lock);
|
|
|
|
spin_lock_init(&rdev->pif_idx_lock);
|
|
|
|
spin_lock_init(&rdev->cg_idx_lock);
|
|
|
|
spin_lock_init(&rdev->uvd_idx_lock);
|
|
|
|
spin_lock_init(&rdev->rcu_idx_lock);
|
|
|
|
spin_lock_init(&rdev->didt_idx_lock);
|
|
|
|
spin_lock_init(&rdev->end_idx_lock);
|
2012-12-18 19:24:37 -07:00
|
|
|
if (rdev->family >= CHIP_BONAIRE) {
|
|
|
|
rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
|
|
|
|
rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
|
|
|
|
} else {
|
|
|
|
rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
|
|
|
|
rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
|
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
|
2016-11-30 18:21:10 -07:00
|
|
|
if (rdev->rmmio == NULL)
|
2009-06-05 06:42:42 -06:00
|
|
|
return -ENOMEM;
|
|
|
|
|
2013-03-04 10:47:46 -07:00
|
|
|
/* doorbell bar mapping */
|
|
|
|
if (rdev->family >= CHIP_BONAIRE)
|
|
|
|
radeon_doorbell_init(rdev);
|
|
|
|
|
2010-06-30 09:52:50 -06:00
|
|
|
/* io port mapping */
|
|
|
|
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
|
|
|
|
if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
|
|
|
|
rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
|
|
|
|
rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (rdev->rio_mem == NULL)
|
|
|
|
DRM_ERROR("Unable to find PCI I/O BAR\n");
|
|
|
|
|
2014-07-18 09:54:20 -06:00
|
|
|
if (rdev->flags & RADEON_IS_PX)
|
|
|
|
radeon_device_handle_px_quirks(rdev);
|
|
|
|
|
2009-09-20 22:33:58 -06:00
|
|
|
/* if we have > 1 VGA cards, then disable the radeon VGA resources */
|
2009-10-27 19:09:58 -06:00
|
|
|
/* this will fail for cards that aren't VGA class devices, just
|
|
|
|
* ignore it */
|
|
|
|
vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
|
2012-09-16 22:40:31 -06:00
|
|
|
|
2016-04-18 09:19:19 -06:00
|
|
|
if (rdev->flags & RADEON_IS_PX)
|
2012-09-16 22:40:31 -06:00
|
|
|
runtime = true;
|
2017-03-10 13:23:45 -07:00
|
|
|
if (!pci_is_thunderbolt_attached(rdev->pdev))
|
|
|
|
vga_switcheroo_register_client(rdev->pdev,
|
|
|
|
&radeon_switcheroo_ops, runtime);
|
2012-09-16 22:40:31 -06:00
|
|
|
if (runtime)
|
|
|
|
vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
|
2009-09-20 22:33:58 -06:00
|
|
|
|
2009-09-07 18:10:24 -06:00
|
|
|
r = radeon_init(rdev);
|
2009-10-06 11:04:29 -06:00
|
|
|
if (r)
|
2014-09-12 16:00:53 -06:00
|
|
|
goto failed;
|
2009-09-07 18:10:24 -06:00
|
|
|
|
2013-04-25 20:29:27 -06:00
|
|
|
r = radeon_gem_debugfs_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("registering gem debugfs failed (%d).\n", r);
|
2015-02-23 16:24:04 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
r = radeon_mst_debugfs_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
DRM_ERROR("registering mst debugfs failed (%d).\n", r);
|
2013-04-25 20:29:27 -06:00
|
|
|
}
|
|
|
|
|
2009-10-06 11:04:29 -06:00
|
|
|
if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
|
|
|
|
/* Acceleration not working on AGP card try again
|
|
|
|
* with fallback to PCI or PCIE GART
|
|
|
|
*/
|
2010-03-09 07:45:11 -07:00
|
|
|
radeon_asic_reset(rdev);
|
2009-10-06 11:04:29 -06:00
|
|
|
radeon_fini(rdev);
|
|
|
|
radeon_agp_disable(rdev);
|
|
|
|
r = radeon_init(rdev);
|
2009-09-14 10:29:49 -06:00
|
|
|
if (r)
|
2014-09-12 16:00:53 -06:00
|
|
|
goto failed;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
2013-12-18 12:07:14 -07:00
|
|
|
|
2014-08-24 06:52:46 -06:00
|
|
|
r = radeon_ib_ring_tests(rdev);
|
|
|
|
if (r)
|
|
|
|
DRM_ERROR("ib ring test failed (%d).\n", r);
|
|
|
|
|
2015-06-05 11:33:57 -06:00
|
|
|
/*
|
|
|
|
* Turks/Thames GPU will freeze whole laptop if DPM is not restarted
|
|
|
|
* after the CP ring have chew one packet at least. Hence here we stop
|
|
|
|
* and restart DPM after the radeon_ib_ring_tests().
|
|
|
|
*/
|
|
|
|
if (rdev->pm.dpm_enabled &&
|
|
|
|
(rdev->pm.pm_method == PM_METHOD_DPM) &&
|
|
|
|
(rdev->family == CHIP_TURKS) &&
|
|
|
|
(rdev->flags & RADEON_IS_MOBILITY)) {
|
|
|
|
mutex_lock(&rdev->pm.mutex);
|
|
|
|
radeon_dpm_disable(rdev);
|
|
|
|
radeon_dpm_enable(rdev);
|
|
|
|
mutex_unlock(&rdev->pm.mutex);
|
|
|
|
}
|
|
|
|
|
2011-09-27 04:31:00 -06:00
|
|
|
if ((radeon_testing & 1)) {
|
2013-09-23 08:38:26 -06:00
|
|
|
if (rdev->accel_working)
|
|
|
|
radeon_test_moves(rdev);
|
|
|
|
else
|
|
|
|
DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
|
2009-07-21 03:23:57 -06:00
|
|
|
}
|
2011-09-27 04:31:00 -06:00
|
|
|
if ((radeon_testing & 2)) {
|
2013-09-23 08:38:26 -06:00
|
|
|
if (rdev->accel_working)
|
|
|
|
radeon_test_syncing(rdev);
|
|
|
|
else
|
|
|
|
DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
|
2011-09-27 04:31:00 -06:00
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
if (radeon_benchmarking) {
|
2013-09-23 08:38:26 -06:00
|
|
|
if (rdev->accel_working)
|
|
|
|
radeon_benchmark(rdev, radeon_benchmarking);
|
|
|
|
else
|
|
|
|
DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
2009-09-10 13:46:48 -06:00
|
|
|
return 0;
|
2014-09-12 16:00:53 -06:00
|
|
|
|
|
|
|
failed:
|
2016-06-08 10:47:27 -06:00
|
|
|
/* balance pm_runtime_get_sync() in radeon_driver_unload_kms() */
|
|
|
|
if (radeon_is_px(ddev))
|
|
|
|
pm_runtime_put_noidle(ddev->dev);
|
2014-09-12 16:00:53 -06:00
|
|
|
if (runtime)
|
|
|
|
vga_switcheroo_fini_domain_pm_ops(rdev->dev);
|
|
|
|
return r;
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_device_fini - tear down the driver
|
|
|
|
*
|
|
|
|
* @rdev: radeon_device pointer
|
|
|
|
*
|
|
|
|
* Tear down the driver info (all asics).
|
|
|
|
* Called at driver shutdown.
|
|
|
|
*/
|
2009-06-05 06:42:42 -06:00
|
|
|
void radeon_device_fini(struct radeon_device *rdev)
|
|
|
|
{
|
|
|
|
DRM_INFO("radeon: finishing device.\n");
|
|
|
|
rdev->shutdown = true;
|
2010-03-09 07:45:12 -07:00
|
|
|
/* evict vram memory */
|
|
|
|
radeon_bo_evict_vram(rdev);
|
2009-10-01 10:02:11 -06:00
|
|
|
radeon_fini(rdev);
|
2017-03-10 13:23:45 -07:00
|
|
|
if (!pci_is_thunderbolt_attached(rdev->pdev))
|
|
|
|
vga_switcheroo_unregister_client(rdev->pdev);
|
2014-09-12 16:00:53 -06:00
|
|
|
if (rdev->flags & RADEON_IS_PX)
|
|
|
|
vga_switcheroo_fini_domain_pm_ops(rdev->dev);
|
2009-10-07 22:03:05 -06:00
|
|
|
vga_client_register(rdev->pdev, NULL, NULL, NULL);
|
2010-07-08 10:24:52 -06:00
|
|
|
if (rdev->rio_mem)
|
|
|
|
pci_iounmap(rdev->pdev, rdev->rio_mem);
|
2010-06-30 09:52:50 -06:00
|
|
|
rdev->rio_mem = NULL;
|
2009-06-05 06:42:42 -06:00
|
|
|
iounmap(rdev->rmmio);
|
|
|
|
rdev->rmmio = NULL;
|
2013-03-04 10:47:46 -07:00
|
|
|
if (rdev->family >= CHIP_BONAIRE)
|
|
|
|
radeon_doorbell_fini(rdev);
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Suspend & resume.
|
|
|
|
*/
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_suspend_kms - initiate device suspend
|
|
|
|
*
|
|
|
|
* @pdev: drm dev pointer
|
|
|
|
* @state: suspend state
|
|
|
|
*
|
|
|
|
* Puts the hw in the suspend state (all asics).
|
|
|
|
* Returns 0 for success or an error on failure.
|
|
|
|
* Called at driver suspend.
|
|
|
|
*/
|
2016-03-18 09:58:39 -06:00
|
|
|
int radeon_suspend_kms(struct drm_device *dev, bool suspend,
|
|
|
|
bool fbcon, bool freeze)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
2009-12-29 18:18:30 -07:00
|
|
|
struct radeon_device *rdev;
|
2009-06-05 06:42:42 -06:00
|
|
|
struct drm_crtc *crtc;
|
2010-06-02 10:08:41 -06:00
|
|
|
struct drm_connector *connector;
|
2011-08-25 11:39:48 -06:00
|
|
|
int i, r;
|
2009-06-05 06:42:42 -06:00
|
|
|
|
2009-12-29 18:18:30 -07:00
|
|
|
if (dev == NULL || dev->dev_private == NULL) {
|
2009-06-05 06:42:42 -06:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
2012-09-12 20:02:30 -06:00
|
|
|
|
2009-12-29 18:18:30 -07:00
|
|
|
rdev = dev->dev_private;
|
|
|
|
|
2016-09-19 10:20:18 -06:00
|
|
|
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
2010-01-31 22:38:10 -07:00
|
|
|
return 0;
|
2010-06-02 10:08:41 -06:00
|
|
|
|
2012-01-31 18:06:25 -07:00
|
|
|
drm_kms_helper_poll_disable(dev);
|
|
|
|
|
2015-09-23 12:26:45 -06:00
|
|
|
drm_modeset_lock_all(dev);
|
2010-06-02 10:08:41 -06:00
|
|
|
/* turn off display hw */
|
|
|
|
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
|
|
|
|
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
|
|
|
|
}
|
2015-09-23 12:26:45 -06:00
|
|
|
drm_modeset_unlock_all(dev);
|
2010-06-02 10:08:41 -06:00
|
|
|
|
2015-07-07 01:27:29 -06:00
|
|
|
/* unpin the front buffers and cursors */
|
2009-06-05 06:42:42 -06:00
|
|
|
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
|
2015-07-07 01:27:29 -06:00
|
|
|
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
|
2014-04-01 16:22:40 -06:00
|
|
|
struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
|
2009-11-20 06:29:23 -07:00
|
|
|
struct radeon_bo *robj;
|
2009-06-05 06:42:42 -06:00
|
|
|
|
2015-07-07 01:27:29 -06:00
|
|
|
if (radeon_crtc->cursor_bo) {
|
|
|
|
struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
|
|
|
|
r = radeon_bo_reserve(robj, false);
|
|
|
|
if (r == 0) {
|
|
|
|
radeon_bo_unpin(robj);
|
|
|
|
radeon_bo_unreserve(robj);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
if (rfb == NULL || rfb->obj == NULL) {
|
|
|
|
continue;
|
|
|
|
}
|
2011-02-18 09:59:17 -07:00
|
|
|
robj = gem_to_radeon_bo(rfb->obj);
|
2010-03-29 23:34:13 -06:00
|
|
|
/* don't unpin kernel fb objects */
|
|
|
|
if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
|
2009-11-20 06:29:23 -07:00
|
|
|
r = radeon_bo_reserve(robj, false);
|
2010-03-29 23:34:13 -06:00
|
|
|
if (r == 0) {
|
2009-11-20 06:29:23 -07:00
|
|
|
radeon_bo_unpin(robj);
|
|
|
|
radeon_bo_unreserve(robj);
|
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
/* evict vram memory */
|
2009-11-20 06:29:23 -07:00
|
|
|
radeon_bo_evict_vram(rdev);
|
2012-05-09 07:34:48 -06:00
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
/* wait for gpu to finish processing current batch */
|
2012-12-17 09:04:32 -07:00
|
|
|
for (i = 0; i < RADEON_NUM_RINGS; i++) {
|
2014-02-18 07:58:31 -07:00
|
|
|
r = radeon_fence_wait_empty(rdev, i);
|
2012-12-17 09:04:32 -07:00
|
|
|
if (r) {
|
|
|
|
/* delay GPU reset to resume */
|
2014-08-27 07:21:56 -06:00
|
|
|
radeon_fence_driver_force_completion(rdev, i);
|
2012-12-17 09:04:32 -07:00
|
|
|
}
|
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
|
2009-09-14 20:21:01 -06:00
|
|
|
radeon_save_bios_scratch_regs(rdev);
|
|
|
|
|
2009-10-01 10:02:11 -06:00
|
|
|
radeon_suspend(rdev);
|
2009-12-04 14:56:37 -07:00
|
|
|
radeon_hpd_fini(rdev);
|
2016-10-10 10:42:33 -06:00
|
|
|
/* evict remaining vram memory
|
|
|
|
* This second call to evict vram is to evict the gart page table
|
|
|
|
* using the CPU.
|
|
|
|
*/
|
2009-11-20 06:29:23 -07:00
|
|
|
radeon_bo_evict_vram(rdev);
|
2009-06-05 06:42:42 -06:00
|
|
|
|
2010-05-21 10:48:54 -06:00
|
|
|
radeon_agp_suspend(rdev);
|
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
pci_save_state(dev->pdev);
|
2016-06-07 15:43:04 -06:00
|
|
|
if (freeze && rdev->family >= CHIP_CEDAR) {
|
2016-03-18 09:58:39 -06:00
|
|
|
rdev->asic->asic_reset(rdev, true);
|
|
|
|
pci_restore_state(dev->pdev);
|
|
|
|
} else if (suspend) {
|
2009-06-05 06:42:42 -06:00
|
|
|
/* Shut down the device */
|
|
|
|
pci_disable_device(dev->pdev);
|
|
|
|
pci_set_power_state(dev->pdev, PCI_D3hot);
|
|
|
|
}
|
2012-09-16 22:40:31 -06:00
|
|
|
|
|
|
|
if (fbcon) {
|
|
|
|
console_lock();
|
|
|
|
radeon_fbdev_set_suspend(rdev, 1);
|
|
|
|
console_unlock();
|
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_resume_kms - initiate device resume
|
|
|
|
*
|
|
|
|
* @pdev: drm dev pointer
|
|
|
|
*
|
|
|
|
* Bring the hw back to operating state (all asics).
|
|
|
|
* Returns 0 for success or an error on failure.
|
|
|
|
* Called at driver resume.
|
|
|
|
*/
|
2012-09-16 22:40:31 -06:00
|
|
|
int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
|
2009-06-05 06:42:42 -06:00
|
|
|
{
|
2010-06-11 12:40:56 -06:00
|
|
|
struct drm_connector *connector;
|
2009-06-05 06:42:42 -06:00
|
|
|
struct radeon_device *rdev = dev->dev_private;
|
2015-07-07 01:27:29 -06:00
|
|
|
struct drm_crtc *crtc;
|
2012-07-07 04:47:58 -06:00
|
|
|
int r;
|
2009-06-05 06:42:42 -06:00
|
|
|
|
2016-09-19 10:20:18 -06:00
|
|
|
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
|
2010-01-31 22:38:10 -07:00
|
|
|
return 0;
|
|
|
|
|
2012-09-16 22:40:31 -06:00
|
|
|
if (fbcon) {
|
|
|
|
console_lock();
|
|
|
|
}
|
2012-09-12 20:02:30 -06:00
|
|
|
if (resume) {
|
|
|
|
pci_set_power_state(dev->pdev, PCI_D0);
|
|
|
|
pci_restore_state(dev->pdev);
|
|
|
|
if (pci_enable_device(dev->pdev)) {
|
2012-09-16 22:40:31 -06:00
|
|
|
if (fbcon)
|
|
|
|
console_unlock();
|
2012-09-12 20:02:30 -06:00
|
|
|
return -1;
|
|
|
|
}
|
2009-06-05 06:42:42 -06:00
|
|
|
}
|
2009-11-04 22:39:10 -07:00
|
|
|
/* resume AGP if in use */
|
|
|
|
radeon_agp_resume(rdev);
|
2009-10-01 10:02:11 -06:00
|
|
|
radeon_resume(rdev);
|
2012-07-07 04:47:58 -06:00
|
|
|
|
|
|
|
r = radeon_ib_ring_tests(rdev);
|
|
|
|
if (r)
|
|
|
|
DRM_ERROR("ib ring test failed (%d).\n", r);
|
|
|
|
|
2014-02-25 10:01:28 -07:00
|
|
|
if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
|
2013-12-18 12:07:14 -07:00
|
|
|
/* do dpm late init */
|
|
|
|
r = radeon_pm_late_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
rdev->pm.dpm_enabled = false;
|
|
|
|
DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
|
|
|
|
}
|
2014-02-25 10:01:28 -07:00
|
|
|
} else {
|
|
|
|
/* resume old pm late */
|
|
|
|
radeon_pm_resume(rdev);
|
2013-12-18 12:07:14 -07:00
|
|
|
}
|
|
|
|
|
2009-09-14 20:21:01 -06:00
|
|
|
radeon_restore_bios_scratch_regs(rdev);
|
2010-06-11 12:40:56 -06:00
|
|
|
|
2015-07-07 01:27:29 -06:00
|
|
|
/* pin cursors */
|
|
|
|
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
|
|
|
|
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
|
|
|
|
|
|
|
|
if (radeon_crtc->cursor_bo) {
|
|
|
|
struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
|
|
|
|
r = radeon_bo_reserve(robj, false);
|
|
|
|
if (r == 0) {
|
|
|
|
/* Only 27 bit offset for legacy cursor */
|
|
|
|
r = radeon_bo_pin_restricted(robj,
|
|
|
|
RADEON_GEM_DOMAIN_VRAM,
|
|
|
|
ASIC_IS_AVIVO(rdev) ?
|
|
|
|
0 : 1 << 27,
|
|
|
|
&radeon_crtc->cursor_addr);
|
|
|
|
if (r != 0)
|
|
|
|
DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
|
|
|
|
radeon_bo_unreserve(robj);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-01-20 12:56:39 -07:00
|
|
|
/* init dig PHYs, disp eng pll */
|
|
|
|
if (rdev->is_atom_bios) {
|
2011-05-22 11:20:36 -06:00
|
|
|
radeon_atom_encoder_init(rdev);
|
2012-03-20 15:18:04 -06:00
|
|
|
radeon_atom_disp_eng_pll_init(rdev);
|
2012-09-14 07:45:50 -06:00
|
|
|
/* turn on the BL */
|
|
|
|
if (rdev->mode_info.bl_encoder) {
|
|
|
|
u8 bl_level = radeon_get_backlight_level(rdev,
|
|
|
|
rdev->mode_info.bl_encoder);
|
|
|
|
radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
|
|
|
|
bl_level);
|
|
|
|
}
|
2012-01-20 12:56:39 -07:00
|
|
|
}
|
2009-12-04 14:56:37 -07:00
|
|
|
/* reset hpd state */
|
|
|
|
radeon_hpd_init(rdev);
|
2009-06-05 06:42:42 -06:00
|
|
|
/* blat the mode back in */
|
2014-03-26 22:09:19 -06:00
|
|
|
if (fbcon) {
|
|
|
|
drm_helper_resume_force_mode(dev);
|
|
|
|
/* turn on display hw */
|
2015-09-23 12:26:45 -06:00
|
|
|
drm_modeset_lock_all(dev);
|
2014-03-26 22:09:19 -06:00
|
|
|
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
|
|
|
|
drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
|
|
|
|
}
|
2015-09-23 12:26:45 -06:00
|
|
|
drm_modeset_unlock_all(dev);
|
2010-12-20 09:22:29 -07:00
|
|
|
}
|
2012-01-31 18:06:25 -07:00
|
|
|
|
|
|
|
drm_kms_helper_poll_enable(dev);
|
2014-05-30 08:41:23 -06:00
|
|
|
|
2014-05-30 10:40:15 -06:00
|
|
|
/* set the power state here in case we are a PX system or headless */
|
|
|
|
if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
|
|
|
|
radeon_pm_compute_clocks(rdev);
|
|
|
|
|
2014-05-30 08:41:23 -06:00
|
|
|
if (fbcon) {
|
|
|
|
radeon_fbdev_set_suspend(rdev, 0);
|
|
|
|
console_unlock();
|
|
|
|
}
|
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-07-17 12:02:33 -06:00
|
|
|
/**
|
|
|
|
* radeon_gpu_reset - reset the asic
|
|
|
|
*
|
|
|
|
* @rdev: radeon device pointer
|
|
|
|
*
|
|
|
|
* Attempt the reset the GPU if it has hung (all asics).
|
|
|
|
* Returns 0 for success or an error on failure.
|
|
|
|
*/
|
2010-03-09 07:45:12 -07:00
|
|
|
int radeon_gpu_reset(struct radeon_device *rdev)
|
|
|
|
{
|
2012-07-09 03:52:44 -06:00
|
|
|
unsigned ring_sizes[RADEON_NUM_RINGS];
|
|
|
|
uint32_t *ring_data[RADEON_NUM_RINGS];
|
|
|
|
|
|
|
|
bool saved = false;
|
|
|
|
|
|
|
|
int i, r;
|
2011-02-09 21:46:06 -07:00
|
|
|
int resched;
|
2010-03-09 07:45:12 -07:00
|
|
|
|
2012-07-02 10:45:19 -06:00
|
|
|
down_write(&rdev->exclusive_lock);
|
2013-10-29 13:14:47 -06:00
|
|
|
|
|
|
|
if (!rdev->needs_reset) {
|
|
|
|
up_write(&rdev->exclusive_lock);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-04-29 11:40:33 -06:00
|
|
|
atomic_inc(&rdev->gpu_reset_counter);
|
|
|
|
|
2010-03-09 07:45:12 -07:00
|
|
|
radeon_save_bios_scratch_regs(rdev);
|
2011-02-09 21:46:06 -07:00
|
|
|
/* block TTM */
|
|
|
|
resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
|
2010-03-09 07:45:12 -07:00
|
|
|
radeon_suspend(rdev);
|
2014-08-18 14:51:46 -06:00
|
|
|
radeon_hpd_fini(rdev);
|
2010-03-09 07:45:12 -07:00
|
|
|
|
2012-07-09 03:52:44 -06:00
|
|
|
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
|
|
|
|
ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
|
|
|
|
&ring_data[i]);
|
|
|
|
if (ring_sizes[i]) {
|
|
|
|
saved = true;
|
|
|
|
dev_info(rdev->dev, "Saved %d dwords of commands "
|
|
|
|
"on ring %d.\n", ring_sizes[i], i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-03-09 07:45:12 -07:00
|
|
|
r = radeon_asic_reset(rdev);
|
|
|
|
if (!r) {
|
2012-07-09 03:52:44 -06:00
|
|
|
dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
|
2010-03-09 07:45:12 -07:00
|
|
|
radeon_resume(rdev);
|
2012-07-09 03:52:44 -06:00
|
|
|
}
|
2012-07-07 04:47:58 -06:00
|
|
|
|
2012-07-09 03:52:44 -06:00
|
|
|
radeon_restore_bios_scratch_regs(rdev);
|
2012-07-07 04:47:58 -06:00
|
|
|
|
2014-08-27 14:45:18 -06:00
|
|
|
for (i = 0; i < RADEON_NUM_RINGS; ++i) {
|
|
|
|
if (!r && ring_data[i]) {
|
2012-07-09 03:52:44 -06:00
|
|
|
radeon_ring_restore(rdev, &rdev->ring[i],
|
|
|
|
ring_sizes[i], ring_data[i]);
|
2014-08-27 14:45:18 -06:00
|
|
|
} else {
|
2014-08-27 07:21:56 -06:00
|
|
|
radeon_fence_driver_force_completion(rdev, i);
|
2012-07-09 03:52:44 -06:00
|
|
|
kfree(ring_data[i]);
|
|
|
|
}
|
2010-03-09 07:45:12 -07:00
|
|
|
}
|
2011-11-10 10:57:26 -07:00
|
|
|
|
2014-08-18 09:57:28 -06:00
|
|
|
if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
|
|
|
|
/* do dpm late init */
|
|
|
|
r = radeon_pm_late_init(rdev);
|
|
|
|
if (r) {
|
|
|
|
rdev->pm.dpm_enabled = false;
|
|
|
|
DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* resume old pm late */
|
|
|
|
radeon_pm_resume(rdev);
|
|
|
|
}
|
|
|
|
|
2014-08-18 14:51:46 -06:00
|
|
|
/* init dig PHYs, disp eng pll */
|
|
|
|
if (rdev->is_atom_bios) {
|
|
|
|
radeon_atom_encoder_init(rdev);
|
|
|
|
radeon_atom_disp_eng_pll_init(rdev);
|
|
|
|
/* turn on the BL */
|
|
|
|
if (rdev->mode_info.bl_encoder) {
|
|
|
|
u8 bl_level = radeon_get_backlight_level(rdev,
|
|
|
|
rdev->mode_info.bl_encoder);
|
|
|
|
radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
|
|
|
|
bl_level);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* reset hpd state */
|
|
|
|
radeon_hpd_init(rdev);
|
|
|
|
|
2014-08-27 14:45:18 -06:00
|
|
|
ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
|
2014-08-27 07:22:01 -06:00
|
|
|
|
|
|
|
rdev->in_reset = true;
|
|
|
|
rdev->needs_reset = false;
|
|
|
|
|
2014-08-27 14:45:18 -06:00
|
|
|
downgrade_write(&rdev->exclusive_lock);
|
|
|
|
|
2012-12-14 14:20:46 -07:00
|
|
|
drm_helper_resume_force_mode(rdev->ddev);
|
|
|
|
|
2014-08-18 09:57:28 -06:00
|
|
|
/* set the power state here in case we are a PX system or headless */
|
|
|
|
if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
|
|
|
|
radeon_pm_compute_clocks(rdev);
|
|
|
|
|
2014-08-27 14:45:18 -06:00
|
|
|
if (!r) {
|
|
|
|
r = radeon_ib_ring_tests(rdev);
|
|
|
|
if (r && saved)
|
|
|
|
r = -EAGAIN;
|
|
|
|
} else {
|
2011-11-10 10:57:26 -07:00
|
|
|
/* bad news, how to tell it to userspace ? */
|
|
|
|
dev_info(rdev->dev, "GPU reset failed\n");
|
|
|
|
}
|
|
|
|
|
2014-08-27 14:45:18 -06:00
|
|
|
rdev->needs_reset = r == -EAGAIN;
|
|
|
|
rdev->in_reset = false;
|
|
|
|
|
|
|
|
up_read(&rdev->exclusive_lock);
|
2010-03-09 07:45:12 -07:00
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
2009-06-05 06:42:42 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Debugfs
|
|
|
|
*/
|
|
|
|
int radeon_debugfs_add_files(struct radeon_device *rdev,
|
|
|
|
struct drm_info_list *files,
|
|
|
|
unsigned nfiles)
|
|
|
|
{
|
|
|
|
unsigned i;
|
|
|
|
|
2011-10-24 06:54:54 -06:00
|
|
|
for (i = 0; i < rdev->debugfs_count; i++) {
|
|
|
|
if (rdev->debugfs[i].files == files) {
|
2009-06-05 06:42:42 -06:00
|
|
|
/* Already registered */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
2011-09-16 14:45:30 -06:00
|
|
|
|
2011-10-24 06:54:54 -06:00
|
|
|
i = rdev->debugfs_count + 1;
|
2011-09-16 14:45:30 -06:00
|
|
|
if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
|
|
|
|
DRM_ERROR("Reached maximum number of debugfs components.\n");
|
|
|
|
DRM_ERROR("Report so we increase "
|
2016-03-16 05:56:45 -06:00
|
|
|
"RADEON_DEBUGFS_MAX_COMPONENTS.\n");
|
2009-06-05 06:42:42 -06:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
2011-10-24 06:54:54 -06:00
|
|
|
rdev->debugfs[rdev->debugfs_count].files = files;
|
|
|
|
rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
|
|
|
|
rdev->debugfs_count = i;
|
2009-06-05 06:42:42 -06:00
|
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
|
|
drm_debugfs_create_files(files, nfiles,
|
|
|
|
rdev->ddev->primary->debugfs_root,
|
|
|
|
rdev->ddev->primary);
|
|
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
}
|