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Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
[MIPS] Make integer overflow exceptions in kernel mode fatal. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-14 14:04:54 -07:00
* Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
* Copyright (C) 1995, 1996 Paul M. Antoine
* Copyright (C) 1998 Ulf Carlsson
* Copyright (C) 1999 Silicon Graphics, Inc.
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
* Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
* Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
MIPS: kernel: traps: Whitespace clean up Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2013-12-04 09:20:08 -07:00
* Copyright (C) 2014, Imagination Technologies Ltd.
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
*/
MIPS: Respect the FCSR exception mask for `si_code' Respect the FCSR exception mask when interpreting the IEEE 754 exception condition to report with SIGFPE in `si_code', so as not to use one that has been masked where a different one set in parallel caused the FPE hardware exception to trigger. As per the IEEE Std 754 the Inexact exception can happen together with Overflow or Underflow. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9703/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:06 -06:00
#include <linux/bitops.h>
[MIPS] SMTC: Don't continue in set_vi_srs_handler on detected bad arguments. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-05-31 07:00:19 -06:00
#include <linux/bug.h>
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
#include <linux/compiler.h>
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
#include <linux/context_tracking.h>
MIPS: traps: Add CPU PM callback for trap configuration Implement a CPU power management callback for restoring trap related CPU configuration after CPU power up from a low power state. The following state is restored: - Status register - HWREna register - Exception vector configuration registers - Context/XContext register Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-03-04 03:20:43 -07:00
#include <linux/cpu_pm.h>
MIPS: kdump: Add support [ralf@linux-mips.org: Original patch by Maxim Uvarov <muvarov@gmail.com> with plenty of further shining, polishing, debugging and testing by me.] Signed-off-by: Maxim Uvarov <muvarov@gmail.com> Cc: linux-mips@linux-mips.org Cc: kexec@lists.infradead.org Cc: horms@verge.net.au Patchwork: https://patchwork.linux-mips.org/patch/1025/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-10-11 10:14:58 -06:00
#include <linux/kexec.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
#include <linux/init.h>
MIPS: Call oops_enter, oops_exit in die This allows pause_on_oops and mtdoops to work. Signed-off-by: Nathan Lynch <ntl@pobox.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2810/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-09-30 12:49:35 -06:00
#include <linux/kernel.h>
MIPS: Fix several implicit uses of export.h/module.h These will show up as a build failure once we clean up a misuse of module.h in the mips termios header. Uses export.h: (EXPORT_SYMBOL) arch/mips/cavium-octeon/setup.c arch/mips/pmc-sierra/yosemite/setup.c arch/mips/rb532/devices.c arch/mips/sni/setup.c Uses module.h: (symbol_get/put) arch/mips/alchemy/devboards/db1200.c Uses module.h: (print_modules) arch/mips/kernel/traps.c Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3448/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-02-28 17:24:46 -07:00
#include <linux/module.h>
MIPS: Migrate exception table users off module.h and onto extable.h These files were only including module.h for exception table related functions. We've now separated that content out into its own file "extable.h" so now move over to that and avoid all the extra header content in module.h that we don't really need to compile these files. In the case of traps.c we can't dump the module.h include since it is also used to provide "print_modules". Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13934/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-08-15 17:11:52 -06:00
#include <linux/extable.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
#include <linux/mm.h>
sched/headers: Move task->mm handling methods to <linux/sched/mm.h> Move the following task->mm helper APIs into a new header file, <linux/sched/mm.h>, to further reduce the size and complexity of <linux/sched.h>. Here are how the APIs are used in various kernel files: # mm_alloc(): arch/arm/mach-rpc/ecard.c fs/exec.c include/linux/sched/mm.h kernel/fork.c # __mmdrop(): arch/arc/include/asm/mmu_context.h include/linux/sched/mm.h kernel/fork.c # mmdrop(): arch/arm/mach-rpc/ecard.c arch/m68k/sun3/mmu_emu.c arch/x86/mm/tlb.c drivers/gpu/drm/amd/amdkfd/kfd_process.c drivers/gpu/drm/i915/i915_gem_userptr.c drivers/infiniband/hw/hfi1/file_ops.c drivers/vfio/vfio_iommu_spapr_tce.c fs/exec.c fs/proc/base.c fs/proc/task_mmu.c fs/proc/task_nommu.c fs/userfaultfd.c include/linux/mmu_notifier.h include/linux/sched/mm.h kernel/fork.c kernel/futex.c kernel/sched/core.c mm/khugepaged.c mm/ksm.c mm/mmu_context.c mm/mmu_notifier.c mm/oom_kill.c virt/kvm/kvm_main.c # mmdrop_async_fn(): include/linux/sched/mm.h # mmdrop_async(): include/linux/sched/mm.h kernel/fork.c # mmget_not_zero(): fs/userfaultfd.c include/linux/sched/mm.h mm/oom_kill.c # mmput(): arch/arc/include/asm/mmu_context.h arch/arc/kernel/troubleshoot.c arch/frv/mm/mmu-context.c arch/powerpc/platforms/cell/spufs/context.c arch/sparc/include/asm/mmu_context_32.h drivers/android/binder.c drivers/gpu/drm/etnaviv/etnaviv_gem.c drivers/gpu/drm/i915/i915_gem_userptr.c drivers/infiniband/core/umem.c drivers/infiniband/core/umem_odp.c drivers/infiniband/core/uverbs_main.c drivers/infiniband/hw/mlx4/main.c drivers/infiniband/hw/mlx5/main.c drivers/infiniband/hw/usnic/usnic_uiom.c drivers/iommu/amd_iommu_v2.c drivers/iommu/intel-svm.c drivers/lguest/lguest_user.c drivers/misc/cxl/fault.c drivers/misc/mic/scif/scif_rma.c drivers/oprofile/buffer_sync.c drivers/vfio/vfio_iommu_type1.c drivers/vhost/vhost.c drivers/xen/gntdev.c fs/exec.c fs/proc/array.c fs/proc/base.c fs/proc/task_mmu.c fs/proc/task_nommu.c fs/userfaultfd.c include/linux/sched/mm.h kernel/cpuset.c kernel/events/core.c kernel/events/uprobes.c kernel/exit.c kernel/fork.c kernel/ptrace.c kernel/sys.c kernel/trace/trace_output.c kernel/tsacct.c mm/memcontrol.c mm/memory.c mm/mempolicy.c mm/migrate.c mm/mmu_notifier.c mm/nommu.c mm/oom_kill.c mm/process_vm_access.c mm/rmap.c mm/swapfile.c mm/util.c virt/kvm/async_pf.c # mmput_async(): include/linux/sched/mm.h kernel/fork.c mm/oom_kill.c # get_task_mm(): arch/arc/kernel/troubleshoot.c arch/powerpc/platforms/cell/spufs/context.c drivers/android/binder.c drivers/gpu/drm/etnaviv/etnaviv_gem.c drivers/infiniband/core/umem.c drivers/infiniband/core/umem_odp.c drivers/infiniband/hw/mlx4/main.c drivers/infiniband/hw/mlx5/main.c drivers/infiniband/hw/usnic/usnic_uiom.c drivers/iommu/amd_iommu_v2.c drivers/iommu/intel-svm.c drivers/lguest/lguest_user.c drivers/misc/cxl/fault.c drivers/misc/mic/scif/scif_rma.c drivers/oprofile/buffer_sync.c drivers/vfio/vfio_iommu_type1.c drivers/vhost/vhost.c drivers/xen/gntdev.c fs/proc/array.c fs/proc/base.c fs/proc/task_mmu.c include/linux/sched/mm.h kernel/cpuset.c kernel/events/core.c kernel/exit.c kernel/fork.c kernel/ptrace.c kernel/sys.c kernel/trace/trace_output.c kernel/tsacct.c mm/memcontrol.c mm/memory.c mm/mempolicy.c mm/migrate.c mm/mmu_notifier.c mm/nommu.c mm/util.c # mm_access(): fs/proc/base.c include/linux/sched/mm.h kernel/fork.c mm/process_vm_access.c # mm_release(): arch/arc/include/asm/mmu_context.h fs/exec.c include/linux/sched/mm.h include/uapi/linux/sched.h kernel/exit.c kernel/fork.c Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mike Galbraith <efault@gmx.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-02-01 11:08:20 -07:00
#include <linux/sched/mm.h>
sched/headers: Prepare for new header dependencies before moving code to <linux/sched/debug.h> We are going to split <linux/sched/debug.h> out of <linux/sched.h>, which will have to be picked up from other headers and a couple of .c files. Create a trivial placeholder <linux/sched/debug.h> file that just maps to <linux/sched.h> to make this patch obviously correct and bisectable. Include the new header in the files that are going to need it. Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Cc: Mike Galbraith <efault@gmx.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-02-08 10:51:35 -07:00
#include <linux/sched/debug.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
#include <linux/smp.h>
#include <linux/spinlock.h>
#include <linux/kallsyms.h>
mips: switch to NO_BOOTMEM MIPS already has memblock support and all the memory is already registered with it. This patch replaces bootmem memory reservations with memblock ones and removes the bootmem initialization. Since memblock allocates memory in top-down mode, we ensure that memblock limit is max_low_pfn to prevent allocations from the high memory. To have the exceptions base in the lower 512M of the physical memory, its allocation in arch/mips/kernel/traps.c::traps_init() is using bottom-up mode. Signed-off-by: Mike Rapoport <rppt@linux.vnet.ibm.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20560/ Cc: Serge Semin <fancer.lancer@gmail.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: Huacai Chen <chenhc@lemote.com> Cc: Michal Hocko <mhocko@kernel.org> Cc: linux-mips@linux-mips.org Cc: linux-mm@kvack.org Cc: linux-kernel@vger.kernel.org
2018-09-10 03:23:18 -06:00
#include <linux/memblock.h>
[MIPS] Honour "panic_on_oops" sysctl. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-20 10:52:02 -06:00
#include <linux/interrupt.h>
[MIPS] Add support for MIPS CMP platform. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 10:14:26 -06:00
#include <linux/ptrace.h>
[MIPS] kgdb: add arch support for the kernel's kgdb core The new kgdb architecture specific handler registers and unregisters dynamically for exceptions depending on when you configure a kgdb I/O driver. Aside from initializing the exceptions earlier in the boot process, kgdb should have no impact on a device when it is compiled in so long as an I/O module is not configured for use. There have been quite a number of contributors during the existence of this patch (see arch/mips/kernel/kgdb.c). Most recently Jason re-wrote the mips kgdb logic to use the die notification handlers. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-07-29 14:58:53 -06:00
#include <linux/kgdb.h>
#include <linux/kdebug.h>
MIPS: kprobe: Add support. This patch is based on previous work by Sony and Himanshu Chauhan. I have done some cleanup and implemented JProbes and KRETPROBES. The KRETPROBES part is pretty much copied verbatim from powerpc. A possible future enhance might be to factor out the common code. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: Himanshu Chauhan <hschauhan@nulltrace.org> To: linux-mips@linux-mips.org To: ananth@in.ibm.com, To: anil.s.keshavamurthy@intel.com To: davem@davemloft.net To: masami.hiramatsu.pt@hitachi.com Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1525/ Patchwork: https://patchwork.linux-mips.org/patch/1530/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-03 12:22:20 -06:00
#include <linux/kprobes.h>
MIPS: Modularize COP2 handling Away with the daemons of ifdef; get ready for future COP2 users. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/708/
2009-11-23 18:24:58 -07:00
#include <linux/notifier.h>
mips,kgdb: kdb low level trap catch and stack trace The only way the debugger can handle a trap in inside rcu_lock, notify_die, or atomic_notifier_call_chain without a recursive fault is to have a low level "first opportunity handler" do_trap_or_bp() handler. Generally this will be something the vast majority of folks will not need, but for those who need it, it is added as a kernel .config option called KGDB_LOW_LEVEL_TRAP. Also added was a die notification for oops such that kdb can catch an oops for analysis. There appeared to be no obvious way to pass the struct pt_regs from the original exception back to the stack back tracer, so a special case was added to show_stack() for when kdb is active because you generally desire to generally look at the back trace of the original exception. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Acked-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-20 20:04:26 -06:00
#include <linux/kdb.h>
MIPS: Add missing #inclusions of <linux/irq.h> Add missing #inclusions of <linux/irq.h> to a whole bunch of files that should really include it. Note that this can replace #inclusions of <asm/irq.h>. This is required for the patch to sort out irqflags handling function naming to compile on MIPS. The problem is that these files require access to things like setup_irq() - which isn't available by #including <linux/interrupt.h> Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-07 07:08:54 -06:00
#include <linux/irq.h>
MIPS: add support for software performance events Software events are required as part of the measurable stuff by the Linux performance counter subsystem. Here is the list of events added by this patch: PERF_COUNT_SW_PAGE_FAULTS PERF_COUNT_SW_PAGE_FAULTS_MIN PERF_COUNT_SW_PAGE_FAULTS_MAJ PERF_COUNT_SW_ALIGNMENT_FAULTS PERF_COUNT_SW_EMULATION_FAULTS Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Acked-by: David Daney <ddaney@caviumnetworks.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Patchwork: https://patchwork.linux-mips.org/patch/1686/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-12 05:37:21 -06:00
#include <linux/perf_event.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: traps: tidy up ebase calculation Rather than #ifdef on CONFIG_KVM_GUEST & redefine the guest kseg0 base locally, make use of the CAC_BASE macro which has the correct value in both cases. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/11183/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-09-22 11:15:22 -06:00
#include <asm/addrspace.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
#include <asm/bootinfo.h>
#include <asm/branch.h>
#include <asm/break.h>
MIPS: Modularize COP2 handling Away with the daemons of ifdef; get ready for future COP2 users. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/708/
2009-11-23 18:24:58 -07:00
#include <asm/cop2.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
#include <asm/cpu.h>
MIPS: Optimize current_cpu_type() for better code. o Move current_cpu_type() to a separate header file o #ifdefing on supported CPU types lets modern GCC know that certain code in callers may be discarded ideally turning current_cpu_type() into a function returning a constant. o Use current_cpu_type() rather than direct access to struct cpuinfo_mips. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5833/
2013-09-17 02:25:47 -06:00
#include <asm/cpu-type.h>
Support the MIPS32 / MIPS64 DSP ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-05-31 05:49:19 -06:00
#include <asm/dsp.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
#include <asm/fpu.h>
MIPS: Switch FPU emulator trap to BREAK instruction. Arguably using the address error handler has always been ugly. But with processors that handle unaligned loads and stores in hardware the current mechanism ceases to work so switch it to a BREAK instruction and allocate break code 514 to the FPU emulator. Yoichi Yuasa provided a build fix for CONFIG_BUG=n. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
2008-10-28 11:38:42 -06:00
#include <asm/fpu_emulator.h>
MIPS: Idle: Consolidate all declarations in <asm/idle.h>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-21 08:59:19 -06:00
#include <asm/idle.h>
MIPS: Don't dump Hi & Lo regs on >= MIPSr6 MIPSr6 removed the Hi & Lo registers, so displaying their values on MIPSr6 systems is pointless. Avoid doing so. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21067/ Cc: linux-mips@linux-mips.org
2018-11-09 13:08:36 -07:00
#include <asm/isa-rev.h>
MIPS: CPS: Have asm/mips-cps.h include CM & CPC headers With Coherence Manager (CM) 3.5 information about the topology of the system, which has previously only been available through & accessed from the CM, is now also provided by the Cluster Power Controller (CPC). This includes a new CPC_CONFIG register mirroring GCR_CONFIG, and similarly a new CPC_Cx_CONFIG register mirroring GCR_Cx_CONFIG. In preparation for adjusting functions such as mips_cm_numcores(), which have previously only needed to access the CM, to also access the CPC this patch modifies the way we use the various CPS headers. Rather than having users include asm/mips-cm.h or asm/mips-cpc.h individually we instead have users include asm/mips-cps.h which in turn includes asm/mips-cm.h & asm/mips-cpc.h. This means that users will gain access to both CM & CPC registers by including one header, and most importantly it makes asm/mips-cps.h an ideal location for helper functions which need to access the various components of the CPS. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17015/ Patchwork: https://patchwork.linux-mips.org/patch/17217/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-12 20:49:41 -06:00
#include <asm/mips-cps.h>
MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6 MIPS R6 removed quite a few R2 instructions. However, there is plenty of <R6 userland code so we add an in-kernel emulator so we can still be able to execute all R2 userland out there. The emulator comes with a handy debugfs under /mips/ directory (r2-emul-stats) to provide some basic statistics of the instructions that are being emulated. Below are some statistics from booting a minimal buildroot image: Instruction Total BDslot ------------------------------ movs 236969 0 hilo 56686 0 muls 55279 0 divs 10941 0 dsps 0 0 bops 1 0 traps 0 0 fpus 0 0 loads 214981 17 stores 103364 0 llsc 56898 0 dsemul 150418 0 jr 370158 bltzl 43 bgezl 1594 bltzll 0 bgezll 0 bltzal 39 bgezal 39 beql 14503 bnel 138741 blezl 0 bgtzl 3988 Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-12-03 08:47:03 -07:00
#include <asm/mips-r2-to-r6-emul.h>
Virtual SMP support for the 34K. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-08-17 11:44:08 -06:00
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
#include <asm/module.h>
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:11 -07:00
#include <asm/msa.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include <asm/sections.h>
MIPS: traps: Correct the SIGTRAP debug ABI in `do_watch' and `do_trap_or_bp' Follow our own rules set in <asm/siginfo.h> for SIGTRAP signals issued from `do_watch' and `do_trap_or_bp' by setting the signal code to TRAP_HWBKPT and TRAP_BRKPT respectively, for Watch exceptions and for those Breakpoint exceptions whose originating BREAK instruction's code does not have a special meaning. Keep Trap exceptions unaffected as these are not debug events. No existing user software is expected to examine signal codes for these signals as SI_KERNEL has been always used here. This change makes the MIPS port more like other Linux ports, which reduces the complexity and provides for performance improvement in GDB. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Pedro Alves <palves@redhat.com> Cc: Luis Machado <lgustavo@codesourcery.com> Cc: linux-mips@linux-mips.org Cc: gdb@sourceware.org Patchwork: https://patchwork.linux-mips.org/patch/12758/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-03-03 18:44:28 -07:00
#include <asm/siginfo.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
#include <asm/tlbdebug.h>
#include <asm/traps.h>
Replace <asm/uaccess.h> with <linux/uaccess.h> globally This was entirely automated, using the script by Al: PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*<asm/uaccess.h>' sed -i -e "s!$PATT!#include <linux/uaccess.h>!" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h) to do the replacement at the end of the merge window. Requested-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-12-24 12:46:01 -07:00
#include <linux/uaccess.h>
MIPS: Watch exception handling for HARDWARE_WATCHPOINTS. Here we hook up the watch exception handler so that it sends SIGTRAP when the hardware watch registers are triggered. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-09-23 01:08:45 -06:00
#include <asm/watch.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
#include <asm/mmu_context.h>
#include <asm/types.h>
[MIPS] lockdep: Add STACKTRACE_SUPPORT and enable LOCKDEP_SUPPORT Implement stacktrace interface by using unwind_stack() and enable lockdep support in Kconfig. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-26 08:44:01 -06:00
#include <asm/stacktrace.h>
MIPS: Consistently declare TLB functions Since at least the beginning of the git era we've declared our TLB exception handling functions inconsistently. They're actually functions, but we declare them as arrays of u32 where each u32 is an encoded instruction. This has always been the case for arch/mips/mm/tlbex.c, and has also been true for arch/mips/kernel/traps.c since commit 86a1708a9d54 ("MIPS: Make tlb exception handler definitions and declarations match.") which aimed for consistency but did so by consistently making the our C code inconsistent with our assembly. This is all usually harmless, but when using GCC 7 or newer to build a kernel targeting microMIPS (ie. CONFIG_CPU_MICROMIPS=y) it becomes problematic. With microMIPS bit 0 of the program counter indicates the ISA mode. When bit 0 is zero instructions are decoded using the standard MIPS32 or MIPS64 ISA. When bit 0 is one instructions are decoded using microMIPS. This means that function pointers become odd - their least significant bit is one for microMIPS code. We work around this in cases where we need to access code using loads & stores with our msk_isa16_mode() macro which simply clears bit 0 of the value it is given: #define msk_isa16_mode(x) ((x) & ~0x1) For example we do this for our TLB load handler in build_r4000_tlb_load_handler(): u32 *p = (u32 *)msk_isa16_mode((ulong)handle_tlbl); We then write code to p, expecting it to be suitably aligned (our LEAF macro aligns functions on 4 byte boundaries, so (ulong)handle_tlbl will give a value one greater than a multiple of 4 - ie. the start of a function on a 4 byte boundary, with the ISA mode bit 0 set). This worked fine up to GCC 6, but GCC 7 & onwards is smart enough to presume that handle_tlbl which we declared as an array of u32s must be aligned sufficiently that bit 0 of its address will never be set, and as a result optimize out msk_isa16_mode(). This leads to p having an address with bit 0 set, and when we go on to attempt to store code at that address we take an address error exception due to the unaligned memory access. This leads to an exception prior to the kernel having configured its own exception handlers, so we jump to whatever handlers the bootloader configured. In the case of QEMU this results in a silent hang, since it has no useful general exception vector. Fix this by consistently declaring our TLB-related functions as functions. For handle_tlbl(), handle_tlbs() & handle_tlbm() we do this in asm/tlbex.h & we make use of the existing declaration of tlbmiss_handler_setup_pgd() in asm/mmu_context.h. Our TLB handler generation code in arch/mips/mm/tlbex.c is adjusted to deal with these definitions, in most cases simply by casting the function pointers to u32 pointers. This allows us to include asm/mmu_context.h in arch/mips/mm/tlbex.c to get the definitions of tlbmiss_handler_setup_pgd & pgd_current, removing some needless duplication. Consistently using msk_isa16_mode() on function pointers means we no longer need the tlbmiss_handler_setup_pgd_start symbol so that is removed entirely. Now that we're declaring our functions as functions GCC stops optimizing out msk_isa16_mode() & a microMIPS kernel built with either GCC 7.3.0 or 8.1.0 boots successfully. Signed-off-by: Paul Burton <paul.burton@mips.com>
2018-08-10 17:03:31 -06:00
#include <asm/tlbex.h>
MIPS: Deal with larger physical offsets AR7 has a larger physical offset than other MIPS based systems and therefore needs to setup its handlers beyond the usual KSEG0 range. When running the kernel in mapped mode this modification is also required. Remove function comment which is now incorrect. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Eugene Konev <ejka@imfi.kspu.ru> Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org To: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/889/ Patchwork: http://patchwork.linux-mips.org/patch/932/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-01-28 07:22:37 -07:00
#include <asm/uasm.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
[MIPS] Fix potential latency problem due to non-atomic cpu_wait. If an interrupt happened between checking of NEED_RESCHED and WAIT instruction, adjust EPC to restart from checking of NEED_RESCHED. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-11 10:05:18 -07:00
extern void check_wait(void);
extern asmlinkage void rollback_handle_int(void);
[MIPS] Rewrite all the assembler interrupt handlers to C. Saves like 1,600 lines of code, is way easier to debug, compilers frequently do a better job than the cut and paste type of handlers many boards had. And finally having all the stuff done in a single place also means alot of bug potencial for the MT ASE is gone. The only surviving handler in assembler is the DECstation one; I hope Maciej will rewrite it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-03 10:56:36 -06:00
extern asmlinkage void handle_int(void);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
extern asmlinkage void handle_adel(void);
extern asmlinkage void handle_ades(void);
extern asmlinkage void handle_ibe(void);
extern asmlinkage void handle_dbe(void);
extern asmlinkage void handle_sys(void);
extern asmlinkage void handle_bp(void);
extern asmlinkage void handle_ri(void);
MIPS: Check TLB before handle_ri_rdhwr() for Loongson-3 Loongson-3's micro TLB (ITLB) is not strictly a subset of JTLB. That means: when a JTLB entry is replaced by hardware, there may be an old valid entry exists in ITLB. So, a TLB miss exception may occur while handle_ri_rdhwr() is running because it try to access EPC's content. However, handle_ri_rdhwr() doesn't clear EXL, which makes a TLB Refill exception be treated as a TLB Invalid exception and tlbp may fail. In this case, if FTLB (which is usually set-associative instead of set- associative) is enabled, a tlbp failure will cause an invalid tlbwi, which will hang the whole system. This patch rename handle_ri_rdhwr_vivt to handle_ri_rdhwr_tlbp and use it for Loongson-3. It try to solve the same problem described as below, but more straightforwards. https://patchwork.linux-mips.org/patch/12591/ I think Loongson-2 has the same problem, but it has no FTLB, so we just keep it as is. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Rui Wang <wangr@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/15753/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-03-16 07:00:26 -06:00
extern asmlinkage void handle_ri_rdhwr_tlbp(void);
[MIPS] Fast path for rdhwr emulation for TLS Add special short path for emulationg RDHWR which is used to support TLS. Add an extra prologue for cpu_has_vtag_icache case. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-11 02:50:29 -06:00
extern asmlinkage void handle_ri_rdhwr(void);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
extern asmlinkage void handle_cpu(void);
extern asmlinkage void handle_ov(void);
extern asmlinkage void handle_tr(void);
MIPS: Dumb MSA FP exception handler This patch adds a simple handler for MSA FP exceptions which delivers a SIGFPE to the running task. In the future it should probably be extended to re-execute the instruction with the MSACSR.NX bit set in order to generate results for any elements which did not cause an exception before delivering the SIGFPE signal. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:12 -07:00
extern asmlinkage void handle_msa_fpe(void);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
extern asmlinkage void handle_fpe(void);
MIPS: Add support for FTLBs The Fixed Page Size TLB (FTLB) is a set-associative dual entry TLB. Its purpose is to reduce the number of TLB misses by increasing the effective TLB size and keep the implementation complexity to minimum levels. A supported core can have both VTLB and FTLB. Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6139/
2013-11-14 09:12:31 -07:00
extern asmlinkage void handle_ftlb(void);
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:11 -07:00
extern asmlinkage void handle_msa(void);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
extern asmlinkage void handle_mdmx(void);
extern asmlinkage void handle_watch(void);
Virtual SMP support for the 34K. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-08-17 11:44:08 -06:00
extern asmlinkage void handle_mt(void);
Support the MIPS32 / MIPS64 DSP ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-05-31 05:49:19 -06:00
extern asmlinkage void handle_dsp(void);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
extern asmlinkage void handle_mcheck(void);
extern asmlinkage void handle_reserved(void);
MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions Use the regular tlb_do_page_fault_0 (no write) handler to handle the RI and XI exceptions. Also skip the RI/XI validation check on TLB load handler since it's redundant when the CPU has unique RI/XI exceptions. Singed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7339/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-15 07:09:56 -06:00
extern void tlb_do_page_fault_0(void);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
void (*board_be_init)(void);
int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
void (*board_nmi_handler_setup)(void);
void (*board_ejtag_handler_setup)(void);
void (*board_bind_eic_interrupt)(int irq, int regset);
MIPS: Add board_ebase_setup() Some systems need to relocate the MIPS exception vector base during trap initialization. Add a hook to make this possible. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2959/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-11-15 18:25:45 -07:00
void (*board_ebase_setup)(void);
MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code commit 3747069b25e419f6b51395f48127e9812abc3596 upstream. The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. Here, we remove all the MIPS __cpuinit from C code and __CPUINIT from asm files. MIPS is interesting in this respect, because there are also uasm users hiding behind their own renamed versions of the __cpuinit macros. [1] https://lkml.org/lkml/2013/5/20/589 [ralf@linux-mips.org: Folded in Paul's followup fix.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5494/ Patchwork: https://patchwork.linux-mips.org/patch/5495/ Patchwork: https://patchwork.linux-mips.org/patch/5509/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-18 07:38:59 -06:00
void(*board_cache_error_setup)(void);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
[MIPS] Improve unwind_stack() This patch allows unwind_stack() to return ra for leaf function. But it tries to detects cases where get_frame_info() wrongly consider nested function as a leaf one. It also pass 'unsinged long *sp' instead of 'unsigned long **sp' as second parameter. The code looks cleaner. Signed-off-by: Franck Bui-Huu <vagabon.xyz@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-08-03 01:29:21 -06:00
static void show_raw_backtrace(unsigned long reg29)
[MIPS] Rearrange show_stack, show_trace Print call-trace in show_stack() (like on other archs). Also make show_trace() static and simplify its argument list. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-25 08:51:36 -06:00
{
[MIPS] Add support for MIPS CMP platform. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 10:14:26 -06:00
unsigned long *sp = (unsigned long *)(reg29 & ~3);
[MIPS] Rearrange show_stack, show_trace Print call-trace in show_stack() (like on other archs). Also make show_trace() static and simplify its argument list. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-25 08:51:36 -06:00
unsigned long addr;
printk("Call Trace:");
#ifdef CONFIG_KALLSYMS
printk("\n");
#endif
[MIPS] Fix check for valid stack pointer during backtrace The newly added check for valid stack pointer address breaks at least for 64bit kernels. Use __get_user() for accessing stack content to avoid crashes, when doing the backtrace. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-05-12 09:58:48 -06:00
while (!kstack_end(sp)) {
unsigned long __user *p =
(unsigned long __user *)(unsigned long)sp++;
if (__get_user(addr, p)) {
printk(" (Bad stack address)");
break;
[MIPS] Add support for MIPS CMP platform. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 10:14:26 -06:00
}
[MIPS] Fix check for valid stack pointer during backtrace The newly added check for valid stack pointer address breaks at least for 64bit kernels. Use __get_user() for accessing stack content to avoid crashes, when doing the backtrace. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-05-12 09:58:48 -06:00
if (__kernel_text_address(addr))
print_ip_sym(addr);
[MIPS] Rearrange show_stack, show_trace Print call-trace in show_stack() (like on other archs). Also make show_trace() static and simplify its argument list. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-25 08:51:36 -06:00
}
[MIPS] Fix check for valid stack pointer during backtrace The newly added check for valid stack pointer address breaks at least for 64bit kernels. Use __get_user() for accessing stack content to avoid crashes, when doing the backtrace. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-05-12 09:58:48 -06:00
printk("\n");
[MIPS] Rearrange show_stack, show_trace Print call-trace in show_stack() (like on other archs). Also make show_trace() static and simplify its argument list. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-25 08:51:36 -06:00
}
[MIPS] dump_stack() based on prologue code analysis Instead of dump all possible address in the stack, unwind the stack frame based on prologue code analysis, as like as get_wchan() does. While the code analysis might fail for some reason, there is a new kernel option "raw_show_trace" to disable this feature. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-29 08:27:20 -06:00
#ifdef CONFIG_KALLSYMS
[MIPS] lockdep: Add STACKTRACE_SUPPORT and enable LOCKDEP_SUPPORT Implement stacktrace interface by using unwind_stack() and enable lockdep support in Kconfig. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-26 08:44:01 -06:00
int raw_show_trace;
[MIPS] dump_stack() based on prologue code analysis Instead of dump all possible address in the stack, unwind the stack frame based on prologue code analysis, as like as get_wchan() does. While the code analysis might fail for some reason, there is a new kernel option "raw_show_trace" to disable this feature. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-29 08:27:20 -06:00
static int __init set_raw_show_trace(char *str)
{
raw_show_trace = 1;
return 1;
}
__setup("raw_show_trace", set_raw_show_trace);
[MIPS] lockdep: Add STACKTRACE_SUPPORT and enable LOCKDEP_SUPPORT Implement stacktrace interface by using unwind_stack() and enable lockdep support in Kconfig. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-26 08:44:01 -06:00
#endif
[MIPS] Improve unwind_stack() This patch allows unwind_stack() to return ra for leaf function. But it tries to detects cases where get_frame_info() wrongly consider nested function as a leaf one. It also pass 'unsinged long *sp' instead of 'unsigned long **sp' as second parameter. The code looks cleaner. Signed-off-by: Franck Bui-Huu <vagabon.xyz@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-08-03 01:29:21 -06:00
[MIPS] IP22: Fix warning. CC arch/mips/sgi-ip22/ip22-berr.o arch/mips/sgi-ip22/ip22-berr.c: In function 'ip22_be_interrupt': arch/mips/sgi-ip22/ip22-berr.c:100: warning: passing argument 2 of 'die_if_kernel' discards qualifiers from pointer target type Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-14 16:27:21 -06:00
static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
[MIPS] dump_stack() based on prologue code analysis Instead of dump all possible address in the stack, unwind the stack frame based on prologue code analysis, as like as get_wchan() does. While the code analysis might fail for some reason, there is a new kernel option "raw_show_trace" to disable this feature. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-29 08:27:20 -06:00
{
[MIPS] Improve unwind_stack() This patch allows unwind_stack() to return ra for leaf function. But it tries to detects cases where get_frame_info() wrongly consider nested function as a leaf one. It also pass 'unsinged long *sp' instead of 'unsigned long **sp' as second parameter. The code looks cleaner. Signed-off-by: Franck Bui-Huu <vagabon.xyz@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-08-03 01:29:21 -06:00
unsigned long sp = regs->regs[29];
unsigned long ra = regs->regs[31];
[MIPS] dump_stack() based on prologue code analysis Instead of dump all possible address in the stack, unwind the stack frame based on prologue code analysis, as like as get_wchan() does. While the code analysis might fail for some reason, there is a new kernel option "raw_show_trace" to disable this feature. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-29 08:27:20 -06:00
unsigned long pc = regs->cp0_epc;
MIPS: Fix Magic SysRq L kernel crash. show_backtrace() was passed a NULL pointer which caused paging request fail. Set to current task as other architectures (ARM, etc) do when passed a NULL task pointer. Signed-off-by: Vincent Wen <vincentwenlinux@gmail.com> Cc: linux-mips@linux-mips.org Cc: cernekee@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/3524/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-07-19 01:11:16 -06:00
if (!task)
task = current;
MIPS: Avoid using unwind_stack() with usermode When showing backtraces in response to traps, for example crashes and address errors (usually unaligned accesses) when they are set in debugfs to be reported, unwind_stack will be used if the PC was in the kernel text address range. However since EVA it is possible for user and kernel address ranges to overlap, and even without EVA userland can still trigger an address error by jumping to a KSeg0 address. Adjust the check to also ensure that it was running in kernel mode. I don't believe any harm can come of this problem, since unwind_stack() is sufficiently defensive, however it is only meant for unwinding kernel code, so to be correct it should use the raw backtracing instead. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.15+ Patchwork: https://patchwork.linux-mips.org/patch/11701/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> (cherry picked from commit d2941a975ac745c607dfb590e92bb30bc352dad9)
2015-12-04 15:25:02 -07:00
if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
[MIPS] Miscellaneous cleanup in prologue analysis code We usually use backtrace term for dumping a call tree during debug. Therefore this patch renames show_frametrace() into show_backtrace() and show_trace() into show_raw_backtrace(). It also uses the new function print_ip_sym(). Signed-off-by: Franck Bui-Huu <vagabon.xyz@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-08-03 01:29:17 -06:00
show_raw_backtrace(sp);
[MIPS] dump_stack() based on prologue code analysis Instead of dump all possible address in the stack, unwind the stack frame based on prologue code analysis, as like as get_wchan() does. While the code analysis might fail for some reason, there is a new kernel option "raw_show_trace" to disable this feature. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-29 08:27:20 -06:00
return;
}
printk("Call Trace:\n");
[MIPS] Improve unwind_stack() This patch allows unwind_stack() to return ra for leaf function. But it tries to detects cases where get_frame_info() wrongly consider nested function as a leaf one. It also pass 'unsinged long *sp' instead of 'unsigned long **sp' as second parameter. The code looks cleaner. Signed-off-by: Franck Bui-Huu <vagabon.xyz@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-08-03 01:29:21 -06:00
do {
[MIPS] Miscellaneous cleanup in prologue analysis code We usually use backtrace term for dumping a call tree during debug. Therefore this patch renames show_frametrace() into show_backtrace() and show_trace() into show_raw_backtrace(). It also uses the new function print_ip_sym(). Signed-off-by: Franck Bui-Huu <vagabon.xyz@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-08-03 01:29:17 -06:00
print_ip_sym(pc);
[MIPS] Make unwind_stack() can dig into interrupted context If the PC was ret_from_irq or ret_from_exception, there will be no more normal stackframe. Instead of stopping the unwinding, use PC and RA saved by an exception handler to continue unwinding into the interrupted context. This also simplifies the CONFIG_STACKTRACE code. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-29 03:02:51 -06:00
pc = unwind_stack(task, &sp, pc, &ra);
[MIPS] Improve unwind_stack() This patch allows unwind_stack() to return ra for leaf function. But it tries to detects cases where get_frame_info() wrongly consider nested function as a leaf one. It also pass 'unsinged long *sp' instead of 'unsigned long **sp' as second parameter. The code looks cleaner. Signed-off-by: Franck Bui-Huu <vagabon.xyz@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-08-03 01:29:21 -06:00
} while (pc);
MIPS: traps: Fix output of show_backtrace Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from show_backtrace on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected output. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14429/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:20 -06:00
pr_cont("\n");
[MIPS] dump_stack() based on prologue code analysis Instead of dump all possible address in the stack, unwind the stack frame based on prologue code analysis, as like as get_wchan() does. While the code analysis might fail for some reason, there is a new kernel option "raw_show_trace" to disable this feature. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-29 08:27:20 -06:00
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
* This routine abuses get_user()/put_user() to reference pointers
* with at least a bit of error checking ...
*/
[MIPS] IP22: Fix warning. CC arch/mips/sgi-ip22/ip22-berr.o arch/mips/sgi-ip22/ip22-berr.c: In function 'ip22_be_interrupt': arch/mips/sgi-ip22/ip22-berr.c:100: warning: passing argument 2 of 'die_if_kernel' discards qualifiers from pointer target type Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-14 16:27:21 -06:00
static void show_stacktrace(struct task_struct *task,
const struct pt_regs *regs)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
{
const int field = 2 * sizeof(unsigned long);
long stackdata;
int i;
[MIPS] Add some __user tags Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-13 08:02:42 -06:00
unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
printk("Stack :");
i = 0;
while ((unsigned long) sp & (PAGE_SIZE - 1)) {
MIPS: traps: Fix output of show_stacktrace Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from show_stacktrace on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected output. Also start a new line with printk such that the presence of timing information does not interfere with output. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14430/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:21 -06:00
if (i && ((i % (64 / field)) == 0)) {
pr_cont("\n");
printk(" ");
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
if (i > 39) {
MIPS: traps: Fix output of show_stacktrace Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from show_stacktrace on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected output. Also start a new line with printk such that the presence of timing information does not interfere with output. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14430/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:21 -06:00
pr_cont(" ...");
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
break;
}
if (__get_user(stackdata, sp++)) {
MIPS: traps: Fix output of show_stacktrace Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from show_stacktrace on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected output. Also start a new line with printk such that the presence of timing information does not interfere with output. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14430/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:21 -06:00
pr_cont(" (Bad stack address)");
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
break;
}
MIPS: traps: Fix output of show_stacktrace Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from show_stacktrace on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected output. Also start a new line with printk such that the presence of timing information does not interfere with output. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14430/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:21 -06:00
pr_cont(" %0*lx", field, stackdata);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
i++;
}
MIPS: traps: Fix output of show_stacktrace Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from show_stacktrace on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected output. Also start a new line with printk such that the presence of timing information does not interfere with output. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14430/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:21 -06:00
pr_cont("\n");
[MIPS] Miscellaneous cleanup in prologue analysis code We usually use backtrace term for dumping a call tree during debug. Therefore this patch renames show_frametrace() into show_backtrace() and show_trace() into show_raw_backtrace(). It also uses the new function print_ip_sym(). Signed-off-by: Franck Bui-Huu <vagabon.xyz@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-08-03 01:29:17 -06:00
show_backtrace(task, regs);
[MIPS] dump_stack() based on prologue code analysis Instead of dump all possible address in the stack, unwind the stack frame based on prologue code analysis, as like as get_wchan() does. While the code analysis might fail for some reason, there is a new kernel option "raw_show_trace" to disable this feature. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-29 08:27:20 -06:00
}
void show_stack(struct task_struct *task, unsigned long *sp)
{
struct pt_regs regs;
MIPS: show_stack: Fix stack trace with EVA The show_stack() function deals exclusively with kernel contexts, but if it gets called in user context with EVA enabled, show_stacktrace() will attempt to access the stack using EVA accesses, which will either read other user mapped data, or more likely cause an exception which will be handled by __get_user(). This is easily reproduced using SysRq t to show all task states, which results in the following stack dump output: Stack : (Bad stack address) Fix by setting the current user access mode to kernel around the call to show_stacktrace(). This causes __get_user() to use normal loads to read the kernel stack. Now we get the correct output, like this: Stack : 00000000 80168960 00000000 004a0000 00000000 00000000 8060016c 1f3abd0c 1f172cd8 8056f09c 7ff1e450 8014fc3c 00000001 806dd0b0 0000001d 00000002 1f17c6a0 1f17c804 1f17c6a0 8066f6e0 00000000 0000000a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0110e800 1f3abd6c 1f17c6a0 ... Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.15+ Patchwork: https://patchwork.linux-mips.org/patch/10778/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-27 06:50:22 -06:00
mm_segment_t old_fs = get_fs();
MIPS: Avoid accidental raw backtrace Since commit 81a76d7119f6 ("MIPS: Avoid using unwind_stack() with usermode") show_backtrace() invokes the raw backtracer when cp0_status & ST0_KSU indicates user mode to fix issues on EVA kernels where user and kernel address spaces overlap. However this is used by show_stack() which creates its own pt_regs on the stack and leaves cp0_status uninitialised in most of the code paths. This results in the non deterministic use of the raw back tracer depending on the previous stack content. show_stack() deals exclusively with kernel mode stacks anyway, so explicitly initialise regs.cp0_status to KSU_KERNEL (i.e. 0) to ensure we get a useful backtrace. Fixes: 81a76d7119f6 ("MIPS: Avoid using unwind_stack() with usermode") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.15+ Patchwork: https://patchwork.linux-mips.org/patch/16656/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-06-29 08:05:04 -06:00
regs.cp0_status = KSU_KERNEL;
[MIPS] dump_stack() based on prologue code analysis Instead of dump all possible address in the stack, unwind the stack frame based on prologue code analysis, as like as get_wchan() does. While the code analysis might fail for some reason, there is a new kernel option "raw_show_trace" to disable this feature. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-29 08:27:20 -06:00
if (sp) {
regs.regs[29] = (unsigned long)sp;
regs.regs[31] = 0;
regs.cp0_epc = 0;
} else {
if (task && task != current) {
regs.regs[29] = task->thread.reg29;
regs.regs[31] = 0;
regs.cp0_epc = task->thread.reg31;
mips,kgdb: kdb low level trap catch and stack trace The only way the debugger can handle a trap in inside rcu_lock, notify_die, or atomic_notifier_call_chain without a recursive fault is to have a low level "first opportunity handler" do_trap_or_bp() handler. Generally this will be something the vast majority of folks will not need, but for those who need it, it is added as a kernel .config option called KGDB_LOW_LEVEL_TRAP. Also added was a die notification for oops such that kdb can catch an oops for analysis. There appeared to be no obvious way to pass the struct pt_regs from the original exception back to the stack back tracer, so a special case was added to show_stack() for when kdb is active because you generally desire to generally look at the back trace of the original exception. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Acked-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-20 20:04:26 -06:00
#ifdef CONFIG_KGDB_KDB
} else if (atomic_read(&kgdb_active) != -1 &&
kdb_current_regs) {
memcpy(&regs, kdb_current_regs, sizeof(regs));
#endif /* CONFIG_KGDB_KDB */
[MIPS] dump_stack() based on prologue code analysis Instead of dump all possible address in the stack, unwind the stack frame based on prologue code analysis, as like as get_wchan() does. While the code analysis might fail for some reason, there is a new kernel option "raw_show_trace" to disable this feature. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-29 08:27:20 -06:00
} else {
prepare_frametrace(&regs);
}
}
MIPS: show_stack: Fix stack trace with EVA The show_stack() function deals exclusively with kernel contexts, but if it gets called in user context with EVA enabled, show_stacktrace() will attempt to access the stack using EVA accesses, which will either read other user mapped data, or more likely cause an exception which will be handled by __get_user(). This is easily reproduced using SysRq t to show all task states, which results in the following stack dump output: Stack : (Bad stack address) Fix by setting the current user access mode to kernel around the call to show_stacktrace(). This causes __get_user() to use normal loads to read the kernel stack. Now we get the correct output, like this: Stack : 00000000 80168960 00000000 004a0000 00000000 00000000 8060016c 1f3abd0c 1f172cd8 8056f09c 7ff1e450 8014fc3c 00000001 806dd0b0 0000001d 00000002 1f17c6a0 1f17c804 1f17c6a0 8066f6e0 00000000 0000000a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0110e800 1f3abd6c 1f17c6a0 ... Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.15+ Patchwork: https://patchwork.linux-mips.org/patch/10778/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-27 06:50:22 -06:00
/*
* show_stack() deals exclusively with kernel mode, so be sure to access
* the stack in the kernel (not user) address space.
*/
set_fs(KERNEL_DS);
[MIPS] dump_stack() based on prologue code analysis Instead of dump all possible address in the stack, unwind the stack frame based on prologue code analysis, as like as get_wchan() does. While the code analysis might fail for some reason, there is a new kernel option "raw_show_trace" to disable this feature. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-29 08:27:20 -06:00
show_stacktrace(task, &regs);
MIPS: show_stack: Fix stack trace with EVA The show_stack() function deals exclusively with kernel contexts, but if it gets called in user context with EVA enabled, show_stacktrace() will attempt to access the stack using EVA accesses, which will either read other user mapped data, or more likely cause an exception which will be handled by __get_user(). This is easily reproduced using SysRq t to show all task states, which results in the following stack dump output: Stack : (Bad stack address) Fix by setting the current user access mode to kernel around the call to show_stacktrace(). This causes __get_user() to use normal loads to read the kernel stack. Now we get the correct output, like this: Stack : 00000000 80168960 00000000 004a0000 00000000 00000000 8060016c 1f3abd0c 1f172cd8 8056f09c 7ff1e450 8014fc3c 00000001 806dd0b0 0000001d 00000002 1f17c6a0 1f17c804 1f17c6a0 8066f6e0 00000000 0000000a 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 0110e800 1f3abd6c 1f17c6a0 ... Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.15+ Patchwork: https://patchwork.linux-mips.org/patch/10778/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-27 06:50:22 -06:00
set_fs(old_fs);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
[MIPS] Make show_code static and add __user tag Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-13 08:51:46 -06:00
static void show_code(unsigned int __user *pc)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
{
long i;
[MIPS] Add support for MIPS CMP platform. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 10:14:26 -06:00
unsigned short __user *pc16 = NULL;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: traps: Fix output of show_code Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from show_code on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected output. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:22 -06:00
printk("Code:");
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
[MIPS] Add support for MIPS CMP platform. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 10:14:26 -06:00
if ((unsigned long)pc & 1)
pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
for(i = -3 ; i < 6 ; i++) {
unsigned int insn;
[MIPS] Add support for MIPS CMP platform. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 10:14:26 -06:00
if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
MIPS: traps: Fix output of show_code Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from show_code on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected output. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:22 -06:00
pr_cont(" (Bad address in epc)\n");
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
break;
}
MIPS: traps: Fix output of show_code Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from show_code on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected output. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:22 -06:00
pr_cont("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
MIPS: traps: Fix output of show_code Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from show_code on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected output. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:22 -06:00
pr_cont("\n");
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
[MIPS] IP22: Fix warning. CC arch/mips/sgi-ip22/ip22-berr.o arch/mips/sgi-ip22/ip22-berr.c: In function 'ip22_be_interrupt': arch/mips/sgi-ip22/ip22-berr.c:100: warning: passing argument 2 of 'die_if_kernel' discards qualifiers from pointer target type Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-14 16:27:21 -06:00
static void __show_regs(const struct pt_regs *regs)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
{
const int field = 2 * sizeof(unsigned long);
unsigned int cause = regs->cp0_cause;
MIPS: traps: print Exception Code in __show_regs() Print Exception Code when printing the Cause register. Signed-off-by: Petri Gynther <pgynther@google.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9998/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-05-08 16:10:10 -06:00
unsigned int exccode;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
int i;
dump_stack: unify debug information printed by show_regs() show_regs() is inherently arch-dependent but it does make sense to print generic debug information and some archs already do albeit in slightly different forms. This patch introduces a generic function to print debug information from show_regs() so that different archs print out the same information and it's much easier to modify what's printed. show_regs_print_info() prints out the same debug info as dump_stack() does plus task and thread_info pointers. * Archs which didn't print debug info now do. alpha, arc, blackfin, c6x, cris, frv, h8300, hexagon, ia64, m32r, metag, microblaze, mn10300, openrisc, parisc, score, sh64, sparc, um, xtensa * Already prints debug info. Replaced with show_regs_print_info(). The printed information is superset of what used to be there. arm, arm64, avr32, mips, powerpc, sh32, tile, unicore32, x86 * s390 is special in that it used to print arch-specific information along with generic debug info. Heiko and Martin think that the arch-specific extra isn't worth keeping s390 specfic implementation. Converted to use the generic version. Note that now all archs print the debug info before actual register dumps. An example BUG() dump follows. kernel BUG at /work/os/work/kernel/workqueue.c:4841! invalid opcode: 0000 [#1] PREEMPT SMP DEBUG_PAGEALLOC Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.9.0-rc1-work+ #7 Hardware name: empty empty/S3992, BIOS 080011 10/26/2007 task: ffff88007c85e040 ti: ffff88007c860000 task.ti: ffff88007c860000 RIP: 0010:[<ffffffff8234a07e>] [<ffffffff8234a07e>] init_workqueues+0x4/0x6 RSP: 0000:ffff88007c861ec8 EFLAGS: 00010246 RAX: ffff88007c861fd8 RBX: ffffffff824466a8 RCX: 0000000000000001 RDX: 0000000000000046 RSI: 0000000000000001 RDI: ffffffff8234a07a RBP: ffff88007c861ec8 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000001 R11: 0000000000000000 R12: ffffffff8234a07a R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000000 FS: 0000000000000000(0000) GS:ffff88007dc00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 000000008005003b CR2: ffff88015f7ff000 CR3: 00000000021f1000 CR4: 00000000000007f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 Stack: ffff88007c861ef8 ffffffff81000312 ffffffff824466a8 ffff88007c85e650 0000000000000003 0000000000000000 ffff88007c861f38 ffffffff82335e5d ffff88007c862080 ffffffff8223d8c0 ffff88007c862080 ffffffff81c47760 Call Trace: [<ffffffff81000312>] do_one_initcall+0x122/0x170 [<ffffffff82335e5d>] kernel_init_freeable+0x9b/0x1c8 [<ffffffff81c47760>] ? rest_init+0x140/0x140 [<ffffffff81c4776e>] kernel_init+0xe/0xf0 [<ffffffff81c6be9c>] ret_from_fork+0x7c/0xb0 [<ffffffff81c47760>] ? rest_init+0x140/0x140 ... v2: Typo fix in x86-32. v3: CPU number dropped from show_regs_print_info() as dump_stack_print_info() has been updated to print it. s390 specific implementation dropped as requested by s390 maintainers. Signed-off-by: Tejun Heo <tj@kernel.org> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Fengguang Wu <fengguang.wu@intel.com> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Sam Ravnborg <sam@ravnborg.org> Acked-by: Chris Metcalf <cmetcalf@tilera.com> [tile bits] Acked-by: Richard Kuo <rkuo@codeaurora.org> [hexagon bits] Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-04-30 16:27:17 -06:00
show_regs_print_info(KERN_DEFAULT);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
* Saved main processor registers
*/
for (i = 0; i < 32; ) {
if ((i % 4) == 0)
printk("$%2d :", i);
if (i == 0)
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont(" %0*lx", field, 0UL);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
else if (i == 26 || i == 27)
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont(" %*s", field, "");
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
else
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont(" %0*lx", field, regs->regs[i]);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
i++;
if ((i % 4) == 0)
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("\n");
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
[MIPS] Add basic SMARTMIPS ASE support This patch adds trivial support for SMARTMIPS extension. This extension is currently implemented by 4KS[CD] CPUs. Basically it saves/restores ACX register, which is part of the SMARTMIPS ASE, when needed. This patch does *not* add any support for Smartmips MMU features. Futhermore this patch does not add explicit support for 4KS[CD] CPUs since they are respectively mips32 and mips32r2 compliant. So with the current processor configuration, a platform that has such CPUs needs to select both configs: CPU_HAS_SMARTMIPS SYS_HAS_CPU_MIPS32_R[12] This is due to the processor configuration which is mixing up all the architecture variants and the processor types. The drawback of this, is that we currently pass '-march=mips32' option to gcc when building a kernel instead of '-march=4ksc' for 4KSC case. This can lead to a kernel image a little bit bigger than required. Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-02 09:41:47 -07:00
#ifdef CONFIG_CPU_HAS_SMARTMIPS
printk("Acx : %0*lx\n", field, regs->acx);
#endif
MIPS: Don't dump Hi & Lo regs on >= MIPSr6 MIPSr6 removed the Hi & Lo registers, so displaying their values on MIPSr6 systems is pointless. Avoid doing so. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21067/ Cc: linux-mips@linux-mips.org
2018-11-09 13:08:36 -07:00
if (MIPS_ISA_REV < 6) {
printk("Hi : %0*lx\n", field, regs->hi);
printk("Lo : %0*lx\n", field, regs->lo);
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
* Saved cp0 registers
*/
[MIPS] Replace use of print_symbol with new %sP pointer format. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-07-15 11:44:33 -06:00
printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
(void *) regs->cp0_epc);
printk("ra : %0*lx %pS\n", field, regs->regs[31],
(void *) regs->regs[31]);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: Whitespace cleanup. Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-01-22 04:59:30 -07:00
printk("Status: %08x ", (uint32_t) regs->cp0_status);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: Get rid of MIPS I flag and test macros. MIPS I is the ancestor of all MIPS ISA and architecture variants. Anything ever build in the MIPS empire is either MIPS I or at least contains MIPS I. If it's running Linux, that is. So there is little point in having cpu_has_mips_1 because it will always evaluate as true - though usually only at runtime. Thus there is no point in having the MIPS_CPU_ISA_I ISA flag, so get rid of it. Little complication: traps.c was using a test for a pure MIPS I ISA as a test for an R3000-style cp0. To deal with that, use a check for cpu_has_3kex or cpu_has_4kex instead. cpu_has_3kex is a new macro. At the moment its default implementation is !cpu_has_4kex but this may eventually change if Linux is ever going to support the oddball MIPS processors R6000 and R8000 so users of either of these macros should not make any assumptions. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5551/
2013-06-26 09:06:34 -06:00
if (cpu_has_3kex) {
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
if (regs->cp0_status & ST0_KUO)
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("KUo ");
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
if (regs->cp0_status & ST0_IEO)
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("IEo ");
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
if (regs->cp0_status & ST0_KUP)
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("KUp ");
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
if (regs->cp0_status & ST0_IEP)
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("IEp ");
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
if (regs->cp0_status & ST0_KUC)
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("KUc ");
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
if (regs->cp0_status & ST0_IEC)
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("IEc ");
MIPS: Get rid of MIPS I flag and test macros. MIPS I is the ancestor of all MIPS ISA and architecture variants. Anything ever build in the MIPS empire is either MIPS I or at least contains MIPS I. If it's running Linux, that is. So there is little point in having cpu_has_mips_1 because it will always evaluate as true - though usually only at runtime. Thus there is no point in having the MIPS_CPU_ISA_I ISA flag, so get rid of it. Little complication: traps.c was using a test for a pure MIPS I ISA as a test for an R3000-style cp0. To deal with that, use a check for cpu_has_3kex or cpu_has_4kex instead. cpu_has_3kex is a new macro. At the moment its default implementation is !cpu_has_4kex but this may eventually change if Linux is ever going to support the oddball MIPS processors R6000 and R8000 so users of either of these macros should not make any assumptions. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/5551/
2013-06-26 09:06:34 -06:00
} else if (cpu_has_4kex) {
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
if (regs->cp0_status & ST0_KX)
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("KX ");
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
if (regs->cp0_status & ST0_SX)
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("SX ");
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
if (regs->cp0_status & ST0_UX)
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("UX ");
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
switch (regs->cp0_status & ST0_KSU) {
case KSU_USER:
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("USER ");
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
break;
case KSU_SUPERVISOR:
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("SUPERVISOR ");
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
break;
case KSU_KERNEL:
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("KERNEL ");
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
break;
default:
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("BAD_MODE ");
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
break;
}
if (regs->cp0_status & ST0_ERL)
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("ERL ");
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
if (regs->cp0_status & ST0_EXL)
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("EXL ");
Use correct names for bits in the R3k cp0.status register. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-06-22 14:43:29 -06:00
if (regs->cp0_status & ST0_IE)
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("IE ");
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
MIPS: Fix __show_regs() output Since commit 4bcc595ccd80 ("printk: reinstate KERN_CONT for printing continuation lines") the output from __show_regs() on MIPS has been pretty unreadable due to the lack of KERN_CONT markers. Use pr_cont to provide the appropriate markers & restore the expected register output. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-19 07:33:23 -06:00
pr_cont("\n");
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: traps: print Exception Code in __show_regs() Print Exception Code when printing the Cause register. Signed-off-by: Petri Gynther <pgynther@google.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9998/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-05-08 16:10:10 -06:00
exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: traps: print Exception Code in __show_regs() Print Exception Code when printing the Cause register. Signed-off-by: Petri Gynther <pgynther@google.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9998/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-05-08 16:10:10 -06:00
if (1 <= exccode && exccode <= 5)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
[MIPS] Make facility to convert CPU types to strings generally available. So far /proc/cpuinfo has been the only user but human readable processor name are more useful than that for proc. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 16:46:17 -06:00
printk("PrId : %08x (%s)\n", read_c0_prid(),
cpu_name_string());
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
[MIPS] IP22: Fix warning. CC arch/mips/sgi-ip22/ip22-berr.o arch/mips/sgi-ip22/ip22-berr.c: In function 'ip22_be_interrupt': arch/mips/sgi-ip22/ip22-berr.c:100: warning: passing argument 2 of 'die_if_kernel' discards qualifiers from pointer target type Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-14 16:27:21 -06:00
/*
* FIXME: really the generic show_regs should take a const pointer argument.
*/
void show_regs(struct pt_regs *regs)
{
MIPS: Remove no-op/identity casts Clean up instances of casts to the type that a value already has, since they are effectively no-ops and only serve to complicate the code. This is the result of the following semantic patch: @identitycast@ type T; T *A; @@ - (T *)(A) + A Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19599/
2018-08-31 12:49:20 -06:00
__show_regs(regs);
MIPS: Call dump_stack() from show_regs() The generic nmi_cpu_backtrace() function calls show_regs() when a struct pt_regs is available, and dump_stack() otherwise. If we were to make use of the generic nmi_cpu_backtrace() with MIPS' current implementation of show_regs() this would mean that we see only register data with no accompanying stack information, in contrast with our current implementation which calls dump_stack() regardless of whether register state is available. In preparation for making use of the generic nmi_cpu_backtrace() to implement arch_trigger_cpumask_backtrace(), have our implementation of show_regs() call dump_stack() and drop the explicit dump_stack() call in arch_dump_stack() which is invoked by arch_trigger_cpumask_backtrace(). This will allow the output we produce to remain the same after a later patch switches to using nmi_cpu_backtrace(). It may mean that we produce extra stack output in other uses of show_regs(), but this: 1) Seems harmless. 2) Is good for consistency between arch_trigger_cpumask_backtrace() and other users of show_regs(). 3) Matches the behaviour of the ARM & PowerPC architectures. Marked for stable back to v4.9 as a prerequisite of the following patch "MIPS: Call dump_stack() from show_regs()". Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/19596/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Huacai Chen <chenhc@lemote.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org # v4.9+
2018-06-22 11:55:45 -06:00
dump_stack();
[MIPS] IP22: Fix warning. CC arch/mips/sgi-ip22/ip22-berr.o arch/mips/sgi-ip22/ip22-berr.c: In function 'ip22_be_interrupt': arch/mips/sgi-ip22/ip22-berr.c:100: warning: passing argument 2 of 'die_if_kernel' discards qualifiers from pointer target type Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-14 16:27:21 -06:00
}
MIPS: kprobe: Add support. This patch is based on previous work by Sony and Himanshu Chauhan. I have done some cleanup and implemented JProbes and KRETPROBES. The KRETPROBES part is pretty much copied verbatim from powerpc. A possible future enhance might be to factor out the common code. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: Himanshu Chauhan <hschauhan@nulltrace.org> To: linux-mips@linux-mips.org To: ananth@in.ibm.com, To: anil.s.keshavamurthy@intel.com To: davem@davemloft.net To: masami.hiramatsu.pt@hitachi.com Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1525/ Patchwork: https://patchwork.linux-mips.org/patch/1530/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-03 12:22:20 -06:00
void show_registers(struct pt_regs *regs)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
{
[MIPS] Add support for MIPS CMP platform. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 10:14:26 -06:00
const int field = 2 * sizeof(unsigned long);
MIPS: Print correct PC in trace dump after NMI exception An NMI exception delivered from YAMON delivers the PC in ErrorPC instead of EPC. It's also necessary to clear the Status.BEV bit for the page fault exception handler to work properly. [ralf@linux-mips: Let the assembler do the loading of the mask value rather than the convoluted explicit %hi/%lo manual relocation sequence from the original patch.] Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6035/ Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6084/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-10-08 05:39:31 -06:00
mm_segment_t old_fs = get_fs();
[MIPS] Add support for MIPS CMP platform. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 10:14:26 -06:00
[MIPS] IP22: Fix warning. CC arch/mips/sgi-ip22/ip22-berr.o arch/mips/sgi-ip22/ip22-berr.c: In function 'ip22_be_interrupt': arch/mips/sgi-ip22/ip22-berr.c:100: warning: passing argument 2 of 'die_if_kernel' discards qualifiers from pointer target type Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-14 16:27:21 -06:00
__show_regs(regs);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
print_modules();
[MIPS] Add support for MIPS CMP platform. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 10:14:26 -06:00
printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
current->comm, current->pid, current_thread_info(), current,
field, current_thread_info()->tp_value);
if (cpu_has_userlocal) {
unsigned long tls;
tls = read_c0_userlocal();
if (tls != current_thread_info()->tp_value)
printk("*HwTLS: %0*lx\n", field, tls);
}
MIPS: Print correct PC in trace dump after NMI exception An NMI exception delivered from YAMON delivers the PC in ErrorPC instead of EPC. It's also necessary to clear the Status.BEV bit for the page fault exception handler to work properly. [ralf@linux-mips: Let the assembler do the loading of the mask value rather than the convoluted explicit %hi/%lo manual relocation sequence from the original patch.] Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6035/ Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6084/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-10-08 05:39:31 -06:00
if (!user_mode(regs))
/* Necessary for getting the correct stack content */
set_fs(KERNEL_DS);
[MIPS] dump_stack() based on prologue code analysis Instead of dump all possible address in the stack, unwind the stack frame based on prologue code analysis, as like as get_wchan() does. While the code analysis might fail for some reason, there is a new kernel option "raw_show_trace" to disable this feature. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-29 08:27:20 -06:00
show_stacktrace(current, regs);
[MIPS] Make show_code static and add __user tag Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-13 08:51:46 -06:00
show_code((unsigned int __user *) regs->cp0_epc);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
printk("\n");
MIPS: Print correct PC in trace dump after NMI exception An NMI exception delivered from YAMON delivers the PC in ErrorPC instead of EPC. It's also necessary to clear the Status.BEV bit for the page fault exception handler to work properly. [ralf@linux-mips: Let the assembler do the loading of the mask value rather than the convoluted explicit %hi/%lo manual relocation sequence from the original patch.] Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6035/ Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6084/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-10-08 05:39:31 -06:00
set_fs(old_fs);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
MIPS: Make the die_lock be raw On preempt-rt this lock needs to be raw, so it does not get converted to a sleeping spinlock. Trying to sleep in a panic is not really desireable. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2636/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-07-23 06:41:24 -06:00
static DEFINE_RAW_SPINLOCK(die_lock);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: Clean up notify_die() usage. The sixth argument of notify_die() is a signal number, the fifth is a trap number. Instead of passing a signal number in a randomly selected argument, pass it in the sixth. Extract the exception code from regs and pass that as the trap number. Get rid of redundant cast, and remove some gratuitous spaces. Nobody actually does anything with the signal number or trap number, but we might as well populate them with sensible values. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1532/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-03 16:44:43 -06:00
void __noreturn die(const char *str, struct pt_regs *regs)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
{
static int die_counter;
MIPS: die() does not call die notifier chain The MIPS implementation of die() forgets to call notify_die() and thus notifiers registered via register_die_notifier() are not called. This results in kgdb not being activated on exceptions. The only subtlety is that notify_die declares its regs argument w/o const, so the const had to be removed from mips die() as well. [Ralf: Fixed build error for SGI IP22 and IP28 platforms.] Signed-off-by: Yury Polyanskiy <ypolyans@princeton.edu> Cc: linux-mips@linux-mips.org Patchworks: http://patchwork.linux-mips.org/patch/1142/ Acked-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2010-04-25 22:53:10 -06:00
int sig = SIGSEGV;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: Call oops_enter, oops_exit in die This allows pause_on_oops and mtdoops to work. Signed-off-by: Nathan Lynch <ntl@pobox.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2810/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-09-30 12:49:35 -06:00
oops_enter();
MIPS: Set trap_no field in thread_struct on exception. This reverts commit 7281cd22973008a782860e48ed8d85d00204168c and adds actual functionality to use the field.
2015-07-28 12:37:43 -06:00
if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
MIPS: traps: Reformat notify_die invocations to 80 columns. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-10-09 00:54:15 -06:00
SIGSEGV) == NOTIFY_STOP)
MIPS: Fix duplicate invocation of notify_die. Initial patch by Yury Polyanskiy <ypolyans@princeton.edu>. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2373/
2011-05-13 03:33:28 -06:00
sig = 0;
mips,kgdb: kdb low level trap catch and stack trace The only way the debugger can handle a trap in inside rcu_lock, notify_die, or atomic_notifier_call_chain without a recursive fault is to have a low level "first opportunity handler" do_trap_or_bp() handler. Generally this will be something the vast majority of folks will not need, but for those who need it, it is added as a kernel .config option called KGDB_LOW_LEVEL_TRAP. Also added was a die notification for oops such that kdb can catch an oops for analysis. There appeared to be no obvious way to pass the struct pt_regs from the original exception back to the stack back tracer, so a special case was added to show_stack() for when kdb is active because you generally desire to generally look at the back trace of the original exception. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Acked-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-20 20:04:26 -06:00
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
console_verbose();
MIPS: Make the die_lock be raw On preempt-rt this lock needs to be raw, so it does not get converted to a sleeping spinlock. Trying to sleep in a panic is not really desireable. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2636/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-07-23 06:41:24 -06:00
raw_spin_lock_irq(&die_lock);
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 02:45:45 -06:00
bust_spinlocks(1);
MIPS: die() does not call die notifier chain The MIPS implementation of die() forgets to call notify_die() and thus notifiers registered via register_die_notifier() are not called. This results in kgdb not being activated on exceptions. The only subtlety is that notify_die declares its regs argument w/o const, so the const had to be removed from mips die() as well. [Ralf: Fixed build error for SGI IP22 and IP28 platforms.] Signed-off-by: Yury Polyanskiy <ypolyans@princeton.edu> Cc: linux-mips@linux-mips.org Patchworks: http://patchwork.linux-mips.org/patch/1142/ Acked-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2010-04-25 22:53:10 -06:00
Don't print file name and line in die and die_if_kernel. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-13 10:07:54 -06:00
printk("%s[#%d]:\n", str, ++die_counter);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
show_registers(regs);
taint: add explicit flag to show whether lock dep is still OK. Fix up all callers as they were before, with make one change: an unsigned module taints the kernel, but doesn't turn off lockdep. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
2013-01-20 23:47:39 -07:00
add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
MIPS: Make the die_lock be raw On preempt-rt this lock needs to be raw, so it does not get converted to a sleeping spinlock. Trying to sleep in a panic is not really desireable. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2636/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-07-23 06:41:24 -06:00
raw_spin_unlock_irq(&die_lock);
[MIPS] Honour "panic_on_oops" sysctl. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-20 10:52:02 -06:00
MIPS: Call oops_enter, oops_exit in die This allows pause_on_oops and mtdoops to work. Signed-off-by: Nathan Lynch <ntl@pobox.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2810/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-09-30 12:49:35 -06:00
oops_exit();
[MIPS] Honour "panic_on_oops" sysctl. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-20 10:52:02 -06:00
if (in_interrupt())
panic("Fatal exception in interrupt");
MIPS: panic immediately when panic_on_oops MIPS wants to sleep 5 seconds before panicking when panic_on_oops is set, with no apparent reason. Remove this feature, since some users may want their systems to fail as quickly as possible. Users who want to delay reboot after panic can use PANIC_TIMEOUT. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Cc: James E.J. Bottomley <jejb@parisc-linux.org> Cc: Helge Deller <deller@gmx.de> Cc: linux-mips@linux-mips.org Cc: linux-parisc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12845/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-03-09 13:08:42 -07:00
if (panic_on_oops)
[MIPS] Honour "panic_on_oops" sysctl. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-20 10:52:02 -06:00
panic("Fatal exception");
MIPS: kdump: Add support [ralf@linux-mips.org: Original patch by Maxim Uvarov <muvarov@gmail.com> with plenty of further shining, polishing, debugging and testing by me.] Signed-off-by: Maxim Uvarov <muvarov@gmail.com> Cc: linux-mips@linux-mips.org Cc: kexec@lists.infradead.org Cc: horms@verge.net.au Patchwork: https://patchwork.linux-mips.org/patch/1025/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-10-11 10:14:58 -06:00
if (regs && kexec_should_crash(current))
crash_kexec(regs);
MIPS: die() does not call die notifier chain The MIPS implementation of die() forgets to call notify_die() and thus notifiers registered via register_die_notifier() are not called. This results in kgdb not being activated on exceptions. The only subtlety is that notify_die declares its regs argument w/o const, so the const had to be removed from mips die() as well. [Ralf: Fixed build error for SGI IP22 and IP28 platforms.] Signed-off-by: Yury Polyanskiy <ypolyans@princeton.edu> Cc: linux-mips@linux-mips.org Patchworks: http://patchwork.linux-mips.org/patch/1142/ Acked-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2010-04-25 22:53:10 -06:00
do_exit(sig);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
[MIPS] Fix data bus error recovery With -ffunction-section the entries in __dbe_table aren't no longer sorted, so the lookup of exception addresses in do_be() failed for some addresses. To avoid this we now sort __dbe_table. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-08-04 11:44:34 -06:00
extern struct exception_table_entry __start___dbe_table[];
extern struct exception_table_entry __stop___dbe_table[];
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
[MIPS] Make __declare_dbe_table static and avoid it getting optimized away Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-18 08:57:09 -07:00
__asm__(
" .section __dbe_table, \"a\"\n"
" .previous \n");
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/* Given an address, look for it in the exception tables. */
static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
{
const struct exception_table_entry *e;
lib/extable.c: use bsearch() library function in search_extable() [thomas@m3y3r.de: v3: fix arch specific implementations] Link: http://lkml.kernel.org/r/1497890858.12931.7.camel@m3y3r.de Signed-off-by: Thomas Meyer <thomas@m3y3r.de> Cc: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2017-07-10 16:51:58 -06:00
e = search_extable(__start___dbe_table,
__stop___dbe_table - __start___dbe_table, addr);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
if (!e)
e = search_module_dbetables(addr);
return e;
}
asmlinkage void do_be(struct pt_regs *regs)
{
const int field = 2 * sizeof(unsigned long);
const struct exception_table_entry *fixup = NULL;
int data = regs->cp0_cause & 4;
int action = MIPS_BE_FATAL;
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
enum ctx_state prev_state;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
prev_state = exception_enter();
MIPS: Whitespace cleanup. Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-01-22 04:59:30 -07:00
/* XXX For now. Fixme, this searches the wrong table ... */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
if (data && !user_mode(regs))
fixup = search_dbe_tables(exception_epc(regs));
if (fixup)
action = MIPS_BE_FIXUP;
if (board_be_handler)
[MIPS] Sparse: Use NULL for pointer This fixes a sparse warning: arch/mips/kernel/traps.c:376:44: warning: Using plain integer as NULL pointer Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-12 10:49:49 -06:00
action = board_be_handler(regs, fixup != NULL);
MIPS: Print CM error reports upon bus errors If a bus error occurs on a system with a MIPS Coherence Manager (CM) then the CM may hold useful diagnostic information. Printing this out has so far been left up to boards, with the requirement that they register a board_be_handler function & call mips_cm_error_decode() from there. In order to avoid boards other than Malta needing to duplicate this code, call mips_cm_error_decode() automatically if the board registers no board_be_handler, and remove the Malta implementation of that. This patch results in no functional change, but removes a further piece of platform-specific code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14350/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-05 11:18:17 -06:00
else
mips_cm_error_report();
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
switch (action) {
case MIPS_BE_DISCARD:
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
goto out;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
case MIPS_BE_FIXUP:
if (fixup) {
regs->cp0_epc = fixup->nextinsn;
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
goto out;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
break;
default:
break;
}
/*
* Assume it would be too dangerous to continue ...
*/
printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
data ? "Data" : "Instruction",
field, regs->cp0_epc, field, regs->regs[31]);
MIPS: Set trap_no field in thread_struct on exception. This reverts commit 7281cd22973008a782860e48ed8d85d00204168c and adds actual functionality to use the field.
2015-07-28 12:37:43 -06:00
if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
MIPS: traps: Reformat notify_die invocations to 80 columns. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-10-09 00:54:15 -06:00
SIGBUS) == NOTIFY_STOP)
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
goto out;
[MIPS] kgdb: add arch support for the kernel's kgdb core The new kgdb architecture specific handler registers and unregisters dynamically for exceptions depending on when you configure a kgdb I/O driver. Aside from initializing the exceptions earlier in the boot process, kgdb should have no impact on a device when it is compiled in so long as an I/O module is not configured for use. There have been quite a number of contributors during the existence of this patch (see arch/mips/kernel/kgdb.c). Most recently Jason re-wrote the mips kgdb logic to use the die notification handlers. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-07-29 14:58:53 -06:00
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
die_if_kernel("Oops", regs);
force_sig(SIGBUS, current);
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
out:
exception_exit(prev_state);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
/*
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
* ll/sc, rdhwr, sync emulation
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
*/
#define OPCODE 0xfc000000
#define BASE 0x03e00000
#define RT 0x001f0000
#define OFFSET 0x0000ffff
#define LL 0xc0000000
#define SC 0xe0000000
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
#define SPEC0 0x00000000
NPTL, round one. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-04-13 11:43:59 -06:00
#define SPEC3 0x7c000000
#define RD 0x0000f800
#define FUNC 0x0000003f
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
#define SYNC 0x0000000f
NPTL, round one. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-04-13 11:43:59 -06:00
#define RDHWR 0x0000003b
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
/* microMIPS definitions */
#define MM_POOL32A_FUNC 0xfc00ffff
#define MM_RDHWR 0x00006b3c
#define MM_RS 0x001f0000
#define MM_RT 0x03e00000
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
* The ll_bit is cleared by r*_switch.S
*/
MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assembler This way it doesn't have to use CONFIG_CPU_HAS_LLSC anymore. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-16 18:25:05 -06:00
unsigned int ll_bit;
struct task_struct *ll_task;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
{
Sparseify MIPS. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-03-01 12:22:29 -07:00
unsigned long value, __user *vaddr;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
long offset;
/*
* analyse the ll instruction that just caused a ri exception
* and put the referenced address to addr.
*/
/* sign extend offset */
offset = opcode & OFFSET;
offset <<= 16;
offset >>= 16;
Sparseify MIPS. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-03-01 12:22:29 -07:00
vaddr = (unsigned long __user *)
MIPS: Whitespace cleanups and reformatting. Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <sjhill@mips.com> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4781/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-01-12 16:29:27 -07:00
((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
if ((unsigned long)vaddr & 3)
return SIGBUS;
if (get_user(value, vaddr))
return SIGSEGV;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
preempt_disable();
if (ll_task == NULL || ll_task == current) {
ll_bit = 1;
} else {
ll_bit = 0;
}
ll_task = current;
preempt_enable();
regs->regs[(opcode & RT) >> 16] = value;
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
return 0;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
{
Sparseify MIPS. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-03-01 12:22:29 -07:00
unsigned long __user *vaddr;
unsigned long reg;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
long offset;
/*
* analyse the sc instruction that just caused a ri exception
* and put the referenced address to addr.
*/
/* sign extend offset */
offset = opcode & OFFSET;
offset <<= 16;
offset >>= 16;
Sparseify MIPS. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-03-01 12:22:29 -07:00
vaddr = (unsigned long __user *)
MIPS: Whitespace cleanups and reformatting. Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <sjhill@mips.com> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4781/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-01-12 16:29:27 -07:00
((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
reg = (opcode & RT) >> 16;
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
if ((unsigned long)vaddr & 3)
return SIGBUS;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
preempt_disable();
if (ll_bit == 0 || ll_task != current) {
regs->regs[reg] = 0;
preempt_enable();
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
return 0;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
preempt_enable();
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
if (put_user(regs->regs[reg], vaddr))
return SIGSEGV;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
regs->regs[reg] = 1;
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
return 0;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
/*
* ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
* opcodes are supposed to result in coprocessor unusable exceptions if
* executed on ll/sc-less processors. That's the theory. In practice a
* few processors such as NEC's VR4100 throw reserved instruction exceptions
* instead, so we're doing the emulation thing in both exception handlers.
*/
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
{
MIPS: add support for software performance events Software events are required as part of the measurable stuff by the Linux performance counter subsystem. Here is the list of events added by this patch: PERF_COUNT_SW_PAGE_FAULTS PERF_COUNT_SW_PAGE_FAULTS_MIN PERF_COUNT_SW_PAGE_FAULTS_MAJ PERF_COUNT_SW_ALIGNMENT_FAULTS PERF_COUNT_SW_EMULATION_FAULTS Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Acked-by: David Daney <ddaney@caviumnetworks.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Patchwork: https://patchwork.linux-mips.org/patch/1686/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-12 05:37:21 -06:00
if ((opcode & OPCODE) == LL) {
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
perf: Remove the nmi parameter from the swevent and overflow interface The nmi parameter indicated if we could do wakeups from the current context, if not, we would set some state and self-IPI and let the resulting interrupt do the wakeup. For the various event classes: - hardware: nmi=0; PMI is in fact an NMI or we run irq_work_run from the PMI-tail (ARM etc.) - tracepoint: nmi=0; since tracepoint could be from NMI context. - software: nmi=[0,1]; some, like the schedule thing cannot perform wakeups, and hence need 0. As one can see, there is very little nmi=1 usage, and the down-side of not using it is that on some platforms some software events can have a jiffy delay in wakeup (when arch_irq_work_raise isn't implemented). The up-side however is that we can remove the nmi parameter and save a bunch of conditionals in fast paths. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Michael Cree <mcree@orcon.net.nz> Cc: Will Deacon <will.deacon@arm.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> Cc: Anton Blanchard <anton@samba.org> Cc: Eric B Munson <emunson@mgebm.net> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: David S. Miller <davem@davemloft.net> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Jason Wessel <jason.wessel@windriver.com> Cc: Don Zickus <dzickus@redhat.com> Link: http://lkml.kernel.org/n/tip-agjev8eu666tvknpb3iaj0fg@git.kernel.org Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-06-27 06:41:57 -06:00
1, regs, 0);
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
return simulate_ll(regs, opcode);
MIPS: add support for software performance events Software events are required as part of the measurable stuff by the Linux performance counter subsystem. Here is the list of events added by this patch: PERF_COUNT_SW_PAGE_FAULTS PERF_COUNT_SW_PAGE_FAULTS_MIN PERF_COUNT_SW_PAGE_FAULTS_MAJ PERF_COUNT_SW_ALIGNMENT_FAULTS PERF_COUNT_SW_EMULATION_FAULTS Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Acked-by: David Daney <ddaney@caviumnetworks.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Patchwork: https://patchwork.linux-mips.org/patch/1686/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-12 05:37:21 -06:00
}
if ((opcode & OPCODE) == SC) {
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
perf: Remove the nmi parameter from the swevent and overflow interface The nmi parameter indicated if we could do wakeups from the current context, if not, we would set some state and self-IPI and let the resulting interrupt do the wakeup. For the various event classes: - hardware: nmi=0; PMI is in fact an NMI or we run irq_work_run from the PMI-tail (ARM etc.) - tracepoint: nmi=0; since tracepoint could be from NMI context. - software: nmi=[0,1]; some, like the schedule thing cannot perform wakeups, and hence need 0. As one can see, there is very little nmi=1 usage, and the down-side of not using it is that on some platforms some software events can have a jiffy delay in wakeup (when arch_irq_work_raise isn't implemented). The up-side however is that we can remove the nmi parameter and save a bunch of conditionals in fast paths. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Michael Cree <mcree@orcon.net.nz> Cc: Will Deacon <will.deacon@arm.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> Cc: Anton Blanchard <anton@samba.org> Cc: Eric B Munson <emunson@mgebm.net> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: David S. Miller <davem@davemloft.net> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Jason Wessel <jason.wessel@windriver.com> Cc: Don Zickus <dzickus@redhat.com> Link: http://lkml.kernel.org/n/tip-agjev8eu666tvknpb3iaj0fg@git.kernel.org Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-06-27 06:41:57 -06:00
1, regs, 0);
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
return simulate_sc(regs, opcode);
MIPS: add support for software performance events Software events are required as part of the measurable stuff by the Linux performance counter subsystem. Here is the list of events added by this patch: PERF_COUNT_SW_PAGE_FAULTS PERF_COUNT_SW_PAGE_FAULTS_MIN PERF_COUNT_SW_PAGE_FAULTS_MAJ PERF_COUNT_SW_ALIGNMENT_FAULTS PERF_COUNT_SW_EMULATION_FAULTS Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Acked-by: David Daney <ddaney@caviumnetworks.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Patchwork: https://patchwork.linux-mips.org/patch/1686/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-12 05:37:21 -06:00
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
return -1; /* Must be something else ... */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
NPTL, round one. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-04-13 11:43:59 -06:00
/*
* Simulate trapping 'rdhwr' instructions to provide user accessible
[MIPS] Added missing cases for rdhwr emulation Some of these are architecturally required for R2 processors so lets try to be bit closer to the real thing. This also provides access to the CPU cycle timer, even on multiprocessors. In that aspect its currently bug compatible to what would happen on a R2-based SMP. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-05-08 11:02:16 -06:00
* registers not implemented in hardware.
NPTL, round one. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-04-13 11:43:59 -06:00
*/
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
NPTL, round one. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-04-13 11:43:59 -06:00
{
[PATCH] mips: task_thread_info() Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-12 02:06:07 -07:00
struct thread_info *ti = task_thread_info(current);
NPTL, round one. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-04-13 11:43:59 -06:00
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
1, regs, 0);
switch (rd) {
MIPS: Clean up RDHWR handling No preprocessor definitions are used in the handling of the registers accessible with the RDHWR instruction, nor the corresponding bits in the CP0 HWREna register. Add definitions for both the register numbers (MIPS_HWR_*) and HWREna bits (MIPS_HWRENA_*) in asm/mipsregs.h and make use of them in the initialisation of HWREna and emulation of the RDHWR instruction. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: David Daney <david.daney@cavium.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-15 12:29:52 -06:00
case MIPS_HWR_CPUNUM: /* CPU number */
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
regs->regs[rt] = smp_processor_id();
return 0;
MIPS: Clean up RDHWR handling No preprocessor definitions are used in the handling of the registers accessible with the RDHWR instruction, nor the corresponding bits in the CP0 HWREna register. Add definitions for both the register numbers (MIPS_HWR_*) and HWREna bits (MIPS_HWRENA_*) in asm/mipsregs.h and make use of them in the initialisation of HWREna and emulation of the RDHWR instruction. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: David Daney <david.daney@cavium.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-15 12:29:52 -06:00
case MIPS_HWR_SYNCISTEP: /* SYNCI length */
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
regs->regs[rt] = min(current_cpu_data.dcache.linesz,
current_cpu_data.icache.linesz);
return 0;
MIPS: Clean up RDHWR handling No preprocessor definitions are used in the handling of the registers accessible with the RDHWR instruction, nor the corresponding bits in the CP0 HWREna register. Add definitions for both the register numbers (MIPS_HWR_*) and HWREna bits (MIPS_HWRENA_*) in asm/mipsregs.h and make use of them in the initialisation of HWREna and emulation of the RDHWR instruction. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: David Daney <david.daney@cavium.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-15 12:29:52 -06:00
case MIPS_HWR_CC: /* Read count register */
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
regs->regs[rt] = read_c0_count();
return 0;
MIPS: Clean up RDHWR handling No preprocessor definitions are used in the handling of the registers accessible with the RDHWR instruction, nor the corresponding bits in the CP0 HWREna register. Add definitions for both the register numbers (MIPS_HWR_*) and HWREna bits (MIPS_HWRENA_*) in asm/mipsregs.h and make use of them in the initialisation of HWREna and emulation of the RDHWR instruction. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: David Daney <david.daney@cavium.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-15 12:29:52 -06:00
case MIPS_HWR_CCRES: /* Count register resolution */
MIPS: Optimize current_cpu_type() for better code. o Move current_cpu_type() to a separate header file o #ifdefing on supported CPU types lets modern GCC know that certain code in callers may be discarded ideally turning current_cpu_type() into a function returning a constant. o Use current_cpu_type() rather than direct access to struct cpuinfo_mips. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5833/
2013-09-17 02:25:47 -06:00
switch (current_cpu_type()) {
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
case CPU_20KC:
case CPU_25KF:
regs->regs[rt] = 1;
break;
default:
regs->regs[rt] = 2;
}
return 0;
MIPS: Clean up RDHWR handling No preprocessor definitions are used in the handling of the registers accessible with the RDHWR instruction, nor the corresponding bits in the CP0 HWREna register. Add definitions for both the register numbers (MIPS_HWR_*) and HWREna bits (MIPS_HWRENA_*) in asm/mipsregs.h and make use of them in the initialisation of HWREna and emulation of the RDHWR instruction. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: David Daney <david.daney@cavium.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-15 12:29:52 -06:00
case MIPS_HWR_ULR: /* Read UserLocal register */
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
regs->regs[rt] = ti->tp_value;
return 0;
default:
return -1;
}
}
static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
{
NPTL, round one. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-04-13 11:43:59 -06:00
if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
int rd = (opcode & RD) >> 11;
int rt = (opcode & RT) >> 16;
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
simulate_rdhwr(regs, rd, rt);
return 0;
}
/* Not ours. */
return -1;
}
MIPS: traps.c: Correct microMIPS RDHWR emulation Fix the code to fetch and decode the whole 32-bit instruction. This only really matters with the `noulri' kernel parameter as all microMIPS processors are supposed to have all the hardware registers we support. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12281/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-30 02:08:28 -07:00
static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
{
if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
int rd = (opcode & MM_RS) >> 16;
int rt = (opcode & MM_RT) >> 21;
simulate_rdhwr(regs, rd, rt);
return 0;
NPTL, round one. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-04-13 11:43:59 -06:00
}
[MIPS] Generate SIGILL again The rdhwr emulation accidentally swallowed the SIGILL from most other illegal instructions. Make sure to return -EFAULT by default. Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-11-26 20:34:41 -07:00
/* Not ours. */
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
return -1;
}
[MIPS] Work around bogus gcc warnings. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-29 18:14:47 -07:00
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
{
MIPS: add support for software performance events Software events are required as part of the measurable stuff by the Linux performance counter subsystem. Here is the list of events added by this patch: PERF_COUNT_SW_PAGE_FAULTS PERF_COUNT_SW_PAGE_FAULTS_MIN PERF_COUNT_SW_PAGE_FAULTS_MAJ PERF_COUNT_SW_ALIGNMENT_FAULTS PERF_COUNT_SW_EMULATION_FAULTS Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Acked-by: David Daney <ddaney@caviumnetworks.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Patchwork: https://patchwork.linux-mips.org/patch/1686/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-12 05:37:21 -06:00
if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
perf: Remove the nmi parameter from the swevent and overflow interface The nmi parameter indicated if we could do wakeups from the current context, if not, we would set some state and self-IPI and let the resulting interrupt do the wakeup. For the various event classes: - hardware: nmi=0; PMI is in fact an NMI or we run irq_work_run from the PMI-tail (ARM etc.) - tracepoint: nmi=0; since tracepoint could be from NMI context. - software: nmi=[0,1]; some, like the schedule thing cannot perform wakeups, and hence need 0. As one can see, there is very little nmi=1 usage, and the down-side of not using it is that on some platforms some software events can have a jiffy delay in wakeup (when arch_irq_work_raise isn't implemented). The up-side however is that we can remove the nmi parameter and save a bunch of conditionals in fast paths. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Michael Cree <mcree@orcon.net.nz> Cc: Will Deacon <will.deacon@arm.com> Cc: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> Cc: Anton Blanchard <anton@samba.org> Cc: Eric B Munson <emunson@mgebm.net> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: David S. Miller <davem@davemloft.net> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Jason Wessel <jason.wessel@windriver.com> Cc: Don Zickus <dzickus@redhat.com> Link: http://lkml.kernel.org/n/tip-agjev8eu666tvknpb3iaj0fg@git.kernel.org Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-06-27 06:41:57 -06:00
1, regs, 0);
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
return 0;
MIPS: add support for software performance events Software events are required as part of the measurable stuff by the Linux performance counter subsystem. Here is the list of events added by this patch: PERF_COUNT_SW_PAGE_FAULTS PERF_COUNT_SW_PAGE_FAULTS_MIN PERF_COUNT_SW_PAGE_FAULTS_MAJ PERF_COUNT_SW_ALIGNMENT_FAULTS PERF_COUNT_SW_EMULATION_FAULTS Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: linux-mips@linux-mips.org Cc: a.p.zijlstra@chello.nl Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: jamie.iles@picochip.com Acked-by: David Daney <ddaney@caviumnetworks.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Patchwork: https://patchwork.linux-mips.org/patch/1686/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-12 05:37:21 -06:00
}
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
return -1; /* Must be something else ... */
NPTL, round one. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-04-13 11:43:59 -06:00
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
asmlinkage void do_ov(struct pt_regs *regs)
{
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
enum ctx_state prev_state;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
prev_state = exception_enter();
[MIPS] Make integer overflow exceptions in kernel mode fatal. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-14 14:04:54 -07:00
die_if_kernel("Integer overflow", regs);
signal/mips: Use force_sig_fault where appropriate Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper force_sig_fault. Which takes as a parameters all of the information it needs, ensures all of the fiddly bits of filling in struct siginfo are done properly and then calls force_sig_info. In short about a 5 line reduction in code for every time force_sig_info is called, which makes the calling function clearer. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-04-15 20:11:06 -06:00
force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc, current);
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
exception_exit(prev_state);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
MIPS: traps: Never enable FPU when CONFIG_MIPS_FP_SUPPORT=n When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so we'll never need to enable the FPU. Avoid doing so on a Co-Processor Unusable exception (do_cpu), and remove the Floating Point Exception handler (do_fpe) which should never be executed when the FPU is disabled. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21007/ Cc: linux-mips@linux-mips.org
2018-11-07 16:14:05 -07:00
#ifdef CONFIG_MIPS_FP_SUPPORT
MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-28 01:21:03 -06:00
/*
* Send SIGFPE according to FCSR Cause bits, which must have already
* been masked against Enable bits. This is impotant as Inexact can
* happen together with Overflow or Underflow, and `ptrace' can set
* any bits.
*/
void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
struct task_struct *tsk)
{
signal/mips: Report FPE_FLTUNK for undiagnosed floating point exceptions Most mips builds fail with arch/mips/kernel/traps.c: In function ‘force_fcr31_sig’: arch/mips/kernel/traps.c:732:2: error: ‘si_code’ may be used uninitialized in this function Fix the problem by initializing si_code with FPE_FLTUNK (undiagnosed floating point exception). Fixes: f43a54a0d916 ("signal/mips: Use force_sig_fault where appropriate") Cc: linux-mips@linux-mips.org Cc: Eric W. Biederman <ebiederm@xmission.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
2018-05-15 07:50:47 -06:00
int si_code = FPE_FLTUNK;
MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-28 01:21:03 -06:00
if (fcr31 & FPU_CSR_INV_X)
signal/mips: Use force_sig_fault where appropriate Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper force_sig_fault. Which takes as a parameters all of the information it needs, ensures all of the fiddly bits of filling in struct siginfo are done properly and then calls force_sig_info. In short about a 5 line reduction in code for every time force_sig_info is called, which makes the calling function clearer. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-04-15 20:11:06 -06:00
si_code = FPE_FLTINV;
MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-28 01:21:03 -06:00
else if (fcr31 & FPU_CSR_DIV_X)
signal/mips: Use force_sig_fault where appropriate Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper force_sig_fault. Which takes as a parameters all of the information it needs, ensures all of the fiddly bits of filling in struct siginfo are done properly and then calls force_sig_info. In short about a 5 line reduction in code for every time force_sig_info is called, which makes the calling function clearer. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-04-15 20:11:06 -06:00
si_code = FPE_FLTDIV;
MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-28 01:21:03 -06:00
else if (fcr31 & FPU_CSR_OVF_X)
signal/mips: Use force_sig_fault where appropriate Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper force_sig_fault. Which takes as a parameters all of the information it needs, ensures all of the fiddly bits of filling in struct siginfo are done properly and then calls force_sig_info. In short about a 5 line reduction in code for every time force_sig_info is called, which makes the calling function clearer. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-04-15 20:11:06 -06:00
si_code = FPE_FLTOVF;
MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-28 01:21:03 -06:00
else if (fcr31 & FPU_CSR_UDF_X)
signal/mips: Use force_sig_fault where appropriate Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper force_sig_fault. Which takes as a parameters all of the information it needs, ensures all of the fiddly bits of filling in struct siginfo are done properly and then calls force_sig_info. In short about a 5 line reduction in code for every time force_sig_info is called, which makes the calling function clearer. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-04-15 20:11:06 -06:00
si_code = FPE_FLTUND;
MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-28 01:21:03 -06:00
else if (fcr31 & FPU_CSR_INE_X)
signal/mips: Use force_sig_fault where appropriate Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper force_sig_fault. Which takes as a parameters all of the information it needs, ensures all of the fiddly bits of filling in struct siginfo are done properly and then calls force_sig_info. In short about a 5 line reduction in code for every time force_sig_info is called, which makes the calling function clearer. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-04-15 20:11:06 -06:00
si_code = FPE_FLTRES;
MIPS: signal: Remove unreachable code from force_fcr31_sig(). Based on discussion with Linus remove the impossible to reach code rather than replacing it with a BUG(). Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Link: http://lkml.kernel.org/r/20170718140651.15973-4-ebiederm@xmission.com
2017-08-07 13:14:18 -06:00
signal/mips: Use force_sig_fault where appropriate Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper force_sig_fault. Which takes as a parameters all of the information it needs, ensures all of the fiddly bits of filling in struct siginfo are done properly and then calls force_sig_info. In short about a 5 line reduction in code for every time force_sig_info is called, which makes the calling function clearer. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-04-15 20:11:06 -06:00
force_sig_fault(SIGFPE, si_code, fault_addr, tsk);
MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-28 01:21:03 -06:00
}
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
MIPS: Send proper signal and siginfo on FP emulator faults. We were unconditionally sending SIGBUS with an empty siginfo on FP emulator faults. This differs from what happens when real floating point hardware would get a fault. For most faults we need to send SIGSEGV with the faulting address filled in in the struct siginfo. Reported-by: Camm Maguire <camm@maguirefamily.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: Camm Maguire <camm@maguirefamily.org> Patchwork: https://patchwork.linux-mips.org/patch/1727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-21 17:32:26 -06:00
{
signal/mips: Use force_sig_fault where appropriate Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper force_sig_fault. Which takes as a parameters all of the information it needs, ensures all of the fiddly bits of filling in struct siginfo are done properly and then calls force_sig_info. In short about a 5 line reduction in code for every time force_sig_info is called, which makes the calling function clearer. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-04-15 20:11:06 -06:00
int si_code;
MIPS: traps: return correct si code for accessing nonmapped addresses find_vma() returns the first VMA which satisfies fault_addr < vm_end, but it does not guarantee fault_addr is actually within VMA. Therefore, kernel has to check that before it chooses correct si code on return. Signed-off-by: Petar Jovanovic <petar.jovanovic@rt-rk.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13808/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-07-13 07:23:37 -06:00
struct vm_area_struct *vma;
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
switch (sig) {
case 0:
return 0;
MIPS: Ensure FCSR cause bits are clear after invoking FPU emulator When running the emulator to handle an instruction that raised an FP unimplemented operation exception, the FCSR cause bits were being cleared. This is done to ensure that the kernel does not take an FP exception when later restoring FP context to registers. However, this was not being done when the emulator is invoked in response to a coprocessor unusable exception. This happens in 2 cases: - There is no FPU present in the system. In this case things were OK, since the FP context is never restored to hardware registers and thus no FP exception may be raised when restoring FCSR. - The FPU could not be configured to the mode required by the task. In this case it would be possible for the emulator to set cause bits which are later restored to hardware if the task migrates to a CPU whose associated FPU does support its mode requirements, or if the tasks FP mode requirements change. Consistently clear the cause bits after invoking the emulator, by moving the clearing to process_fpemu_return and ensuring this is always called before the tasks FP context is restored. This will make it easier to catch further paths invoking the emulator in future, as will be introduced in further patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9165/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-30 05:09:35 -07:00
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
case SIGFPE:
MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-28 01:21:03 -06:00
force_fcr31_sig(fcr31, fault_addr, current);
MIPS: Send proper signal and siginfo on FP emulator faults. We were unconditionally sending SIGBUS with an empty siginfo on FP emulator faults. This differs from what happens when real floating point hardware would get a fault. For most faults we need to send SIGSEGV with the faulting address filled in in the struct siginfo. Reported-by: Camm Maguire <camm@maguirefamily.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: Camm Maguire <camm@maguirefamily.org> Patchwork: https://patchwork.linux-mips.org/patch/1727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-21 17:32:26 -06:00
return 1;
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
case SIGBUS:
signal/mips: Use force_sig_fault where appropriate Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper force_sig_fault. Which takes as a parameters all of the information it needs, ensures all of the fiddly bits of filling in struct siginfo are done properly and then calls force_sig_info. In short about a 5 line reduction in code for every time force_sig_info is called, which makes the calling function clearer. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-04-15 20:11:06 -06:00
force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr, current);
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
return 1;
case SIGSEGV:
down_read(&current->mm->mmap_sem);
MIPS: traps: return correct si code for accessing nonmapped addresses find_vma() returns the first VMA which satisfies fault_addr < vm_end, but it does not guarantee fault_addr is actually within VMA. Therefore, kernel has to check that before it chooses correct si code on return. Signed-off-by: Petar Jovanovic <petar.jovanovic@rt-rk.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13808/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-07-13 07:23:37 -06:00
vma = find_vma(current->mm, (unsigned long)fault_addr);
if (vma && (vma->vm_start <= (unsigned long)fault_addr))
signal/mips: Use force_sig_fault where appropriate Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper force_sig_fault. Which takes as a parameters all of the information it needs, ensures all of the fiddly bits of filling in struct siginfo are done properly and then calls force_sig_info. In short about a 5 line reduction in code for every time force_sig_info is called, which makes the calling function clearer. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-04-15 20:11:06 -06:00
si_code = SEGV_ACCERR;
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
else
signal/mips: Use force_sig_fault where appropriate Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper force_sig_fault. Which takes as a parameters all of the information it needs, ensures all of the fiddly bits of filling in struct siginfo are done properly and then calls force_sig_info. In short about a 5 line reduction in code for every time force_sig_info is called, which makes the calling function clearer. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-04-15 20:11:06 -06:00
si_code = SEGV_MAPERR;
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
up_read(&current->mm->mmap_sem);
signal/mips: Use force_sig_fault where appropriate Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper force_sig_fault. Which takes as a parameters all of the information it needs, ensures all of the fiddly bits of filling in struct siginfo are done properly and then calls force_sig_info. In short about a 5 line reduction in code for every time force_sig_info is called, which makes the calling function clearer. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-04-15 20:11:06 -06:00
force_sig_fault(SIGSEGV, si_code, fault_addr, current);
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
return 1;
default:
MIPS: Send proper signal and siginfo on FP emulator faults. We were unconditionally sending SIGBUS with an empty siginfo on FP emulator faults. This differs from what happens when real floating point hardware would get a fault. For most faults we need to send SIGSEGV with the faulting address filled in in the struct siginfo. Reported-by: Camm Maguire <camm@maguirefamily.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: Camm Maguire <camm@maguirefamily.org> Patchwork: https://patchwork.linux-mips.org/patch/1727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-21 17:32:26 -06:00
force_sig(sig, current);
return 1;
}
}
MIPS: Support for hybrid FPRs Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but accesses to odd indexed single registers use bits 63:32 of the preceeding even indexed 64b register. In this mode all FP code except that built for the plain FP64 ABI can execute correctly. Most notably a combination of FP64A & FP32 code can execute correctly, allowing for existing FP32 binaries to be linked with new FP64A binaries that can make use of 64 bit FP & MSA. Hybrid FPRs are implemented by setting both the FR & FRE bits, trapping & emulating single precision FP instructions (via Reserved Instruction exceptions) whilst allowing others to execute natively. It therefore has a penalty in terms of execution speed, and should only be used when no fully native mode can be. As more binaries are recompiled to use either the FPXX or FP64(A) ABIs, the need for hybrid FPRs should diminish. However in the short to mid term it allows for a gradual transition towards that world, rather than a complete ABI break which is not feasible for some users & not desirable for many. A task will be executed using the hybrid FPR scheme when its TIF_HYBRID_FPREGS flag is set & TIF_32BIT_FPREGS is clear. A further patch will set the flags as necessary, this patch simply adds the infrastructure necessary for the hybrid FPR mode to work. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-09-11 01:30:20 -06:00
static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
unsigned long old_epc, unsigned long old_ra)
{
union mips_instruction inst = { .word = opcode };
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
void __user *fault_addr;
unsigned long fcr31;
MIPS: Support for hybrid FPRs Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but accesses to odd indexed single registers use bits 63:32 of the preceeding even indexed 64b register. In this mode all FP code except that built for the plain FP64 ABI can execute correctly. Most notably a combination of FP64A & FP32 code can execute correctly, allowing for existing FP32 binaries to be linked with new FP64A binaries that can make use of 64 bit FP & MSA. Hybrid FPRs are implemented by setting both the FR & FRE bits, trapping & emulating single precision FP instructions (via Reserved Instruction exceptions) whilst allowing others to execute natively. It therefore has a penalty in terms of execution speed, and should only be used when no fully native mode can be. As more binaries are recompiled to use either the FPXX or FP64(A) ABIs, the need for hybrid FPRs should diminish. However in the short to mid term it allows for a gradual transition towards that world, rather than a complete ABI break which is not feasible for some users & not desirable for many. A task will be executed using the hybrid FPR scheme when its TIF_HYBRID_FPREGS flag is set & TIF_32BIT_FPREGS is clear. A further patch will set the flags as necessary, this patch simply adds the infrastructure necessary for the hybrid FPR mode to work. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-09-11 01:30:20 -06:00
int sig;
/* If it's obviously not an FP instruction, skip it */
switch (inst.i_format.opcode) {
case cop1_op:
case cop1x_op:
case lwc1_op:
case ldc1_op:
case swc1_op:
case sdc1_op:
break;
default:
return -1;
}
/*
* do_ri skipped over the instruction via compute_return_epc, undo
* that for the FPU emulator.
*/
regs->cp0_epc = old_epc;
regs->regs[31] = old_ra;
/* Run the emulator */
sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
&fault_addr);
MIPS: Always clear FCSR cause bits after emulation Clear any FCSR cause bits recorded in the saved FPU context after emulation in all cases rather than in `do_fpe' only, so that any unmasked IEEE 754 exception left from emulation does not cause a fatal kernel-mode FPE hardware exception with the CTC1 instruction used by the kernel to subsequently restore FCSR hardware from the saved FPU context. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9704/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:10 -06:00
/*
MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-28 01:21:03 -06:00
* We can't allow the emulated instruction to leave any
* enabled Cause bits set in $fcr31.
MIPS: Always clear FCSR cause bits after emulation Clear any FCSR cause bits recorded in the saved FPU context after emulation in all cases rather than in `do_fpe' only, so that any unmasked IEEE 754 exception left from emulation does not cause a fatal kernel-mode FPE hardware exception with the CTC1 instruction used by the kernel to subsequently restore FCSR hardware from the saved FPU context. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9704/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:10 -06:00
*/
MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-28 01:21:03 -06:00
fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
current->thread.fpu.fcr31 &= ~fcr31;
MIPS: Support for hybrid FPRs Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but accesses to odd indexed single registers use bits 63:32 of the preceeding even indexed 64b register. In this mode all FP code except that built for the plain FP64 ABI can execute correctly. Most notably a combination of FP64A & FP32 code can execute correctly, allowing for existing FP32 binaries to be linked with new FP64A binaries that can make use of 64 bit FP & MSA. Hybrid FPRs are implemented by setting both the FR & FRE bits, trapping & emulating single precision FP instructions (via Reserved Instruction exceptions) whilst allowing others to execute natively. It therefore has a penalty in terms of execution speed, and should only be used when no fully native mode can be. As more binaries are recompiled to use either the FPXX or FP64(A) ABIs, the need for hybrid FPRs should diminish. However in the short to mid term it allows for a gradual transition towards that world, rather than a complete ABI break which is not feasible for some users & not desirable for many. A task will be executed using the hybrid FPR scheme when its TIF_HYBRID_FPREGS flag is set & TIF_32BIT_FPREGS is clear. A further patch will set the flags as necessary, this patch simply adds the infrastructure necessary for the hybrid FPR mode to work. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-09-11 01:30:20 -06:00
/* Restore the hardware register state */
own_fpu(1);
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
/* Send a signal if required. */
process_fpemu_return(sig, fault_addr, fcr31);
MIPS: Support for hybrid FPRs Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but accesses to odd indexed single registers use bits 63:32 of the preceeding even indexed 64b register. In this mode all FP code except that built for the plain FP64 ABI can execute correctly. Most notably a combination of FP64A & FP32 code can execute correctly, allowing for existing FP32 binaries to be linked with new FP64A binaries that can make use of 64 bit FP & MSA. Hybrid FPRs are implemented by setting both the FR & FRE bits, trapping & emulating single precision FP instructions (via Reserved Instruction exceptions) whilst allowing others to execute natively. It therefore has a penalty in terms of execution speed, and should only be used when no fully native mode can be. As more binaries are recompiled to use either the FPXX or FP64(A) ABIs, the need for hybrid FPRs should diminish. However in the short to mid term it allows for a gradual transition towards that world, rather than a complete ABI break which is not feasible for some users & not desirable for many. A task will be executed using the hybrid FPR scheme when its TIF_HYBRID_FPREGS flag is set & TIF_32BIT_FPREGS is clear. A further patch will set the flags as necessary, this patch simply adds the infrastructure necessary for the hybrid FPR mode to work. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-09-11 01:30:20 -06:00
return 0;
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
* XXX Delayed fp exceptions when doing a lazy ctx switch XXX
*/
asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
{
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
enum ctx_state prev_state;
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
void __user *fault_addr;
int sig;
[MIPS] Maintain si_code field properly for FP exceptions The appended patch adds code to update siginfo_t's si_code field. It fixes e.g. a floating point overflow regression in the SBCL testsuite. Signed-off-By: Thiemo Seufer <ths@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-08-21 18:42:04 -06:00
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
prev_state = exception_enter();
MIPS: Set trap_no field in thread_struct on exception. This reverts commit 7281cd22973008a782860e48ed8d85d00204168c and adds actual functionality to use the field.
2015-07-28 12:37:43 -06:00
if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
MIPS: traps: Reformat notify_die invocations to 80 columns. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-10-09 00:54:15 -06:00
SIGFPE) == NOTIFY_STOP)
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
goto out;
MIPS: Clear [MSA]FPE CSR.Cause after notify_die() When handling floating point exceptions (FPEs) and MSA FPEs the Cause bits of the appropriate control and status register (FCSR for FPEs and MSACSR for MSA FPEs) are read and cleared before enabling interrupts, presumably so that it doesn't have to go through the pain of restoring those bits if the process is pre-empted, since writing those bits would cause another immediate exception while still in the kernel. The bits aren't normally ever restored again, since userland never expects to see them set. However for virtualisation it is necessary for the kernel to be able to restore these Cause bits, as the guest may have been interrupted in an FP exception handler but before it could read the Cause bits. This can be done by registering a die notifier, to get notified of the exception when such a value is restored, and if the PC was at the instruction which is used to restore the guest state, the handler can step over it and continue execution. The Cause bits can then remain set without causing further exceptions. For this to work safely a few changes are made: - __build_clear_fpe and __build_clear_msa_fpe no longer clear the Cause bits, and now return from exception level with interrupts disabled instead of enabled. - do_fpe() now clears the Cause bits and enables interrupts after notify_die() is called, so that the notifier can chose to return from exception without this happening. - do_msa_fpe() acts similarly, but now actually makes use of the second argument (msacsr) and calls notify_die() with the new DIE_MSAFP, allowing die notifiers to be informed of MSA FPEs too. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
2014-12-02 06:44:13 -07:00
/* Clear FCSR.Cause before enabling interrupts */
MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-28 01:21:03 -06:00
write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31));
MIPS: Clear [MSA]FPE CSR.Cause after notify_die() When handling floating point exceptions (FPEs) and MSA FPEs the Cause bits of the appropriate control and status register (FCSR for FPEs and MSACSR for MSA FPEs) are read and cleared before enabling interrupts, presumably so that it doesn't have to go through the pain of restoring those bits if the process is pre-empted, since writing those bits would cause another immediate exception while still in the kernel. The bits aren't normally ever restored again, since userland never expects to see them set. However for virtualisation it is necessary for the kernel to be able to restore these Cause bits, as the guest may have been interrupted in an FP exception handler but before it could read the Cause bits. This can be done by registering a die notifier, to get notified of the exception when such a value is restored, and if the PC was at the instruction which is used to restore the guest state, the handler can step over it and continue execution. The Cause bits can then remain set without causing further exceptions. For this to work safely a few changes are made: - __build_clear_fpe and __build_clear_msa_fpe no longer clear the Cause bits, and now return from exception level with interrupts disabled instead of enabled. - do_fpe() now clears the Cause bits and enables interrupts after notify_die() is called, so that the notifier can chose to return from exception without this happening. - do_msa_fpe() acts similarly, but now actually makes use of the second argument (msacsr) and calls notify_die() with the new DIE_MSAFP, allowing die notifiers to be informed of MSA FPEs too. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
2014-12-02 06:44:13 -07:00
local_irq_enable();
[MIPS] Panic on fp exception in kernel mode. There should never be a FP exception in kernel mode. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-30 16:35:28 -06:00
die_if_kernel("FP exception in kernel code", regs);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
if (fcr31 & FPU_CSR_UNI_X) {
/*
[MIPS] War on whitespace: cleanup initial spaces followed by tabs. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-11 01:18:41 -07:00
* Unimplemented operation exception. If we've got the full
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
* software emulator on-board, let's use it...
*
* Force FPU to dump state into task/thread context. We're
* moving a lot of data here for what is probably a single
* instruction, but the alternative is to pre-decode the FP
* register operands before invoking the emulator, which seems
* a bit extreme for what should be an infrequent event.
*/
/* Run the emulator */
MIPS: Send proper signal and siginfo on FP emulator faults. We were unconditionally sending SIGBUS with an empty siginfo on FP emulator faults. This differs from what happens when real floating point hardware would get a fault. For most faults we need to send SIGSEGV with the faulting address filled in in the struct siginfo. Reported-by: Camm Maguire <camm@maguirefamily.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Cc: Camm Maguire <camm@maguirefamily.org> Patchwork: https://patchwork.linux-mips.org/patch/1727/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-10-21 17:32:26 -06:00
sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
&fault_addr);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-28 01:21:03 -06:00
* We can't allow the emulated instruction to leave any
* enabled Cause bits set in $fcr31.
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
*/
MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-28 01:21:03 -06:00
fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
current->thread.fpu.fcr31 &= ~fcr31;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/* Restore the hardware register state */
MIPS: Whitespace cleanup. Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-01-22 04:59:30 -07:00
own_fpu(1); /* Using the FPU again. */
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
} else {
sig = SIGFPE;
fault_addr = (void __user *) regs->cp0_epc;
MIPS: Respect the FCSR exception mask for `si_code' Respect the FCSR exception mask when interpreting the IEEE 754 exception condition to report with SIGFPE in `si_code', so as not to use one that has been masked where a different one set in parallel caused the FPE hardware exception to trigger. As per the IEEE Std 754 the Inexact exception can happen together with Overflow or Underflow. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9703/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:06 -06:00
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
/* Send a signal if required. */
process_fpemu_return(sig, fault_addr, fcr31);
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
out:
exception_exit(prev_state);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
MIPS: traps: Never enable FPU when CONFIG_MIPS_FP_SUPPORT=n When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so we'll never need to enable the FPU. Avoid doing so on a Co-Processor Unusable exception (do_cpu), and remove the Floating Point Exception handler (do_fpe) which should never be executed when the FPU is disabled. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21007/ Cc: linux-mips@linux-mips.org
2018-11-07 16:14:05 -07:00
/*
* MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
* emulated more than some threshold number of instructions, force migration to
* a "CPU" that has FP support.
*/
static void mt_ase_fp_affinity(void)
{
#ifdef CONFIG_MIPS_MT_FPAFF
if (mt_fpemul_threshold > 0 &&
((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
/*
* If there's no FPU present, or if the application has already
* restricted the allowed set to exclude any CPUs with FPUs,
* we'll skip the procedure.
*/
if (cpumask_intersects(&current->cpus_allowed, &mt_fpu_cpumask)) {
cpumask_t tmask;
current->thread.user_cpus_allowed
= current->cpus_allowed;
cpumask_and(&tmask, &current->cpus_allowed,
&mt_fpu_cpumask);
set_cpus_allowed_ptr(current, &tmask);
set_thread_flag(TIF_FPUBOUND);
}
}
#endif /* CONFIG_MIPS_MT_FPAFF */
}
#else /* !CONFIG_MIPS_FP_SUPPORT */
static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
unsigned long old_epc, unsigned long old_ra)
{
return -1;
}
#endif /* !CONFIG_MIPS_FP_SUPPORT */
MIPS: traps: Correct the SIGTRAP debug ABI in `do_watch' and `do_trap_or_bp' Follow our own rules set in <asm/siginfo.h> for SIGTRAP signals issued from `do_watch' and `do_trap_or_bp' by setting the signal code to TRAP_HWBKPT and TRAP_BRKPT respectively, for Watch exceptions and for those Breakpoint exceptions whose originating BREAK instruction's code does not have a special meaning. Keep Trap exceptions unaffected as these are not debug events. No existing user software is expected to examine signal codes for these signals as SI_KERNEL has been always used here. This change makes the MIPS port more like other Linux ports, which reduces the complexity and provides for performance improvement in GDB. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Pedro Alves <palves@redhat.com> Cc: Luis Machado <lgustavo@codesourcery.com> Cc: linux-mips@linux-mips.org Cc: gdb@sourceware.org Patchwork: https://patchwork.linux-mips.org/patch/12758/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-03-03 18:44:28 -07:00
void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
[MIPS] Fix handling of trap and breakpoint instructions With fixes and cleanups from Atsushi Nemoto (anemo@mba.ocn.ne.jp). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-20 09:28:54 -06:00
const char *str)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
{
[MIPS] Fix handling of trap and breakpoint instructions With fixes and cleanups from Atsushi Nemoto (anemo@mba.ocn.ne.jp). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-20 09:28:54 -06:00
char b[40];
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
mips,kgdb: kdb low level trap catch and stack trace The only way the debugger can handle a trap in inside rcu_lock, notify_die, or atomic_notifier_call_chain without a recursive fault is to have a low level "first opportunity handler" do_trap_or_bp() handler. Generally this will be something the vast majority of folks will not need, but for those who need it, it is added as a kernel .config option called KGDB_LOW_LEVEL_TRAP. Also added was a die notification for oops such that kdb can catch an oops for analysis. There appeared to be no obvious way to pass the struct pt_regs from the original exception back to the stack back tracer, so a special case was added to show_stack() for when kdb is active because you generally desire to generally look at the back trace of the original exception. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Acked-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-20 20:04:26 -06:00
#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
MIPS: Set trap_no field in thread_struct on exception. This reverts commit 7281cd22973008a782860e48ed8d85d00204168c and adds actual functionality to use the field.
2015-07-28 12:37:43 -06:00
if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
SIGTRAP) == NOTIFY_STOP)
mips,kgdb: kdb low level trap catch and stack trace The only way the debugger can handle a trap in inside rcu_lock, notify_die, or atomic_notifier_call_chain without a recursive fault is to have a low level "first opportunity handler" do_trap_or_bp() handler. Generally this will be something the vast majority of folks will not need, but for those who need it, it is added as a kernel .config option called KGDB_LOW_LEVEL_TRAP. Also added was a die notification for oops such that kdb can catch an oops for analysis. There appeared to be no obvious way to pass the struct pt_regs from the original exception back to the stack back tracer, so a special case was added to show_stack() for when kdb is active because you generally desire to generally look at the back trace of the original exception. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Acked-by: Ralf Baechle <ralf@linux-mips.org>
2010-05-20 20:04:26 -06:00
return;
#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
MIPS: Set trap_no field in thread_struct on exception. This reverts commit 7281cd22973008a782860e48ed8d85d00204168c and adds actual functionality to use the field.
2015-07-28 12:37:43 -06:00
if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
MIPS: traps: Reformat notify_die invocations to 80 columns. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-10-09 00:54:15 -06:00
SIGTRAP) == NOTIFY_STOP)
[MIPS] kgdb: add arch support for the kernel's kgdb core The new kgdb architecture specific handler registers and unregisters dynamically for exceptions depending on when you configure a kgdb I/O driver. Aside from initializing the exceptions earlier in the boot process, kgdb should have no impact on a device when it is compiled in so long as an I/O module is not configured for use. There have been quite a number of contributors during the existence of this patch (see arch/mips/kernel/kgdb.c). Most recently Jason re-wrote the mips kgdb logic to use the die notification handlers. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-07-29 14:58:53 -06:00
return;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
[MIPS] Fix handling of trap and breakpoint instructions With fixes and cleanups from Atsushi Nemoto (anemo@mba.ocn.ne.jp). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-20 09:28:54 -06:00
* A short test says that IRIX 5.3 sends SIGTRAP for all trap
* insns, even for trap and break codes that indicate arithmetic
* failures. Weird ...
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
* But should we continue the brokenness??? --macro
*/
[MIPS] Fix handling of trap and breakpoint instructions With fixes and cleanups from Atsushi Nemoto (anemo@mba.ocn.ne.jp). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-20 09:28:54 -06:00
switch (code) {
case BRK_OVERFLOW:
case BRK_DIVZERO:
scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
die_if_kernel(b, regs);
signal/mips: Use force_sig_fault where appropriate Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper force_sig_fault. Which takes as a parameters all of the information it needs, ensures all of the fiddly bits of filling in struct siginfo are done properly and then calls force_sig_info. In short about a 5 line reduction in code for every time force_sig_info is called, which makes the calling function clearer. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-04-15 20:11:06 -06:00
force_sig_fault(SIGFPE,
code == BRK_DIVZERO ? FPE_INTDIV : FPE_INTOVF,
(void __user *) regs->cp0_epc, current);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
break;
[MIPS] Use conditional traps for BUG_ON on MIPS II and better. This shaves of around 4kB and a few cycles for the average kernel that has CONFIG_BUG enabled. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-10-15 18:38:50 -06:00
case BRK_BUG:
[MIPS] Fix handling of trap and breakpoint instructions With fixes and cleanups from Atsushi Nemoto (anemo@mba.ocn.ne.jp). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-20 09:28:54 -06:00
die_if_kernel("Kernel bug detected", regs);
force_sig(SIGTRAP, current);
[MIPS] Use conditional traps for BUG_ON on MIPS II and better. This shaves of around 4kB and a few cycles for the average kernel that has CONFIG_BUG enabled. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-10-15 18:38:50 -06:00
break;
MIPS: Switch FPU emulator trap to BREAK instruction. Arguably using the address error handler has always been ugly. But with processors that handle unaligned loads and stores in hardware the current mechanism ceases to work so switch it to a BREAK instruction and allocate break code 514 to the FPU emulator. Yoichi Yuasa provided a build fix for CONFIG_BUG=n. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
2008-10-28 11:38:42 -06:00
case BRK_MEMU:
/*
MIPS: Correct the comment for FPU emulator traps Adjust the explanatory comment for FPU emulator traps according to ba3049ed [MIPS: Switch FPU emulator trap to BREAK instruction.]; originally coming from `do_ade'. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9672/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:24:14 -06:00
* This breakpoint code is used by the FPU emulator to retake
* control of the CPU after executing the instruction from the
* delay slot of an emulated branch.
MIPS: Switch FPU emulator trap to BREAK instruction. Arguably using the address error handler has always been ugly. But with processors that handle unaligned loads and stores in hardware the current mechanism ceases to work so switch it to a BREAK instruction and allocate break code 514 to the FPU emulator. Yoichi Yuasa provided a build fix for CONFIG_BUG=n. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
2008-10-28 11:38:42 -06:00
*
* Terminate if exception was recognized as a delay slot return
* otherwise handle as normal.
*/
if (do_dsemulret(regs))
return;
die_if_kernel("Math emu break/trap", regs);
force_sig(SIGTRAP, current);
break;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
default:
[MIPS] Fix handling of trap and breakpoint instructions With fixes and cleanups from Atsushi Nemoto (anemo@mba.ocn.ne.jp). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-20 09:28:54 -06:00
scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
die_if_kernel(b, regs);
MIPS: traps: Correct the SIGTRAP debug ABI in `do_watch' and `do_trap_or_bp' Follow our own rules set in <asm/siginfo.h> for SIGTRAP signals issued from `do_watch' and `do_trap_or_bp' by setting the signal code to TRAP_HWBKPT and TRAP_BRKPT respectively, for Watch exceptions and for those Breakpoint exceptions whose originating BREAK instruction's code does not have a special meaning. Keep Trap exceptions unaffected as these are not debug events. No existing user software is expected to examine signal codes for these signals as SI_KERNEL has been always used here. This change makes the MIPS port more like other Linux ports, which reduces the complexity and provides for performance improvement in GDB. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Pedro Alves <palves@redhat.com> Cc: Luis Machado <lgustavo@codesourcery.com> Cc: linux-mips@linux-mips.org Cc: gdb@sourceware.org Patchwork: https://patchwork.linux-mips.org/patch/12758/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-03-03 18:44:28 -07:00
if (si_code) {
signal/mips: Use force_sig_fault where appropriate Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper force_sig_fault. Which takes as a parameters all of the information it needs, ensures all of the fiddly bits of filling in struct siginfo are done properly and then calls force_sig_info. In short about a 5 line reduction in code for every time force_sig_info is called, which makes the calling function clearer. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-04-15 20:11:06 -06:00
force_sig_fault(SIGTRAP, si_code, NULL, current);
MIPS: traps: Correct the SIGTRAP debug ABI in `do_watch' and `do_trap_or_bp' Follow our own rules set in <asm/siginfo.h> for SIGTRAP signals issued from `do_watch' and `do_trap_or_bp' by setting the signal code to TRAP_HWBKPT and TRAP_BRKPT respectively, for Watch exceptions and for those Breakpoint exceptions whose originating BREAK instruction's code does not have a special meaning. Keep Trap exceptions unaffected as these are not debug events. No existing user software is expected to examine signal codes for these signals as SI_KERNEL has been always used here. This change makes the MIPS port more like other Linux ports, which reduces the complexity and provides for performance improvement in GDB. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Pedro Alves <palves@redhat.com> Cc: Luis Machado <lgustavo@codesourcery.com> Cc: linux-mips@linux-mips.org Cc: gdb@sourceware.org Patchwork: https://patchwork.linux-mips.org/patch/12758/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-03-03 18:44:28 -07:00
} else {
force_sig(SIGTRAP, current);
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
[MIPS] Fix handling of trap and breakpoint instructions With fixes and cleanups from Atsushi Nemoto (anemo@mba.ocn.ne.jp). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-20 09:28:54 -06:00
}
asmlinkage void do_bp(struct pt_regs *regs)
{
MIPS: BREAK instruction interpretation corrections Add the missing microMIPS BREAK16 instruction code interpretation and reshape code removing instruction fetching duplication and the separate call to `do_trap_or_bp' in the MIPS16 path. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9696/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:26:27 -06:00
unsigned long epc = msk_isa16_mode(exception_epc(regs));
[MIPS] Fix handling of trap and breakpoint instructions With fixes and cleanups from Atsushi Nemoto (anemo@mba.ocn.ne.jp). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-20 09:28:54 -06:00
unsigned int opcode, bcode;
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
enum ctx_state prev_state;
MIPS: traps: Set correct address limit for breakpoints and traps When a breakpoint or trap happens when operating in kernel mode but on users behalf (eg syscall) it is necessary to change the address limit to KERNEL_DS so any address checking can be bypassed and print the correct stack trace. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2013-12-04 09:39:34 -07:00
mm_segment_t seg;
seg = get_fs();
if (!user_mode(regs))
set_fs(KERNEL_DS);
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
prev_state = exception_enter();
MIPS: Set trap_no field in thread_struct on exception. This reverts commit 7281cd22973008a782860e48ed8d85d00204168c and adds actual functionality to use the field.
2015-07-28 12:37:43 -06:00
current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
if (get_isa16_mode(regs->cp0_epc)) {
MIPS: BREAK instruction interpretation corrections Add the missing microMIPS BREAK16 instruction code interpretation and reshape code removing instruction fetching duplication and the separate call to `do_trap_or_bp' in the MIPS16 path. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9696/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:26:27 -06:00
u16 instr[2];
if (__get_user(instr[0], (u16 __user *)epc))
goto out_sigsegv;
if (!cpu_has_mmips) {
MIPS: kernel: traps: Whitespace clean up Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2013-12-04 09:20:08 -07:00
/* MIPS16e mode */
MIPS: Correct MIPS16 BREAK code interpretation Correct the interpretation of the immediate MIPS16 BREAK instruction code embedded in the instruction word across bits 10:5 rather than 11:6 as current code implies, fixing the interpretation of integer overflow and divide by zero traps. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9695/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:26:21 -06:00
bcode = (instr[0] >> 5) & 0x3f;
MIPS: BREAK instruction interpretation corrections Add the missing microMIPS BREAK16 instruction code interpretation and reshape code removing instruction fetching duplication and the separate call to `do_trap_or_bp' in the MIPS16 path. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9696/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:26:27 -06:00
} else if (mm_insn_16bit(instr[0])) {
/* 16-bit microMIPS BREAK */
bcode = instr[0] & 0xf;
} else {
/* 32-bit microMIPS BREAK */
if (__get_user(instr[1], (u16 __user *)(epc + 2)))
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
goto out_sigsegv;
MIPS: BREAK instruction interpretation corrections Add the missing microMIPS BREAK16 instruction code interpretation and reshape code removing instruction fetching duplication and the separate call to `do_trap_or_bp' in the MIPS16 path. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9696/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:26:27 -06:00
opcode = (instr[0] << 16) | instr[1];
bcode = (opcode >> 6) & ((1 << 20) - 1);
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
}
} else {
MIPS: BREAK instruction interpretation corrections Add the missing microMIPS BREAK16 instruction code interpretation and reshape code removing instruction fetching duplication and the separate call to `do_trap_or_bp' in the MIPS16 path. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9696/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:26:27 -06:00
if (__get_user(opcode, (unsigned int __user *)epc))
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
goto out_sigsegv;
MIPS: BREAK instruction interpretation corrections Add the missing microMIPS BREAK16 instruction code interpretation and reshape code removing instruction fetching duplication and the separate call to `do_trap_or_bp' in the MIPS16 path. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9696/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:26:27 -06:00
bcode = (opcode >> 6) & ((1 << 20) - 1);
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
}
[MIPS] Fix handling of trap and breakpoint instructions With fixes and cleanups from Atsushi Nemoto (anemo@mba.ocn.ne.jp). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-20 09:28:54 -06:00
/*
* There is the ancient bug in the MIPS assemblers that the break
* code starts left to bit 16 instead to bit 6 in the opcode.
* Gas is bug-compatible, but not always, grrr...
* We handle both cases with a simple heuristics. --macro
*/
if (bcode >= (1 << 10))
MIPS: Fix BREAK code interpretation heuristics Do not lose the other half of the BREAK code where there is an upper half. This is so that e.g. `BREAK 7, 7' is not interpreted as a divide by zero trap, while `BREAK 0, 7' or `BREAK 7, 0' still are. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9697/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:26:32 -06:00
bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
[MIPS] Fix handling of trap and breakpoint instructions With fixes and cleanups from Atsushi Nemoto (anemo@mba.ocn.ne.jp). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-20 09:28:54 -06:00
MIPS: kprobe: Add support. This patch is based on previous work by Sony and Himanshu Chauhan. I have done some cleanup and implemented JProbes and KRETPROBES. The KRETPROBES part is pretty much copied verbatim from powerpc. A possible future enhance might be to factor out the common code. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: Himanshu Chauhan <hschauhan@nulltrace.org> To: linux-mips@linux-mips.org To: ananth@in.ibm.com, To: anil.s.keshavamurthy@intel.com To: davem@davemloft.net To: masami.hiramatsu.pt@hitachi.com Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1525/ Patchwork: https://patchwork.linux-mips.org/patch/1530/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-03 12:22:20 -06:00
/*
* notify the kprobe handlers, if instruction is likely to
* pertain to them.
*/
switch (bcode) {
MIPS: Add uprobes support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-29 14:44:53 -06:00
case BRK_UPROBE:
if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
goto out;
else
break;
case BRK_UPROBE_XOL:
if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
goto out;
else
break;
MIPS: kprobe: Add support. This patch is based on previous work by Sony and Himanshu Chauhan. I have done some cleanup and implemented JProbes and KRETPROBES. The KRETPROBES part is pretty much copied verbatim from powerpc. A possible future enhance might be to factor out the common code. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: Himanshu Chauhan <hschauhan@nulltrace.org> To: linux-mips@linux-mips.org To: ananth@in.ibm.com, To: anil.s.keshavamurthy@intel.com To: davem@davemloft.net To: masami.hiramatsu.pt@hitachi.com Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1525/ Patchwork: https://patchwork.linux-mips.org/patch/1530/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-03 12:22:20 -06:00
case BRK_KPROBE_BP:
MIPS: traps: Reformat notify_die invocations to 80 columns. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-10-09 00:54:15 -06:00
if (notify_die(DIE_BREAK, "debug", regs, bcode,
MIPS: Set trap_no field in thread_struct on exception. This reverts commit 7281cd22973008a782860e48ed8d85d00204168c and adds actual functionality to use the field.
2015-07-28 12:37:43 -06:00
current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
goto out;
MIPS: kprobe: Add support. This patch is based on previous work by Sony and Himanshu Chauhan. I have done some cleanup and implemented JProbes and KRETPROBES. The KRETPROBES part is pretty much copied verbatim from powerpc. A possible future enhance might be to factor out the common code. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: Himanshu Chauhan <hschauhan@nulltrace.org> To: linux-mips@linux-mips.org To: ananth@in.ibm.com, To: anil.s.keshavamurthy@intel.com To: davem@davemloft.net To: masami.hiramatsu.pt@hitachi.com Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1525/ Patchwork: https://patchwork.linux-mips.org/patch/1530/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-03 12:22:20 -06:00
else
break;
case BRK_KPROBE_SSTEPBP:
MIPS: traps: Reformat notify_die invocations to 80 columns. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-10-09 00:54:15 -06:00
if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
MIPS: Set trap_no field in thread_struct on exception. This reverts commit 7281cd22973008a782860e48ed8d85d00204168c and adds actual functionality to use the field.
2015-07-28 12:37:43 -06:00
current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
goto out;
MIPS: kprobe: Add support. This patch is based on previous work by Sony and Himanshu Chauhan. I have done some cleanup and implemented JProbes and KRETPROBES. The KRETPROBES part is pretty much copied verbatim from powerpc. A possible future enhance might be to factor out the common code. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: Himanshu Chauhan <hschauhan@nulltrace.org> To: linux-mips@linux-mips.org To: ananth@in.ibm.com, To: anil.s.keshavamurthy@intel.com To: davem@davemloft.net To: masami.hiramatsu.pt@hitachi.com Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1525/ Patchwork: https://patchwork.linux-mips.org/patch/1530/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-08-03 12:22:20 -06:00
else
break;
default:
break;
}
MIPS: traps: Correct the SIGTRAP debug ABI in `do_watch' and `do_trap_or_bp' Follow our own rules set in <asm/siginfo.h> for SIGTRAP signals issued from `do_watch' and `do_trap_or_bp' by setting the signal code to TRAP_HWBKPT and TRAP_BRKPT respectively, for Watch exceptions and for those Breakpoint exceptions whose originating BREAK instruction's code does not have a special meaning. Keep Trap exceptions unaffected as these are not debug events. No existing user software is expected to examine signal codes for these signals as SI_KERNEL has been always used here. This change makes the MIPS port more like other Linux ports, which reduces the complexity and provides for performance improvement in GDB. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Pedro Alves <palves@redhat.com> Cc: Luis Machado <lgustavo@codesourcery.com> Cc: linux-mips@linux-mips.org Cc: gdb@sourceware.org Patchwork: https://patchwork.linux-mips.org/patch/12758/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-03-03 18:44:28 -07:00
do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
out:
MIPS: traps: Set correct address limit for breakpoints and traps When a breakpoint or trap happens when operating in kernel mode but on users behalf (eg syscall) it is necessary to change the address limit to KERNEL_DS so any address checking can be bypassed and print the correct stack trace. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2013-12-04 09:39:34 -07:00
set_fs(seg);
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
exception_exit(prev_state);
[MIPS] Fix double signal on trap and break instruction This commit broke gdb, since any BREAK or TRAP instruction cause SIGSEGV. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06 00:02:21 -07:00
return;
[MIPS] Work around bogus gcc warnings. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-29 18:14:47 -07:00
out_sigsegv:
force_sig(SIGSEGV, current);
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
goto out;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
asmlinkage void do_tr(struct pt_regs *regs)
{
MIPS: Trap exception handling fixes 2a0b24f56c2492b932f1aed617ae80fb23500d21 broke Trap exception handling in the standard MIPS mode. Additionally the microMIPS-mode trap code mask is wrong, as it's a 4-bit field. Here's a fix. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5309/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-23 08:31:23 -06:00
u32 opcode, tcode = 0;
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
enum ctx_state prev_state;
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
u16 instr[2];
MIPS: traps: Set correct address limit for breakpoints and traps When a breakpoint or trap happens when operating in kernel mode but on users behalf (eg syscall) it is necessary to change the address limit to KERNEL_DS so any address checking can be bypassed and print the correct stack trace. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2013-12-04 09:39:34 -07:00
mm_segment_t seg;
MIPS: Trap exception handling fixes 2a0b24f56c2492b932f1aed617ae80fb23500d21 broke Trap exception handling in the standard MIPS mode. Additionally the microMIPS-mode trap code mask is wrong, as it's a 4-bit field. Here's a fix. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5309/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-23 08:31:23 -06:00
unsigned long epc = msk_isa16_mode(exception_epc(regs));
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: traps: Set correct address limit for breakpoints and traps When a breakpoint or trap happens when operating in kernel mode but on users behalf (eg syscall) it is necessary to change the address limit to KERNEL_DS so any address checking can be bypassed and print the correct stack trace. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2013-12-04 09:39:34 -07:00
seg = get_fs();
if (!user_mode(regs))
get rid of legacy 'get_ds()' function Every in-kernel use of this function defined it to KERNEL_DS (either as an actual define, or as an inline function). It's an entirely historical artifact, and long long long ago used to actually read the segment selector valueof '%ds' on x86. Which in the kernel is always KERNEL_DS. Inspired by a patch from Jann Horn that just did this for a very small subset of users (the ones in fs/), along with Al who suggested a script. I then just took it to the logical extreme and removed all the remaining gunk. Roughly scripted with git grep -l '(get_ds())' -- :^tools/ | xargs sed -i 's/(get_ds())/(KERNEL_DS)/' git grep -lw 'get_ds' -- :^tools/ | xargs sed -i '/^#define get_ds()/d' plus manual fixups to remove a few unusual usage patterns, the couple of inline function cases and to fix up a comment that had become stale. The 'get_ds()' function remains in an x86 kvm selftest, since in user space it actually does something relevant. Inspired-by: Jann Horn <jannh@google.com> Inspired-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2019-03-04 11:39:05 -07:00
set_fs(KERNEL_DS);
MIPS: traps: Set correct address limit for breakpoints and traps When a breakpoint or trap happens when operating in kernel mode but on users behalf (eg syscall) it is necessary to change the address limit to KERNEL_DS so any address checking can be bypassed and print the correct stack trace. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2013-12-04 09:39:34 -07:00
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
prev_state = exception_enter();
MIPS: Set trap_no field in thread_struct on exception. This reverts commit 7281cd22973008a782860e48ed8d85d00204168c and adds actual functionality to use the field.
2015-07-28 12:37:43 -06:00
current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
MIPS: Trap exception handling fixes 2a0b24f56c2492b932f1aed617ae80fb23500d21 broke Trap exception handling in the standard MIPS mode. Additionally the microMIPS-mode trap code mask is wrong, as it's a 4-bit field. Here's a fix. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5309/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-23 08:31:23 -06:00
if (get_isa16_mode(regs->cp0_epc)) {
if (__get_user(instr[0], (u16 __user *)(epc + 0)) ||
__get_user(instr[1], (u16 __user *)(epc + 2)))
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
goto out_sigsegv;
MIPS: Trap exception handling fixes 2a0b24f56c2492b932f1aed617ae80fb23500d21 broke Trap exception handling in the standard MIPS mode. Additionally the microMIPS-mode trap code mask is wrong, as it's a 4-bit field. Here's a fix. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5309/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-23 08:31:23 -06:00
opcode = (instr[0] << 16) | instr[1];
/* Immediate versions don't provide a code. */
if (!(opcode & OPCODE))
tcode = (opcode >> 12) & ((1 << 4) - 1);
} else {
if (__get_user(opcode, (u32 __user *)epc))
goto out_sigsegv;
/* Immediate versions don't provide a code. */
if (!(opcode & OPCODE))
tcode = (opcode >> 6) & ((1 << 10) - 1);
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: traps: Correct the SIGTRAP debug ABI in `do_watch' and `do_trap_or_bp' Follow our own rules set in <asm/siginfo.h> for SIGTRAP signals issued from `do_watch' and `do_trap_or_bp' by setting the signal code to TRAP_HWBKPT and TRAP_BRKPT respectively, for Watch exceptions and for those Breakpoint exceptions whose originating BREAK instruction's code does not have a special meaning. Keep Trap exceptions unaffected as these are not debug events. No existing user software is expected to examine signal codes for these signals as SI_KERNEL has been always used here. This change makes the MIPS port more like other Linux ports, which reduces the complexity and provides for performance improvement in GDB. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Pedro Alves <palves@redhat.com> Cc: Luis Machado <lgustavo@codesourcery.com> Cc: linux-mips@linux-mips.org Cc: gdb@sourceware.org Patchwork: https://patchwork.linux-mips.org/patch/12758/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-03-03 18:44:28 -07:00
do_trap_or_bp(regs, tcode, 0, "Trap");
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
out:
MIPS: traps: Set correct address limit for breakpoints and traps When a breakpoint or trap happens when operating in kernel mode but on users behalf (eg syscall) it is necessary to change the address limit to KERNEL_DS so any address checking can be bypassed and print the correct stack trace. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2013-12-04 09:39:34 -07:00
set_fs(seg);
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
exception_exit(prev_state);
[MIPS] Fix double signal on trap and break instruction This commit broke gdb, since any BREAK or TRAP instruction cause SIGSEGV. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-02-06 00:02:21 -07:00
return;
[MIPS] Work around bogus gcc warnings. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-29 18:14:47 -07:00
out_sigsegv:
force_sig(SIGSEGV, current);
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
goto out;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
asmlinkage void do_ri(struct pt_regs *regs)
{
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
unsigned long old_epc = regs->cp0_epc;
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
unsigned long old31 = regs->regs[31];
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
enum ctx_state prev_state;
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
unsigned int opcode = 0;
int status = -1;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6 MIPS R6 removed quite a few R2 instructions. However, there is plenty of <R6 userland code so we add an in-kernel emulator so we can still be able to execute all R2 userland out there. The emulator comes with a handy debugfs under /mips/ directory (r2-emul-stats) to provide some basic statistics of the instructions that are being emulated. Below are some statistics from booting a minimal buildroot image: Instruction Total BDslot ------------------------------ movs 236969 0 hilo 56686 0 muls 55279 0 divs 10941 0 dsps 0 0 bops 1 0 traps 0 0 fpus 0 0 loads 214981 17 stores 103364 0 llsc 56898 0 dsemul 150418 0 jr 370158 bltzl 43 bgezl 1594 bltzll 0 bgezll 0 bltzal 39 bgezal 39 beql 14503 bnel 138741 blezl 0 bgtzl 3988 Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-12-03 08:47:03 -07:00
/*
* Avoid any kernel code. Just emulate the R2 instruction
* as quickly as possible.
*/
if (mipsr2_emulation && cpu_has_mips_r6 &&
MIPS: Reindent R6 RI exception emulation Fold a nested `if' statement for the R6 case in `do_ri' into its containing `if' block, removing excessive indentation causing code to extend beyond 79 columns. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9679/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:24:51 -06:00
likely(user_mode(regs)) &&
likely(get_user(opcode, epc) >= 0)) {
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
unsigned long fcr31 = 0;
status = mipsr2_decoder(regs, opcode, &fcr31);
MIPS: Reindent R6 RI exception emulation Fold a nested `if' statement for the R6 case in `do_ri' into its containing `if' block, removing excessive indentation causing code to extend beyond 79 columns. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9679/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:24:51 -06:00
switch (status) {
case 0:
case SIGEMT:
return;
case SIGILL:
goto no_r2_instr;
default:
process_fpemu_return(status,
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
&current->thread.cp0_baduaddr,
fcr31);
MIPS: Reindent R6 RI exception emulation Fold a nested `if' statement for the R6 case in `do_ri' into its containing `if' block, removing excessive indentation causing code to extend beyond 79 columns. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9679/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:24:51 -06:00
return;
MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6 MIPS R6 removed quite a few R2 instructions. However, there is plenty of <R6 userland code so we add an in-kernel emulator so we can still be able to execute all R2 userland out there. The emulator comes with a handy debugfs under /mips/ directory (r2-emul-stats) to provide some basic statistics of the instructions that are being emulated. Below are some statistics from booting a minimal buildroot image: Instruction Total BDslot ------------------------------ movs 236969 0 hilo 56686 0 muls 55279 0 divs 10941 0 dsps 0 0 bops 1 0 traps 0 0 fpus 0 0 loads 214981 17 stores 103364 0 llsc 56898 0 dsemul 150418 0 jr 370158 bltzl 43 bgezl 1594 bltzll 0 bgezll 0 bltzal 39 bgezal 39 beql 14503 bnel 138741 blezl 0 bgtzl 3988 Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-12-03 08:47:03 -07:00
}
}
no_r2_instr:
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
prev_state = exception_enter();
MIPS: Set trap_no field in thread_struct on exception. This reverts commit 7281cd22973008a782860e48ed8d85d00204168c and adds actual functionality to use the field.
2015-07-28 12:37:43 -06:00
current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6 MIPS R6 removed quite a few R2 instructions. However, there is plenty of <R6 userland code so we add an in-kernel emulator so we can still be able to execute all R2 userland out there. The emulator comes with a handy debugfs under /mips/ directory (r2-emul-stats) to provide some basic statistics of the instructions that are being emulated. Below are some statistics from booting a minimal buildroot image: Instruction Total BDslot ------------------------------ movs 236969 0 hilo 56686 0 muls 55279 0 divs 10941 0 dsps 0 0 bops 1 0 traps 0 0 fpus 0 0 loads 214981 17 stores 103364 0 llsc 56898 0 dsemul 150418 0 jr 370158 bltzl 43 bgezl 1594 bltzll 0 bgezll 0 bltzal 39 bgezal 39 beql 14503 bnel 138741 blezl 0 bgtzl 3988 Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-12-03 08:47:03 -07:00
MIPS: Set trap_no field in thread_struct on exception. This reverts commit 7281cd22973008a782860e48ed8d85d00204168c and adds actual functionality to use the field.
2015-07-28 12:37:43 -06:00
if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
MIPS: traps: Reformat notify_die invocations to 80 columns. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-10-09 00:54:15 -06:00
SIGILL) == NOTIFY_STOP)
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
goto out;
[MIPS] kgdb: add arch support for the kernel's kgdb core The new kgdb architecture specific handler registers and unregisters dynamically for exceptions depending on when you configure a kgdb I/O driver. Aside from initializing the exceptions earlier in the boot process, kgdb should have no impact on a device when it is compiled in so long as an I/O module is not configured for use. There have been quite a number of contributors during the existence of this patch (see arch/mips/kernel/kgdb.c). Most recently Jason re-wrote the mips kgdb logic to use the die notification handlers. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-07-29 14:58:53 -06:00
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
die_if_kernel("Reserved instruction in kernel code", regs);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
if (unlikely(compute_return_epc(regs) < 0))
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
goto out;
NPTL, round one. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-04-13 11:43:59 -06:00
MIPS: traps.c: Verify the ISA for microMIPS RDHWR emulation Make sure it's the microMIPS rather than MIPS16 ISA before emulating microMIPS RDHWR. Mostly needed as an optimisation for configurations where `cpu_has_mmips' is hardcoded to 0 and also a good measure in case we add further microMIPS instructions to emulate in the future, as the corresponding MIPS16 encoding is ADDIUSP, not supposed to trap. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12282/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-30 02:08:43 -07:00
if (!get_isa16_mode(regs->cp0_epc)) {
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
if (unlikely(get_user(opcode, epc) < 0))
status = SIGSEGV;
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
if (!cpu_has_llsc && status < 0)
status = simulate_llsc(regs, opcode);
if (status < 0)
status = simulate_rdhwr_normal(regs, opcode);
if (status < 0)
status = simulate_sync(regs, opcode);
MIPS: Support for hybrid FPRs Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but accesses to odd indexed single registers use bits 63:32 of the preceeding even indexed 64b register. In this mode all FP code except that built for the plain FP64 ABI can execute correctly. Most notably a combination of FP64A & FP32 code can execute correctly, allowing for existing FP32 binaries to be linked with new FP64A binaries that can make use of 64 bit FP & MSA. Hybrid FPRs are implemented by setting both the FR & FRE bits, trapping & emulating single precision FP instructions (via Reserved Instruction exceptions) whilst allowing others to execute natively. It therefore has a penalty in terms of execution speed, and should only be used when no fully native mode can be. As more binaries are recompiled to use either the FPXX or FP64(A) ABIs, the need for hybrid FPRs should diminish. However in the short to mid term it allows for a gradual transition towards that world, rather than a complete ABI break which is not feasible for some users & not desirable for many. A task will be executed using the hybrid FPR scheme when its TIF_HYBRID_FPREGS flag is set & TIF_32BIT_FPREGS is clear. A further patch will set the flags as necessary, this patch simply adds the infrastructure necessary for the hybrid FPR mode to work. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-09-11 01:30:20 -06:00
if (status < 0)
status = simulate_fp(regs, opcode, old_epc, old31);
MIPS: traps.c: Verify the ISA for microMIPS RDHWR emulation Make sure it's the microMIPS rather than MIPS16 ISA before emulating microMIPS RDHWR. Mostly needed as an optimisation for configurations where `cpu_has_mmips' is hardcoded to 0 and also a good measure in case we add further microMIPS instructions to emulate in the future, as the corresponding MIPS16 encoding is ADDIUSP, not supposed to trap. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12282/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-30 02:08:43 -07:00
} else if (cpu_has_mmips) {
unsigned short mmop[2] = { 0 };
if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
status = SIGSEGV;
if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
status = SIGSEGV;
opcode = mmop[0];
opcode = (opcode << 16) | mmop[1];
if (status < 0)
status = simulate_rdhwr_mm(regs, opcode);
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
}
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
if (status < 0)
status = SIGILL;
if (unlikely(status > 0)) {
regs->cp0_epc = old_epc; /* Undo skip-over. */
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
regs->regs[31] = old31;
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
force_sig(status, current);
}
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
out:
exception_exit(prev_state);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
MIPS: Modularize COP2 handling Away with the daemons of ifdef; get ready for future COP2 users. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/708/
2009-11-23 18:24:58 -07:00
/*
* No lock; only written during early bootup by CPU 0.
*/
static RAW_NOTIFIER_HEAD(cu2_chain);
int __ref register_cu2_notifier(struct notifier_block *nb)
{
return raw_notifier_chain_register(&cu2_chain, nb);
}
int cu2_notifier_call_chain(unsigned long val, void *v)
{
return raw_notifier_call_chain(&cu2_chain, val, v);
}
static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
MIPS: Whitespace cleanup. Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-01-22 04:59:30 -07:00
void *data)
MIPS: Modularize COP2 handling Away with the daemons of ifdef; get ready for future COP2 users. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/708/
2009-11-23 18:24:58 -07:00
{
struct pt_regs *regs = data;
MIPS: Allow kernel to use coprocessor 2 Kernel threads should be able to use COP2 if the platform needs it. Do not call die_if_kernel() for a coprocessor unusable exception if the exception due to COP2 usage. Instead, the default notifier for COP2 exceptions is updated to call die_if_kernel. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5415/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-10 00:30:01 -06:00
die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
MIPS: Modularize COP2 handling Away with the daemons of ifdef; get ready for future COP2 users. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/708/
2009-11-23 18:24:58 -07:00
"instruction", regs);
MIPS: Allow kernel to use coprocessor 2 Kernel threads should be able to use COP2 if the platform needs it. Do not call die_if_kernel() for a coprocessor unusable exception if the exception due to COP2 usage. Instead, the default notifier for COP2 exceptions is updated to call die_if_kernel. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5415/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-10 00:30:01 -06:00
force_sig(SIGILL, current);
MIPS: Modularize COP2 handling Away with the daemons of ifdef; get ready for future COP2 users. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/708/
2009-11-23 18:24:58 -07:00
return NOTIFY_OK;
}
MIPS: traps: Never enable FPU when CONFIG_MIPS_FP_SUPPORT=n When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so we'll never need to enable the FPU. Avoid doing so on a Co-Processor Unusable exception (do_cpu), and remove the Floating Point Exception handler (do_fpe) which should never be executed when the FPU is disabled. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21007/ Cc: linux-mips@linux-mips.org
2018-11-07 16:14:05 -07:00
#ifdef CONFIG_MIPS_FP_SUPPORT
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:11 -07:00
static int enable_restore_fp_context(int msa)
{
MIPS: init upper 64b of vector registers when MSA is first used When a task first makes use of MSA we need to ensure that the upper 64b of the vector registers are set to some value such that no information can be leaked to it from the previous task to use MSA context on the CPU. The architecture formerly specified that these bits would be cleared to 0 when a scalar FP instructions wrote to the aliased FP registers, which would have implicitly handled this as the kernel restored scalar FP context. However more recent versions of the specification now state that the value of the bits in such cases is unpredictable. Initialise them explictly to be sure, and set all the bits to 1 rather than 0 for consistency with the least significant 64b. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30 01:53:20 -06:00
int err, was_fpu_owner, prior_msa;
MIPS: Simplify FP context initialization MIPS has up until now had 3 different ways for a task's floating point context to be initialized: - If the task's first use of FP involves it gaining ownership of an FPU then _init_fpu() is used to initialize the FPU's registers such that they all contain ~0, and the FPU registers will be stored to struct thread_info later (eg. when context switching). - If the task first uses FP on a CPU without an associated FPU then fpu_emulator_init_fpu() initializes the task's floating point register state in struct thread_info such that all floating point register contain the bit pattern 0x7ff800007ff80000, different to the _init_fpu() behaviour. - If a task's floating point context is first accessed via ptrace then init_fp_ctx() initializes the floating point register state in struct thread_info to ~0, giving equivalent state to _init_fpu(). The _init_fpu() path has 2 separate implementations - one for r2k/r3k style systems & one for r4k style systems. The _init_fpu() path also requires that we be careful to clear & restore the value of the Config5.FRE bit on modern systems in order to avoid inadvertently triggering floating point exceptions. None of this code is in a performance critical hot path - it runs only the first time a task uses floating point. As such it doesn't seem to warrant the complications of maintaining the _init_fpu() path. Remove _init_fpu() & fpu_emulator_init_fpu(), instead using init_fp_ctx() consistently to initialize floating point register state in struct thread_info. Upon a task's first use of floating point this will typically mean that we initialize state in memory & then load it into FPU registers using _restore_fp() just as we would on a context switch. For other paths such as __compute_return_epc_for_insn() or mipsr2_decoder() this results in a significant simplification of the work to be done. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21002/ Cc: linux-mips@linux-mips.org
2018-11-07 16:13:59 -07:00
bool first_fp;
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:11 -07:00
MIPS: Simplify FP context initialization MIPS has up until now had 3 different ways for a task's floating point context to be initialized: - If the task's first use of FP involves it gaining ownership of an FPU then _init_fpu() is used to initialize the FPU's registers such that they all contain ~0, and the FPU registers will be stored to struct thread_info later (eg. when context switching). - If the task first uses FP on a CPU without an associated FPU then fpu_emulator_init_fpu() initializes the task's floating point register state in struct thread_info such that all floating point register contain the bit pattern 0x7ff800007ff80000, different to the _init_fpu() behaviour. - If a task's floating point context is first accessed via ptrace then init_fp_ctx() initializes the floating point register state in struct thread_info to ~0, giving equivalent state to _init_fpu(). The _init_fpu() path has 2 separate implementations - one for r2k/r3k style systems & one for r4k style systems. The _init_fpu() path also requires that we be careful to clear & restore the value of the Config5.FRE bit on modern systems in order to avoid inadvertently triggering floating point exceptions. None of this code is in a performance critical hot path - it runs only the first time a task uses floating point. As such it doesn't seem to warrant the complications of maintaining the _init_fpu() path. Remove _init_fpu() & fpu_emulator_init_fpu(), instead using init_fp_ctx() consistently to initialize floating point register state in struct thread_info. Upon a task's first use of floating point this will typically mean that we initialize state in memory & then load it into FPU registers using _restore_fp() just as we would on a context switch. For other paths such as __compute_return_epc_for_insn() or mipsr2_decoder() this results in a significant simplification of the work to be done. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21002/ Cc: linux-mips@linux-mips.org
2018-11-07 16:13:59 -07:00
/* Initialize context if it hasn't been used already */
first_fp = init_fp_ctx(current);
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:11 -07:00
MIPS: Simplify FP context initialization MIPS has up until now had 3 different ways for a task's floating point context to be initialized: - If the task's first use of FP involves it gaining ownership of an FPU then _init_fpu() is used to initialize the FPU's registers such that they all contain ~0, and the FPU registers will be stored to struct thread_info later (eg. when context switching). - If the task first uses FP on a CPU without an associated FPU then fpu_emulator_init_fpu() initializes the task's floating point register state in struct thread_info such that all floating point register contain the bit pattern 0x7ff800007ff80000, different to the _init_fpu() behaviour. - If a task's floating point context is first accessed via ptrace then init_fp_ctx() initializes the floating point register state in struct thread_info to ~0, giving equivalent state to _init_fpu(). The _init_fpu() path has 2 separate implementations - one for r2k/r3k style systems & one for r4k style systems. The _init_fpu() path also requires that we be careful to clear & restore the value of the Config5.FRE bit on modern systems in order to avoid inadvertently triggering floating point exceptions. None of this code is in a performance critical hot path - it runs only the first time a task uses floating point. As such it doesn't seem to warrant the complications of maintaining the _init_fpu() path. Remove _init_fpu() & fpu_emulator_init_fpu(), instead using init_fp_ctx() consistently to initialize floating point register state in struct thread_info. Upon a task's first use of floating point this will typically mean that we initialize state in memory & then load it into FPU registers using _restore_fp() just as we would on a context switch. For other paths such as __compute_return_epc_for_insn() or mipsr2_decoder() this results in a significant simplification of the work to be done. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21002/ Cc: linux-mips@linux-mips.org
2018-11-07 16:13:59 -07:00
if (first_fp) {
MIPS: disable preemption whilst initialising MSA Preemption must be disabled throughout the process of enabling the FPU, enabling MSA & initialising the vector registers. Without doing so it is possible to lose the FPU or MSA whilst initialising them causing that initialisation to fail. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7307/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-11 09:44:35 -06:00
preempt_disable();
MIPS: Simplify FP context initialization MIPS has up until now had 3 different ways for a task's floating point context to be initialized: - If the task's first use of FP involves it gaining ownership of an FPU then _init_fpu() is used to initialize the FPU's registers such that they all contain ~0, and the FPU registers will be stored to struct thread_info later (eg. when context switching). - If the task first uses FP on a CPU without an associated FPU then fpu_emulator_init_fpu() initializes the task's floating point register state in struct thread_info such that all floating point register contain the bit pattern 0x7ff800007ff80000, different to the _init_fpu() behaviour. - If a task's floating point context is first accessed via ptrace then init_fp_ctx() initializes the floating point register state in struct thread_info to ~0, giving equivalent state to _init_fpu(). The _init_fpu() path has 2 separate implementations - one for r2k/r3k style systems & one for r4k style systems. The _init_fpu() path also requires that we be careful to clear & restore the value of the Config5.FRE bit on modern systems in order to avoid inadvertently triggering floating point exceptions. None of this code is in a performance critical hot path - it runs only the first time a task uses floating point. As such it doesn't seem to warrant the complications of maintaining the _init_fpu() path. Remove _init_fpu() & fpu_emulator_init_fpu(), instead using init_fp_ctx() consistently to initialize floating point register state in struct thread_info. Upon a task's first use of floating point this will typically mean that we initialize state in memory & then load it into FPU registers using _restore_fp() just as we would on a context switch. For other paths such as __compute_return_epc_for_insn() or mipsr2_decoder() this results in a significant simplification of the work to be done. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21002/ Cc: linux-mips@linux-mips.org
2018-11-07 16:13:59 -07:00
err = own_fpu_inatomic(1);
MIPS: init upper 64b of vector registers when MSA is first used When a task first makes use of MSA we need to ensure that the upper 64b of the vector registers are set to some value such that no information can be leaked to it from the previous task to use MSA context on the CPU. The architecture formerly specified that these bits would be cleared to 0 when a scalar FP instructions wrote to the aliased FP registers, which would have implicitly handled this as the kernel restored scalar FP context. However more recent versions of the specification now state that the value of the bits in such cases is unpredictable. Initialise them explictly to be sure, and set all the bits to 1 rather than 0 for consistency with the least significant 64b. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30 01:53:20 -06:00
if (msa && !err) {
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:11 -07:00
enable_msa();
MIPS: fix MSA context for tasks which don't use FP first If a task does not execute scalar FP instructions prior to using MSA then the flags indicating that the task has live MSA context were not being set. The upper 64b of each vector register would then be lost upon the tasks first context switch after using MSA. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7500/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-31 07:53:16 -06:00
set_thread_flag(TIF_USEDMSA);
set_thread_flag(TIF_MSA_CTX_LIVE);
MIPS: init upper 64b of vector registers when MSA is first used When a task first makes use of MSA we need to ensure that the upper 64b of the vector registers are set to some value such that no information can be leaked to it from the previous task to use MSA context on the CPU. The architecture formerly specified that these bits would be cleared to 0 when a scalar FP instructions wrote to the aliased FP registers, which would have implicitly handled this as the kernel restored scalar FP context. However more recent versions of the specification now state that the value of the bits in such cases is unpredictable. Initialise them explictly to be sure, and set all the bits to 1 rather than 0 for consistency with the least significant 64b. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30 01:53:20 -06:00
}
MIPS: disable preemption whilst initialising MSA Preemption must be disabled throughout the process of enabling the FPU, enabling MSA & initialising the vector registers. Without doing so it is possible to lose the FPU or MSA whilst initialising them causing that initialisation to fail. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7307/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-11 09:44:35 -06:00
preempt_enable();
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:11 -07:00
return err;
}
/*
* This task has formerly used the FP context.
*
* If this thread has no live MSA vector context then we can simply
* restore the scalar FP context. If it has live MSA vector context
* (that is, it has or may have used MSA since last performing a
* function call) then we'll need to restore the vector context. This
* applies even if we're currently only executing a scalar FP
* instruction. This is because if we were to later execute an MSA
* instruction then we'd either have to:
*
* - Restore the vector context & clobber any registers modified by
* scalar FP instructions between now & then.
*
* or
*
* - Not restore the vector context & lose the most significant bits
* of all vector registers.
*
* Neither of those options is acceptable. We cannot restore the least
* significant bits of the registers now & only restore the most
* significant bits later because the most significant bits of any
* vector registers whose aliased FP register is modified now will have
* been zeroed. We'd have no way to know that when restoring the vector
* context & thus may load an outdated value for the most significant
* bits of a vector register.
*/
if (!msa && !thread_msa_context_live())
return own_fpu(1);
/*
* This task is using or has previously used MSA. Thus we require
* that Status.FR == 1.
*/
MIPS: disable preemption whilst initialising MSA Preemption must be disabled throughout the process of enabling the FPU, enabling MSA & initialising the vector registers. Without doing so it is possible to lose the FPU or MSA whilst initialising them causing that initialisation to fail. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7307/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-11 09:44:35 -06:00
preempt_disable();
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:11 -07:00
was_fpu_owner = is_fpu_owner();
MIPS: disable preemption whilst initialising MSA Preemption must be disabled throughout the process of enabling the FPU, enabling MSA & initialising the vector registers. Without doing so it is possible to lose the FPU or MSA whilst initialising them causing that initialisation to fail. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7307/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-11 09:44:35 -06:00
err = own_fpu_inatomic(0);
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:11 -07:00
if (err)
MIPS: disable preemption whilst initialising MSA Preemption must be disabled throughout the process of enabling the FPU, enabling MSA & initialising the vector registers. Without doing so it is possible to lose the FPU or MSA whilst initialising them causing that initialisation to fail. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7307/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-11 09:44:35 -06:00
goto out;
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:11 -07:00
enable_msa();
write_msa_csr(current->thread.fpu.msacsr);
set_thread_flag(TIF_USEDMSA);
/*
* If this is the first time that the task is using MSA and it has
* previously used scalar FP in this time slice then we already nave
MIPS: init upper 64b of vector registers when MSA is first used When a task first makes use of MSA we need to ensure that the upper 64b of the vector registers are set to some value such that no information can be leaked to it from the previous task to use MSA context on the CPU. The architecture formerly specified that these bits would be cleared to 0 when a scalar FP instructions wrote to the aliased FP registers, which would have implicitly handled this as the kernel restored scalar FP context. However more recent versions of the specification now state that the value of the bits in such cases is unpredictable. Initialise them explictly to be sure, and set all the bits to 1 rather than 0 for consistency with the least significant 64b. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30 01:53:20 -06:00
* FP context which we shouldn't clobber. We do however need to clear
* the upper 64b of each vector register so that this task has no
* opportunity to see data left behind by another.
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:11 -07:00
*/
MIPS: init upper 64b of vector registers when MSA is first used When a task first makes use of MSA we need to ensure that the upper 64b of the vector registers are set to some value such that no information can be leaked to it from the previous task to use MSA context on the CPU. The architecture formerly specified that these bits would be cleared to 0 when a scalar FP instructions wrote to the aliased FP registers, which would have implicitly handled this as the kernel restored scalar FP context. However more recent versions of the specification now state that the value of the bits in such cases is unpredictable. Initialise them explictly to be sure, and set all the bits to 1 rather than 0 for consistency with the least significant 64b. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30 01:53:20 -06:00
prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
if (!prior_msa && was_fpu_owner) {
MIPS: MSA: Fix a link error on `_init_msa_upper' with older GCC Fix a build regression from commit c9017757c532 ("MIPS: init upper 64b of vector registers when MSA is first used"): arch/mips/built-in.o: In function `enable_restore_fp_context': traps.c:(.text+0xbb90): undefined reference to `_init_msa_upper' traps.c:(.text+0xbb90): relocation truncated to fit: R_MIPS_26 against `_init_msa_upper' traps.c:(.text+0xbef0): undefined reference to `_init_msa_upper' traps.c:(.text+0xbef0): relocation truncated to fit: R_MIPS_26 against `_init_msa_upper' to !CONFIG_CPU_HAS_MSA configurations with older GCC versions, which are unable to figure out that calls to `_init_msa_upper' are indeed dead. Of the many ways to tackle this failure choose the approach we have already taken in `thread_msa_context_live'. [ralf@linux-mips.org: Drop patch segment to junk file.] Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: stable@vger.kernel.org # v3.16+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13271/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-16 23:12:27 -06:00
init_msa_upper();
MIPS: disable preemption whilst initialising MSA Preemption must be disabled throughout the process of enabling the FPU, enabling MSA & initialising the vector registers. Without doing so it is possible to lose the FPU or MSA whilst initialising them causing that initialisation to fail. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7307/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-11 09:44:35 -06:00
goto out;
MIPS: init upper 64b of vector registers when MSA is first used When a task first makes use of MSA we need to ensure that the upper 64b of the vector registers are set to some value such that no information can be leaked to it from the previous task to use MSA context on the CPU. The architecture formerly specified that these bits would be cleared to 0 when a scalar FP instructions wrote to the aliased FP registers, which would have implicitly handled this as the kernel restored scalar FP context. However more recent versions of the specification now state that the value of the bits in such cases is unpredictable. Initialise them explictly to be sure, and set all the bits to 1 rather than 0 for consistency with the least significant 64b. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30 01:53:20 -06:00
}
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:11 -07:00
MIPS: init upper 64b of vector registers when MSA is first used When a task first makes use of MSA we need to ensure that the upper 64b of the vector registers are set to some value such that no information can be leaked to it from the previous task to use MSA context on the CPU. The architecture formerly specified that these bits would be cleared to 0 when a scalar FP instructions wrote to the aliased FP registers, which would have implicitly handled this as the kernel restored scalar FP context. However more recent versions of the specification now state that the value of the bits in such cases is unpredictable. Initialise them explictly to be sure, and set all the bits to 1 rather than 0 for consistency with the least significant 64b. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30 01:53:20 -06:00
if (!prior_msa) {
/*
* Restore the least significant 64b of each vector register
* from the existing scalar FP context.
*/
_restore_fp(current);
MIPS: preserve scalar FP CSR when switching vector context Switching the vector context implicitly saves & restores the state of the aliased scalar FP data registers, however the scalar FP control & status register is distinct from the MSA control & status register. In order to allow scalar FP to function correctly in programs using MSA, the scalar CSR needs to be saved & restored along with the MSA vector context. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7301/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-11 09:44:29 -06:00
MIPS: init upper 64b of vector registers when MSA is first used When a task first makes use of MSA we need to ensure that the upper 64b of the vector registers are set to some value such that no information can be leaked to it from the previous task to use MSA context on the CPU. The architecture formerly specified that these bits would be cleared to 0 when a scalar FP instructions wrote to the aliased FP registers, which would have implicitly handled this as the kernel restored scalar FP context. However more recent versions of the specification now state that the value of the bits in such cases is unpredictable. Initialise them explictly to be sure, and set all the bits to 1 rather than 0 for consistency with the least significant 64b. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30 01:53:20 -06:00
/*
* The task has not formerly used MSA, so clear the upper 64b
* of each vector register such that it cannot see data left
* behind by another task.
*/
MIPS: MSA: Fix a link error on `_init_msa_upper' with older GCC Fix a build regression from commit c9017757c532 ("MIPS: init upper 64b of vector registers when MSA is first used"): arch/mips/built-in.o: In function `enable_restore_fp_context': traps.c:(.text+0xbb90): undefined reference to `_init_msa_upper' traps.c:(.text+0xbb90): relocation truncated to fit: R_MIPS_26 against `_init_msa_upper' traps.c:(.text+0xbef0): undefined reference to `_init_msa_upper' traps.c:(.text+0xbef0): relocation truncated to fit: R_MIPS_26 against `_init_msa_upper' to !CONFIG_CPU_HAS_MSA configurations with older GCC versions, which are unable to figure out that calls to `_init_msa_upper' are indeed dead. Of the many ways to tackle this failure choose the approach we have already taken in `thread_msa_context_live'. [ralf@linux-mips.org: Drop patch segment to junk file.] Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: stable@vger.kernel.org # v3.16+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13271/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-16 23:12:27 -06:00
init_msa_upper();
MIPS: init upper 64b of vector registers when MSA is first used When a task first makes use of MSA we need to ensure that the upper 64b of the vector registers are set to some value such that no information can be leaked to it from the previous task to use MSA context on the CPU. The architecture formerly specified that these bits would be cleared to 0 when a scalar FP instructions wrote to the aliased FP registers, which would have implicitly handled this as the kernel restored scalar FP context. However more recent versions of the specification now state that the value of the bits in such cases is unpredictable. Initialise them explictly to be sure, and set all the bits to 1 rather than 0 for consistency with the least significant 64b. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30 01:53:20 -06:00
} else {
/* We need to restore the vector context. */
restore_msa(current);
MIPS: preserve scalar FP CSR when switching vector context Switching the vector context implicitly saves & restores the state of the aliased scalar FP data registers, however the scalar FP control & status register is distinct from the MSA control & status register. In order to allow scalar FP to function correctly in programs using MSA, the scalar CSR needs to be saved & restored along with the MSA vector context. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7301/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-11 09:44:29 -06:00
MIPS: init upper 64b of vector registers when MSA is first used When a task first makes use of MSA we need to ensure that the upper 64b of the vector registers are set to some value such that no information can be leaked to it from the previous task to use MSA context on the CPU. The architecture formerly specified that these bits would be cleared to 0 when a scalar FP instructions wrote to the aliased FP registers, which would have implicitly handled this as the kernel restored scalar FP context. However more recent versions of the specification now state that the value of the bits in such cases is unpredictable. Initialise them explictly to be sure, and set all the bits to 1 rather than 0 for consistency with the least significant 64b. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30 01:53:20 -06:00
/* Restore the scalar FP control & status register */
if (!was_fpu_owner)
MIPS: traps: Fix inline asm ctc1 missing .set hardfloat Commit 842dfc11ea9a ("MIPS: Fix build with binutils 2.24.51+") in v3.18 enabled -msoft-float and sprinkled ".set hardfloat" where necessary to use FP instructions. However it missed enable_restore_fp_context() which since v3.17 does a ctc1 with inline assembly, causing the following assembler errors on Mentor's 2014.05 toolchain: {standard input}: Assembler messages: {standard input}:2913: Error: opcode not supported on this processor: mips32r2 (mips32r2) `ctc1 $2,$31' scripts/Makefile.build:257: recipe for target 'arch/mips/kernel/traps.o' failed Fix that to use the new write_32bit_cp1_register() macro so that ".set hardfloat" is automatically added when -msoft-float is in use. Fixes 842dfc11ea9a ("MIPS: Fix build with binutils 2.24.51+") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.18+, depends on "MIPS: mipsregs.h: Add write_32bit_cp1_register()" Patchwork: https://patchwork.linux-mips.org/patch/9173/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-30 08:40:20 -07:00
write_32bit_cp1_register(CP1_STATUS,
current->thread.fpu.fcr31);
MIPS: init upper 64b of vector registers when MSA is first used When a task first makes use of MSA we need to ensure that the upper 64b of the vector registers are set to some value such that no information can be leaked to it from the previous task to use MSA context on the CPU. The architecture formerly specified that these bits would be cleared to 0 when a scalar FP instructions wrote to the aliased FP registers, which would have implicitly handled this as the kernel restored scalar FP context. However more recent versions of the specification now state that the value of the bits in such cases is unpredictable. Initialise them explictly to be sure, and set all the bits to 1 rather than 0 for consistency with the least significant 64b. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7497/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-30 01:53:20 -06:00
}
MIPS: disable preemption whilst initialising MSA Preemption must be disabled throughout the process of enabling the FPU, enabling MSA & initialising the vector registers. Without doing so it is possible to lose the FPU or MSA whilst initialising them causing that initialisation to fail. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7307/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-11 09:44:35 -06:00
out:
preempt_enable();
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:11 -07:00
return 0;
}
MIPS: traps: Never enable FPU when CONFIG_MIPS_FP_SUPPORT=n When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so we'll never need to enable the FPU. Avoid doing so on a Co-Processor Unusable exception (do_cpu), and remove the Floating Point Exception handler (do_fpe) which should never be executed when the FPU is disabled. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21007/ Cc: linux-mips@linux-mips.org
2018-11-07 16:14:05 -07:00
#else /* !CONFIG_MIPS_FP_SUPPORT */
static int enable_restore_fp_context(int msa)
{
return SIGILL;
}
#endif /* CONFIG_MIPS_FP_SUPPORT */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
asmlinkage void do_cpu(struct pt_regs *regs)
{
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
enum ctx_state prev_state;
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
unsigned int __user *epc;
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
unsigned long old_epc, old31;
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
unsigned int opcode;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
unsigned int cpid;
MIPS: traps: Never enable FPU when CONFIG_MIPS_FP_SUPPORT=n When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so we'll never need to enable the FPU. Avoid doing so on a Co-Processor Unusable exception (do_cpu), and remove the Floating Point Exception handler (do_fpe) which should never be executed when the FPU is disabled. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21007/ Cc: linux-mips@linux-mips.org
2018-11-07 16:14:05 -07:00
int status;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
prev_state = exception_enter();
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
MIPS: Allow kernel to use coprocessor 2 Kernel threads should be able to use COP2 if the platform needs it. Do not call die_if_kernel() for a coprocessor unusable exception if the exception due to COP2 usage. Instead, the default notifier for COP2 exceptions is updated to call die_if_kernel. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5415/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-10 00:30:01 -06:00
if (cpid != 2)
die_if_kernel("do_cpu invoked from kernel context!", regs);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
switch (cpid) {
case 0:
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
epc = (unsigned int __user *)exception_epc(regs);
old_epc = regs->cp0_epc;
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
old31 = regs->regs[31];
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
opcode = 0;
status = -1;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
if (unlikely(compute_return_epc(regs) < 0))
MIPS: Normalise code flow in the CpU exception handler Changes applied to `do_cpu' over time reduced the use of the SIGILL issued with `force_sig' at the end to a single CU3 case only in the switch statement there. Move that `force_sig' call over to right where required then and toss out the pile of gotos now not needed to skip over the call, replacing them with regular breaks out of the switch. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:25:08 -06:00
break;
NPTL, round one. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-04-13 11:43:59 -06:00
MIPS: traps.c: Don't emulate RDHWR in the CpU #0 exception handler In the regular MIPS instruction set RDHWR is encoded with the SPECIAL3 (011111) major opcode. Therefore it cannot trigger the CpU (Coprocessor Unusable) exception, and certainly not for coprocessor 0, as the opcode does not overlap with any of the older ISA reservations, i.e. LWC0 (110000), SWC0 (111000), LDC0 (110100) or SDC0 (111100). The closest match might be SDC3 (111111), possibly causing a CpU #3 exception, however our code does not handle it anyway. A quick check with a MIPS I and a MIPS III processor: CPU0 revision is: 00000220 (R3000) CPU0 revision is: 00000440 (R4400SC) indeed indicates that the RI (Reserved Instruction) exception is triggered. It's only LL and SC that require emulation in the CpU #0 exception handler as they reuse the LWC0 and SWC0 opcodes respectively. In the microMIPS instruction set RDHWR is mandatory and triggering the RI exception is required on unimplemented or disabled register accesses. Therefore emulating the microMIPS instruction in the CpU #0 exception handler is not required either. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12280/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-01-30 02:08:16 -07:00
if (!get_isa16_mode(regs->cp0_epc)) {
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
if (unlikely(get_user(opcode, epc) < 0))
status = SIGSEGV;
if (!cpu_has_llsc && status < 0)
status = simulate_llsc(regs, opcode);
}
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
if (status < 0)
status = SIGILL;
if (unlikely(status > 0)) {
regs->cp0_epc = old_epc; /* Undo skip-over. */
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
regs->regs[31] = old31;
[MIPS] SYNC emulation for MIPS I processors Userland, including the C library and the dynamic linker, is keen to use the SYNC instruction, even for "generic" MIPS I binaries these days. Which makes it less than useful on MIPS I processors. This change adds the emulation, but as our do_ri() infrastructure was not really prepared to take yet another instruction, I have rewritten it and its callees slightly as follows. Now there is only a single place a possible signal is thrown from. The place is at the end of do_ri(). The instruction word is fetched in do_ri() and passed down to handlers. The handlers are called in sequence and return a result that lets the caller decide upon further processing. If the result is positive, then the handler has picked the instruction, but a signal should be thrown and the result is the signal number. If the result is zero, then the handler has successfully simulated the instruction. If the result is negative, then the handler did not handle the instruction; to make it more obvious the calls do not follow the usual 0/-Exxx result convention they now return -1 instead of -EFAULT. The calculation of the return EPC is now at the beginning. The reason is it is easier to handle it there as emulation callees may modify a register and an instruction may be located in delay slot of a branch whose result depends on the register. It has to be undone if a signal is to be raised, but it is not a problem as this is the slow-path case, and both actions are done in single places now rather than the former being scattered through emulation handlers. The part of do_cpu() being covered follows the changes to do_ri(). Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2007-10-16 11:43:26 -06:00
force_sig(status, current);
}
MIPS: Normalise code flow in the CpU exception handler Changes applied to `do_cpu' over time reduced the use of the SIGILL issued with `force_sig' at the end to a single CU3 case only in the switch statement there. Move that `force_sig' call over to right where required then and toss out the pile of gotos now not needed to skip over the call, replacing them with regular breaks out of the switch. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:25:08 -06:00
break;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: traps: Never enable FPU when CONFIG_MIPS_FP_SUPPORT=n When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so we'll never need to enable the FPU. Avoid doing so on a Co-Processor Unusable exception (do_cpu), and remove the Floating Point Exception handler (do_fpe) which should never be executed when the FPU is disabled. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21007/ Cc: linux-mips@linux-mips.org
2018-11-07 16:14:05 -07:00
#ifdef CONFIG_MIPS_FP_SUPPORT
MIPS: Handle COP3 Unusable exception as COP1X for FP emulation Our FP emulator is hardcoded for the MIPS IV FP instruction set and does not match the FP ISA with the general ISA. However for the few MIPS IV FP instructions that use the COP1X major opcode it relies on the Coprocessor Unusable exception to be delivered as a COP1 rather than COP3 exception. This includes indexed transfer (LDXC1, etc.) and FP multiply-accumulate (MADD.D, etc.) instructions. All the MIPS I, II, III and IV processors and some newer chips that do not implement the FPU use the COP3 exception however. Therefore I believe the kernel should follow and redirect any COP3 Unusable traps to the emulator unless an actual FPU part or core is present. This is a change that implements it. Any minor opcode encodings that are not recognised as valid FP instructions are rejected by the emulator and will result in a SIGILL signal being delivered as they currently do. We do not support vendor-specific coprocessor 3 implementations supported with MIPS I and MIPS II ISA processors; we never set CP0.Status.CU3. [Ralf: On MIPS IV processors the kernel always enables the XX bit which replaces the CU3 bit off earlier architecture revisions.] If matching between the CPU and the FPU ISA is considered required one day, this can still be done in the emulator itself. I think the CpU exception dispatcher is not the right place to do this anyway, as there are further differences between MIPS I, MIPS II, MIPS III, MIPS IV and MIPS32 FP ISAs. Corresponding explanation of this implementation is included within the change itself. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/project/linux-mips/list/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-03-06 13:28:54 -07:00
case 3:
/*
MIPS: Correct FP ISA requirements Correct ISA requirements for floating-point instructions: * the CU3 exception signifies a real COP3 instruction in MIPS I & II, * the BC1FL and BC1TL instructions are not supported in MIPS I, * the SQRT.fmt instructions are indeed supported in MIPS II, * the LDC1 and SDC1 instructions are indeed supported in MIPS32r1, * the CEIL.W.fmt, FLOOR.W.fmt, ROUND.W.fmt and TRUNC.W.fmt instructions are indeed supported in MIPS32, * the CVT.L.fmt and CVT.fmt.L instructions are indeed supported in MIPS32r2 and MIPS32r6, * the CEIL.L.fmt, FLOOR.L.fmt, ROUND.L.fmt and TRUNC.L.fmt instructions are indeed supported in MIPS32r2 and MIPS32r6, * the RSQRT.fmt and RECIP.fmt instructions are indeed supported in MIPS64r1, Also simplify conditionals for MIPS III and MIPS IV FPU instructions and the handling of the MOVCI minor opcode. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:26:49 -06:00
* The COP3 opcode space and consequently the CP0.Status.CU3
* bit and the CP0.Cause.CE=3 encoding have been removed as
* of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
* up the space has been reused for COP1X instructions, that
* are enabled by the CP0.Status.CU1 bit and consequently
* use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
* exceptions. Some FPU-less processors that implement one
* of these ISAs however use this code erroneously for COP1X
* instructions. Therefore we redirect this trap to the FP
* emulator too.
MIPS: Handle COP3 Unusable exception as COP1X for FP emulation Our FP emulator is hardcoded for the MIPS IV FP instruction set and does not match the FP ISA with the general ISA. However for the few MIPS IV FP instructions that use the COP1X major opcode it relies on the Coprocessor Unusable exception to be delivered as a COP1 rather than COP3 exception. This includes indexed transfer (LDXC1, etc.) and FP multiply-accumulate (MADD.D, etc.) instructions. All the MIPS I, II, III and IV processors and some newer chips that do not implement the FPU use the COP3 exception however. Therefore I believe the kernel should follow and redirect any COP3 Unusable traps to the emulator unless an actual FPU part or core is present. This is a change that implements it. Any minor opcode encodings that are not recognised as valid FP instructions are rejected by the emulator and will result in a SIGILL signal being delivered as they currently do. We do not support vendor-specific coprocessor 3 implementations supported with MIPS I and MIPS II ISA processors; we never set CP0.Status.CU3. [Ralf: On MIPS IV processors the kernel always enables the XX bit which replaces the CU3 bit off earlier architecture revisions.] If matching between the CPU and the FPU ISA is considered required one day, this can still be done in the emulator itself. I think the CpU exception dispatcher is not the right place to do this anyway, as there are further differences between MIPS I, MIPS II, MIPS III, MIPS IV and MIPS32 FP ISAs. Corresponding explanation of this implementation is included within the change itself. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/project/linux-mips/list/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-03-06 13:28:54 -07:00
*/
MIPS: Correct FP ISA requirements Correct ISA requirements for floating-point instructions: * the CU3 exception signifies a real COP3 instruction in MIPS I & II, * the BC1FL and BC1TL instructions are not supported in MIPS I, * the SQRT.fmt instructions are indeed supported in MIPS II, * the LDC1 and SDC1 instructions are indeed supported in MIPS32r1, * the CEIL.W.fmt, FLOOR.W.fmt, ROUND.W.fmt and TRUNC.W.fmt instructions are indeed supported in MIPS32, * the CVT.L.fmt and CVT.fmt.L instructions are indeed supported in MIPS32r2 and MIPS32r6, * the CEIL.L.fmt, FLOOR.L.fmt, ROUND.L.fmt and TRUNC.L.fmt instructions are indeed supported in MIPS32r2 and MIPS32r6, * the RSQRT.fmt and RECIP.fmt instructions are indeed supported in MIPS64r1, Also simplify conditionals for MIPS III and MIPS IV FPU instructions and the handling of the MOVCI minor opcode. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:26:49 -06:00
if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
MIPS: Normalise code flow in the CpU exception handler Changes applied to `do_cpu' over time reduced the use of the SIGILL issued with `force_sig' at the end to a single CU3 case only in the switch statement there. Move that `force_sig' call over to right where required then and toss out the pile of gotos now not needed to skip over the call, replacing them with regular breaks out of the switch. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:25:08 -06:00
force_sig(SIGILL, current);
MIPS: Handle COP3 Unusable exception as COP1X for FP emulation Our FP emulator is hardcoded for the MIPS IV FP instruction set and does not match the FP ISA with the general ISA. However for the few MIPS IV FP instructions that use the COP1X major opcode it relies on the Coprocessor Unusable exception to be delivered as a COP1 rather than COP3 exception. This includes indexed transfer (LDXC1, etc.) and FP multiply-accumulate (MADD.D, etc.) instructions. All the MIPS I, II, III and IV processors and some newer chips that do not implement the FPU use the COP3 exception however. Therefore I believe the kernel should follow and redirect any COP3 Unusable traps to the emulator unless an actual FPU part or core is present. This is a change that implements it. Any minor opcode encodings that are not recognised as valid FP instructions are rejected by the emulator and will result in a SIGILL signal being delivered as they currently do. We do not support vendor-specific coprocessor 3 implementations supported with MIPS I and MIPS II ISA processors; we never set CP0.Status.CU3. [Ralf: On MIPS IV processors the kernel always enables the XX bit which replaces the CU3 bit off earlier architecture revisions.] If matching between the CPU and the FPU ISA is considered required one day, this can still be done in the emulator itself. I think the CpU exception dispatcher is not the right place to do this anyway, as there are further differences between MIPS I, MIPS II, MIPS III, MIPS IV and MIPS32 FP ISAs. Corresponding explanation of this implementation is included within the change itself. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/project/linux-mips/list/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-03-06 13:28:54 -07:00
break;
MIPS: Normalise code flow in the CpU exception handler Changes applied to `do_cpu' over time reduced the use of the SIGILL issued with `force_sig' at the end to a single CU3 case only in the switch statement there. Move that `force_sig' call over to right where required then and toss out the pile of gotos now not needed to skip over the call, replacing them with regular breaks out of the switch. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:25:08 -06:00
}
MIPS: Handle COP3 Unusable exception as COP1X for FP emulation Our FP emulator is hardcoded for the MIPS IV FP instruction set and does not match the FP ISA with the general ISA. However for the few MIPS IV FP instructions that use the COP1X major opcode it relies on the Coprocessor Unusable exception to be delivered as a COP1 rather than COP3 exception. This includes indexed transfer (LDXC1, etc.) and FP multiply-accumulate (MADD.D, etc.) instructions. All the MIPS I, II, III and IV processors and some newer chips that do not implement the FPU use the COP3 exception however. Therefore I believe the kernel should follow and redirect any COP3 Unusable traps to the emulator unless an actual FPU part or core is present. This is a change that implements it. Any minor opcode encodings that are not recognised as valid FP instructions are rejected by the emulator and will result in a SIGILL signal being delivered as they currently do. We do not support vendor-specific coprocessor 3 implementations supported with MIPS I and MIPS II ISA processors; we never set CP0.Status.CU3. [Ralf: On MIPS IV processors the kernel always enables the XX bit which replaces the CU3 bit off earlier architecture revisions.] If matching between the CPU and the FPU ISA is considered required one day, this can still be done in the emulator itself. I think the CpU exception dispatcher is not the right place to do this anyway, as there are further differences between MIPS I, MIPS II, MIPS III, MIPS IV and MIPS32 FP ISAs. Corresponding explanation of this implementation is included within the change itself. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/project/linux-mips/list/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-03-06 13:28:54 -07:00
/* Fall through. */
MIPS: traps: Never enable FPU when CONFIG_MIPS_FP_SUPPORT=n When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so we'll never need to enable the FPU. Avoid doing so on a Co-Processor Unusable exception (do_cpu), and remove the Floating Point Exception handler (do_fpe) which should never be executed when the FPU is disabled. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21007/ Cc: linux-mips@linux-mips.org
2018-11-07 16:14:05 -07:00
case 1: {
void __user *fault_addr;
unsigned long fcr31;
int err, sig;
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:11 -07:00
err = enable_restore_fp_context(0);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
if (raw_cpu_has_fpu && !err)
break;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
&fault_addr);
/*
* We can't allow the emulated instruction to leave
MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-28 01:21:03 -06:00
* any enabled Cause bits set in $fcr31.
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
*/
MIPS: Fix FCSR Cause bit handling for correct SIGFPE issue Sanitize FCSR Cause bit handling, following a trail of past attempts: * commit 4249548454f7 ("MIPS: ptrace: Fix FP context restoration FCSR regression"), * commit 443c44032a54 ("MIPS: Always clear FCSR cause bits after emulation"), * commit 64bedffe4968 ("MIPS: Clear [MSA]FPE CSR.Cause after notify_die()"), * commit b1442d39fac2 ("MIPS: Prevent user from setting FCSR cause bits"), * commit b54d2901517d ("Properly handle branch delay slots in connection with signals."). Specifically do not mask these bits out in ptrace(2) processing and send a SIGFPE signal instead whenever a matching pair of an FCSR Cause and Enable bit is seen as execution of an affected context is about to resume. Only then clear Cause bits, and even then do not clear any bits that are set but masked with the respective Enable bits. Adjust Cause bit clearing throughout code likewise, except within the FPU emulator proper where they are set according to IEEE 754 exceptions raised as the operation emulated executed. Do so so that any IEEE 754 exceptions subject to their default handling are recorded like with operations executed by FPU hardware. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14460/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-28 01:21:03 -06:00
fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
current->thread.fpu.fcr31 &= ~fcr31;
MIPS: Set `si_code' for SIGFPE signals sent from emulation too Rework `process_fpemu_return' and move IEEE 754 exception interpretation there, from `do_fpe'. Record the cause bits set in FCSR before they are cleared and pass them through to `process_fpemu_return' so as to set `si_code' correctly too for SIGFPE signals sent from emulation rather than those issued by hardware with the FPE processor exception only. For simplicity `mipsr2_decoder' assumes `*fcr31' has been preinitialised and only sets it to anything if an FPU instruction has been emulated, which in turn is the only case SIGFPE can be issued for here. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9705/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:27:15 -06:00
/* Send a signal if required. */
if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
mt_ase_fp_affinity();
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: Normalise code flow in the CpU exception handler Changes applied to `do_cpu' over time reduced the use of the SIGILL issued with `force_sig' at the end to a single CU3 case only in the switch statement there. Move that `force_sig' call over to right where required then and toss out the pile of gotos now not needed to skip over the call, replacing them with regular breaks out of the switch. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:25:08 -06:00
break;
MIPS: traps: Never enable FPU when CONFIG_MIPS_FP_SUPPORT=n When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so we'll never need to enable the FPU. Avoid doing so on a Co-Processor Unusable exception (do_cpu), and remove the Floating Point Exception handler (do_fpe) which should never be executed when the FPU is disabled. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21007/ Cc: linux-mips@linux-mips.org
2018-11-07 16:14:05 -07:00
}
#else /* CONFIG_MIPS_FP_SUPPORT */
case 1:
case 3:
force_sig(SIGILL, current);
break;
#endif /* CONFIG_MIPS_FP_SUPPORT */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
case 2:
MIPS: Modularize COP2 handling Away with the daemons of ifdef; get ready for future COP2 users. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/708/
2009-11-23 18:24:58 -07:00
raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
MIPS: Normalise code flow in the CpU exception handler Changes applied to `do_cpu' over time reduced the use of the SIGILL issued with `force_sig' at the end to a single CU3 case only in the switch statement there. Move that `force_sig' call over to right where required then and toss out the pile of gotos now not needed to skip over the call, replacing them with regular breaks out of the switch. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-04-03 16:25:08 -06:00
break;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
exception_exit(prev_state);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
MIPS: Clear [MSA]FPE CSR.Cause after notify_die() When handling floating point exceptions (FPEs) and MSA FPEs the Cause bits of the appropriate control and status register (FCSR for FPEs and MSACSR for MSA FPEs) are read and cleared before enabling interrupts, presumably so that it doesn't have to go through the pain of restoring those bits if the process is pre-empted, since writing those bits would cause another immediate exception while still in the kernel. The bits aren't normally ever restored again, since userland never expects to see them set. However for virtualisation it is necessary for the kernel to be able to restore these Cause bits, as the guest may have been interrupted in an FP exception handler but before it could read the Cause bits. This can be done by registering a die notifier, to get notified of the exception when such a value is restored, and if the PC was at the instruction which is used to restore the guest state, the handler can step over it and continue execution. The Cause bits can then remain set without causing further exceptions. For this to work safely a few changes are made: - __build_clear_fpe and __build_clear_msa_fpe no longer clear the Cause bits, and now return from exception level with interrupts disabled instead of enabled. - do_fpe() now clears the Cause bits and enables interrupts after notify_die() is called, so that the notifier can chose to return from exception without this happening. - do_msa_fpe() acts similarly, but now actually makes use of the second argument (msacsr) and calls notify_die() with the new DIE_MSAFP, allowing die notifiers to be informed of MSA FPEs too. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
2014-12-02 06:44:13 -07:00
asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
MIPS: Dumb MSA FP exception handler This patch adds a simple handler for MSA FP exceptions which delivers a SIGFPE to the running task. In the future it should probably be extended to re-execute the instruction with the MSACSR.NX bit set in order to generate results for any elements which did not cause an exception before delivering the SIGFPE signal. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:12 -07:00
{
enum ctx_state prev_state;
prev_state = exception_enter();
MIPS: Set trap_no field in thread_struct on exception. This reverts commit 7281cd22973008a782860e48ed8d85d00204168c and adds actual functionality to use the field.
2015-07-28 12:37:43 -06:00
current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
MIPS: Clear [MSA]FPE CSR.Cause after notify_die() When handling floating point exceptions (FPEs) and MSA FPEs the Cause bits of the appropriate control and status register (FCSR for FPEs and MSACSR for MSA FPEs) are read and cleared before enabling interrupts, presumably so that it doesn't have to go through the pain of restoring those bits if the process is pre-empted, since writing those bits would cause another immediate exception while still in the kernel. The bits aren't normally ever restored again, since userland never expects to see them set. However for virtualisation it is necessary for the kernel to be able to restore these Cause bits, as the guest may have been interrupted in an FP exception handler but before it could read the Cause bits. This can be done by registering a die notifier, to get notified of the exception when such a value is restored, and if the PC was at the instruction which is used to restore the guest state, the handler can step over it and continue execution. The Cause bits can then remain set without causing further exceptions. For this to work safely a few changes are made: - __build_clear_fpe and __build_clear_msa_fpe no longer clear the Cause bits, and now return from exception level with interrupts disabled instead of enabled. - do_fpe() now clears the Cause bits and enables interrupts after notify_die() is called, so that the notifier can chose to return from exception without this happening. - do_msa_fpe() acts similarly, but now actually makes use of the second argument (msacsr) and calls notify_die() with the new DIE_MSAFP, allowing die notifiers to be informed of MSA FPEs too. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
2014-12-02 06:44:13 -07:00
if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
MIPS: Set trap_no field in thread_struct on exception. This reverts commit 7281cd22973008a782860e48ed8d85d00204168c and adds actual functionality to use the field.
2015-07-28 12:37:43 -06:00
current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
MIPS: Clear [MSA]FPE CSR.Cause after notify_die() When handling floating point exceptions (FPEs) and MSA FPEs the Cause bits of the appropriate control and status register (FCSR for FPEs and MSACSR for MSA FPEs) are read and cleared before enabling interrupts, presumably so that it doesn't have to go through the pain of restoring those bits if the process is pre-empted, since writing those bits would cause another immediate exception while still in the kernel. The bits aren't normally ever restored again, since userland never expects to see them set. However for virtualisation it is necessary for the kernel to be able to restore these Cause bits, as the guest may have been interrupted in an FP exception handler but before it could read the Cause bits. This can be done by registering a die notifier, to get notified of the exception when such a value is restored, and if the PC was at the instruction which is used to restore the guest state, the handler can step over it and continue execution. The Cause bits can then remain set without causing further exceptions. For this to work safely a few changes are made: - __build_clear_fpe and __build_clear_msa_fpe no longer clear the Cause bits, and now return from exception level with interrupts disabled instead of enabled. - do_fpe() now clears the Cause bits and enables interrupts after notify_die() is called, so that the notifier can chose to return from exception without this happening. - do_msa_fpe() acts similarly, but now actually makes use of the second argument (msacsr) and calls notify_die() with the new DIE_MSAFP, allowing die notifiers to be informed of MSA FPEs too. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
2014-12-02 06:44:13 -07:00
goto out;
/* Clear MSACSR.Cause before enabling interrupts */
write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
local_irq_enable();
MIPS: Dumb MSA FP exception handler This patch adds a simple handler for MSA FP exceptions which delivers a SIGFPE to the running task. In the future it should probably be extended to re-execute the instruction with the MSACSR.NX bit set in order to generate results for any elements which did not cause an exception before delivering the SIGFPE signal. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:12 -07:00
die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
force_sig(SIGFPE, current);
MIPS: Clear [MSA]FPE CSR.Cause after notify_die() When handling floating point exceptions (FPEs) and MSA FPEs the Cause bits of the appropriate control and status register (FCSR for FPEs and MSACSR for MSA FPEs) are read and cleared before enabling interrupts, presumably so that it doesn't have to go through the pain of restoring those bits if the process is pre-empted, since writing those bits would cause another immediate exception while still in the kernel. The bits aren't normally ever restored again, since userland never expects to see them set. However for virtualisation it is necessary for the kernel to be able to restore these Cause bits, as the guest may have been interrupted in an FP exception handler but before it could read the Cause bits. This can be done by registering a die notifier, to get notified of the exception when such a value is restored, and if the PC was at the instruction which is used to restore the guest state, the handler can step over it and continue execution. The Cause bits can then remain set without causing further exceptions. For this to work safely a few changes are made: - __build_clear_fpe and __build_clear_msa_fpe no longer clear the Cause bits, and now return from exception level with interrupts disabled instead of enabled. - do_fpe() now clears the Cause bits and enables interrupts after notify_die() is called, so that the notifier can chose to return from exception without this happening. - do_msa_fpe() acts similarly, but now actually makes use of the second argument (msacsr) and calls notify_die() with the new DIE_MSAFP, allowing die notifiers to be informed of MSA FPEs too. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
2014-12-02 06:44:13 -07:00
out:
MIPS: Dumb MSA FP exception handler This patch adds a simple handler for MSA FP exceptions which delivers a SIGFPE to the running task. In the future it should probably be extended to re-execute the instruction with the MSACSR.NX bit set in order to generate results for any elements which did not cause an exception before delivering the SIGFPE signal. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6432/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:12 -07:00
exception_exit(prev_state);
}
MIPS: Basic MSA context switching support This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-27 08:23:11 -07:00
asmlinkage void do_msa(struct pt_regs *regs)
{
enum ctx_state prev_state;
int err;
prev_state = exception_enter();
if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
force_sig(SIGILL, current);
goto out;
}
die_if_kernel("do_msa invoked from kernel context!", regs);
err = enable_restore_fp_context(1);
if (err)
force_sig(SIGILL, current);
out:
exception_exit(prev_state);
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
asmlinkage void do_mdmx(struct pt_regs *regs)
{
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
enum ctx_state prev_state;
prev_state = exception_enter();
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
force_sig(SIGILL, current);
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
exception_exit(prev_state);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
MIPS: Read watch registers with interrupts disabled. If a context switch occurred between the watch exception and reading the watch registers, it would be possible for the new process to corrupt their state. Enabling interrupts only after the watch registers are read avoids this race. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-05 16:29:58 -07:00
/*
* Called with interrupts disabled.
*/
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
asmlinkage void do_watch(struct pt_regs *regs)
{
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
enum ctx_state prev_state;
MIPS: Watch exception handling for HARDWARE_WATCHPOINTS. Here we hook up the watch exception handler so that it sends SIGTRAP when the hardware watch registers are triggered. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-09-23 01:08:45 -06:00
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
prev_state = exception_enter();
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
MIPS: Watch exception handling for HARDWARE_WATCHPOINTS. Here we hook up the watch exception handler so that it sends SIGTRAP when the hardware watch registers are triggered. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-09-23 01:08:45 -06:00
* Clear WP (bit 22) bit of cause register so we don't loop
* forever.
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
*/
MIPS: Add and use CAUSEF_WP definition do_watch() clears bit 22 of cause without using a CAUSEF_* definition from mipsregs.h. Add a definition for this bit (CAUSEF_WP) and make use of it. Also use clear_c0_cause() instead of manual read/modify/write. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12728/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-03-01 15:19:38 -07:00
clear_c0_cause(CAUSEF_WP);
MIPS: Watch exception handling for HARDWARE_WATCHPOINTS. Here we hook up the watch exception handler so that it sends SIGTRAP when the hardware watch registers are triggered. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-09-23 01:08:45 -06:00
/*
* If the current thread has the watch registers loaded, save
* their values and send SIGTRAP. Otherwise another thread
* left the registers set, clear them and continue.
*/
if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
mips_read_watch_registers();
MIPS: Read watch registers with interrupts disabled. If a context switch occurred between the watch exception and reading the watch registers, it would be possible for the new process to corrupt their state. Enabling interrupts only after the watch registers are read avoids this race. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-05 16:29:58 -07:00
local_irq_enable();
signal/mips: Use force_sig_fault where appropriate Filling in struct siginfo before calling force_sig_info a tedious and error prone process, where once in a great while the wrong fields are filled out, and siginfo has been inconsistently cleared. Simplify this process by using the helper force_sig_fault. Which takes as a parameters all of the information it needs, ensures all of the fiddly bits of filling in struct siginfo are done properly and then calls force_sig_info. In short about a 5 line reduction in code for every time force_sig_info is called, which makes the calling function clearer. Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
2018-04-15 20:11:06 -06:00
force_sig_fault(SIGTRAP, TRAP_HWBKPT, NULL, current);
MIPS: Read watch registers with interrupts disabled. If a context switch occurred between the watch exception and reading the watch registers, it would be possible for the new process to corrupt their state. Enabling interrupts only after the watch registers are read avoids this race. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-05 16:29:58 -07:00
} else {
MIPS: Watch exception handling for HARDWARE_WATCHPOINTS. Here we hook up the watch exception handler so that it sends SIGTRAP when the hardware watch registers are triggered. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-09-23 01:08:45 -06:00
mips_clear_watch_registers();
MIPS: Read watch registers with interrupts disabled. If a context switch occurred between the watch exception and reading the watch registers, it would be possible for the new process to corrupt their state. Enabling interrupts only after the watch registers are read avoids this race. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-05 16:29:58 -07:00
local_irq_enable();
}
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
exception_exit(prev_state);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
asmlinkage void do_mcheck(struct pt_regs *regs)
{
[MIPS] Print more information if we're struck by a machine check exception. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-05-24 09:51:02 -06:00
int multi_match = regs->cp0_status & ST0_TS;
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
enum ctx_state prev_state;
MIPS: do_mcheck: Fix kernel code dump with EVA If a machine check exception is raised in kernel mode, user context, with EVA enabled, then the do_mcheck handler will attempt to read the code around the EPC using EVA load instructions, i.e. as if the reads were from user mode. This will either read random user data if the process has anything mapped at the same address, or it will cause an exception which is handled by __get_user, resulting in this output: Code: (Bad address in epc) Fix by setting the current user access mode to kernel if the saved register context indicates the exception was taken in kernel mode. This causes __get_user to use normal loads to read the kernel code. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.15+ Patchwork: https://patchwork.linux-mips.org/patch/10777/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-27 06:50:21 -06:00
mm_segment_t old_fs = get_fs();
[MIPS] Print more information if we're struck by a machine check exception. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-05-24 09:51:02 -06:00
MIPS: Implement HAVE_CONTEXT_TRACKING. This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-28 17:07:19 -06:00
prev_state = exception_enter();
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
show_regs(regs);
[MIPS] Print more information if we're struck by a machine check exception. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-05-24 09:51:02 -06:00
if (multi_match) {
MIPS: Refactor dumping of TLB registers for r3k/r4k The TLB registers are dumped in a couble of places: - sysrq_tlbdump_single() - when dumping TLB state. - do_mcheck() - in response to a machine check error. The main TLB registers also differ between r3k and r4k, but r4k appears to be assumed. Refactor this code into a dump_tlb_regs() function, implemented for both r3k and r4k, and used by both of the above functions. Fixes: d1e9a4f54735 ("MIPS: Add SysRq operation to dump TLBs on all CPUs") Suggested-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10721/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-15 09:17:43 -06:00
dump_tlb_regs();
pr_info("\n");
[MIPS] Print more information if we're struck by a machine check exception. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-05-24 09:51:02 -06:00
dump_tlb_all();
}
MIPS: do_mcheck: Fix kernel code dump with EVA If a machine check exception is raised in kernel mode, user context, with EVA enabled, then the do_mcheck handler will attempt to read the code around the EPC using EVA load instructions, i.e. as if the reads were from user mode. This will either read random user data if the process has anything mapped at the same address, or it will cause an exception which is handled by __get_user, resulting in this output: Code: (Bad address in epc) Fix by setting the current user access mode to kernel if the saved register context indicates the exception was taken in kernel mode. This causes __get_user to use normal loads to read the kernel code. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.15+ Patchwork: https://patchwork.linux-mips.org/patch/10777/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-27 06:50:21 -06:00
if (!user_mode(regs))
set_fs(KERNEL_DS);
[MIPS] Make show_code static and add __user tag Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-13 08:51:46 -06:00
show_code((unsigned int __user *) regs->cp0_epc);
[MIPS] Print more information if we're struck by a machine check exception. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-05-24 09:51:02 -06:00
MIPS: do_mcheck: Fix kernel code dump with EVA If a machine check exception is raised in kernel mode, user context, with EVA enabled, then the do_mcheck handler will attempt to read the code around the EPC using EVA load instructions, i.e. as if the reads were from user mode. This will either read random user data if the process has anything mapped at the same address, or it will cause an exception which is handled by __get_user, resulting in this output: Code: (Bad address in epc) Fix by setting the current user access mode to kernel if the saved register context indicates the exception was taken in kernel mode. This causes __get_user to use normal loads to read the kernel code. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 3.15+ Patchwork: https://patchwork.linux-mips.org/patch/10777/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-07-27 06:50:21 -06:00
set_fs(old_fs);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
* Some chips may have other causes of machine check (e.g. SB1
* graduation timer)
*/
panic("Caught Machine Check exception - %scaused by multiple "
"matching entries in the TLB.",
[MIPS] Print more information if we're struck by a machine check exception. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-05-24 09:51:02 -06:00
(multi_match) ? "" : "not ");
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
Virtual SMP support for the 34K. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-08-17 11:44:08 -06:00
asmlinkage void do_mt(struct pt_regs *regs)
{
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 02:45:45 -06:00
int subcode;
subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
>> VPECONTROL_EXCPT_SHIFT;
switch (subcode) {
case 0:
[MIPS] Less noise on multithreading exceptions. Make the MT handler silent and output the MT exception type at debug priority. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-30 07:19:45 -06:00
printk(KERN_DEBUG "Thread Underflow\n");
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 02:45:45 -06:00
break;
case 1:
[MIPS] Less noise on multithreading exceptions. Make the MT handler silent and output the MT exception type at debug priority. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-30 07:19:45 -06:00
printk(KERN_DEBUG "Thread Overflow\n");
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 02:45:45 -06:00
break;
case 2:
[MIPS] Less noise on multithreading exceptions. Make the MT handler silent and output the MT exception type at debug priority. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-30 07:19:45 -06:00
printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 02:45:45 -06:00
break;
case 3:
[MIPS] Less noise on multithreading exceptions. Make the MT handler silent and output the MT exception type at debug priority. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-30 07:19:45 -06:00
printk(KERN_DEBUG "Gating Storage Exception\n");
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 02:45:45 -06:00
break;
case 4:
[MIPS] Less noise on multithreading exceptions. Make the MT handler silent and output the MT exception type at debug priority. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-30 07:19:45 -06:00
printk(KERN_DEBUG "YIELD Scheduler Exception\n");
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 02:45:45 -06:00
break;
case 5:
MIPS: traps.c: Fix typo Correct spelling of "Schedulier" to "Scheduler" in arch/mips/kernel/traps.c Signed-off-by: Masanari Iida <standby24x7@gmail.com> Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/3354/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-02-08 05:53:14 -07:00
printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 02:45:45 -06:00
break;
default:
[MIPS] Less noise on multithreading exceptions. Make the MT handler silent and output the MT exception type at debug priority. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-30 07:19:45 -06:00
printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 02:45:45 -06:00
subcode);
break;
}
Virtual SMP support for the 34K. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-08-17 11:44:08 -06:00
die_if_kernel("MIPS MT Thread exception in kernel", regs);
force_sig(SIGILL, current);
}
Support the MIPS32 / MIPS64 DSP ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-05-31 05:49:19 -06:00
asmlinkage void do_dsp(struct pt_regs *regs)
{
if (cpu_has_dsp)
MIPS: Fix up inconsistency in panic() string argument. Panic() invokes printk() to add a \n internally, so panic arguments should not themselves end in \n. Panic invocations in arch/mips and elsewhere are inconsistently sometimes terminating in \n, sometimes not. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-11-17 08:07:31 -07:00
panic("Unexpected DSP exception");
Support the MIPS32 / MIPS64 DSP ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-05-31 05:49:19 -06:00
force_sig(SIGILL, current);
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
asmlinkage void do_reserved(struct pt_regs *regs)
{
/*
MIPS: Whitespace cleanup. Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-01-22 04:59:30 -07:00
* Game over - no way to handle this if it ever occurs. Most probably
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
* caused by a new unknown cpu type or after another deadly
* hard/software error.
*/
show_regs(regs);
panic("Caught reserved exception %ld - should not happen.",
(regs->cp0_cause & 0x7f) >> 2);
}
[MIPS] Add support for MIPS CMP platform. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 10:14:26 -06:00
static int __initdata l1parity = 1;
static int __init nol1parity(char *s)
{
l1parity = 0;
return 1;
}
__setup("nol1par", nol1parity);
static int __initdata l2parity = 1;
static int __init nol2parity(char *s)
{
l2parity = 0;
return 1;
}
__setup("nol2par", nol2parity);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
* Some MIPS CPUs can enable/disable for cache parity detection, but do
* it different ways.
*/
static inline void parity_protection_init(void)
{
MIPS: traps: Ensure L1 & L2 ECC checking match for CM3 systems On systems with CM3, we must ensure that the L1 & L2 ECC enables are set to the same value. This is presumed by the hardware & cache corruption can occur when it is not the case. Support enabling & disabling the L2 ECC checking on CM3 systems where this is controlled via a GCR, and ensure that it matches the state of L1 ECC checking. Remove I6400 from the switch statement it will no longer hit, and which was incorrect since the L2 ECC enable bit isn't in the CP0 ErrCtl register. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14413/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-17 09:01:07 -06:00
#define ERRCTL_PE 0x80000000
#define ERRCTL_L2P 0x00800000
if (mips_cm_revision() >= CM_REV_CM3) {
ulong gcr_ectl, cp0_ectl;
/*
* With CM3 systems we need to ensure that the L1 & L2
* parity enables are set to the same value, since this
* is presumed by the hardware engineers.
*
* If the user disabled either of L1 or L2 ECC checking,
* disable both.
*/
l1parity &= l2parity;
l2parity &= l1parity;
/* Probe L1 ECC support */
cp0_ectl = read_c0_ecc();
write_c0_ecc(cp0_ectl | ERRCTL_PE);
back_to_back_c0_hazard();
cp0_ectl = read_c0_ecc();
/* Probe L2 ECC support */
gcr_ectl = read_gcr_err_control();
MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts There's no reason for us not to use BIT() & GENMASK() in asm/mips-cm.h when declaring macros corresponding to register fields. This patch modifies our definitions to do so. The *_SHF definitions are removed entirely - they duplicate information found in the masks, are infrequently used & can be replaced with use of __ffs() where needed. The *_MSK definitions then lose their _MSK suffix which is now somewhat redundant, and users are modified to match. The field definitions are moved to follow the appropriate register's accessor functions, which helps to keep the field definitions in order & to find the appropriate fields for a given register. Whilst here a comment is added describing each register & including its name, which is helpful both for linking the register back to hardware documentation & for grepping purposes. This also cleans up a couple of issues that became obvious as a result of making the changes described above: - We previously had definitions for GCR_Cx_RESET_EXT_BASE & a phony copy of that named GCR_RESET_EXT_BASE - a register which does not exist. The bad definitions were added by commit 497e803ebf98 ("MIPS: smp-cps: Ensure secondary cores start with EVA disabled") and made use of from boot_core(), which is now modified to use the GCR_Cx_RESET_EXT_BASE definitions. - We had a typo in CM_GCR_ERROR_CAUSE_ERRINGO_MSK - we now correctly define this as inFo rather than inGo. Now that we don't duplicate field information between _SHF & _MSK definitions, and keep the fields next to the register accessors, it will be much easier to spot & prevent any similar oddities being introduced in the future. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Thomas Gleixner <tglx@linutronix.de Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17001/ Patchwork: https://patchwork.linux-mips.org/patch/17216/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-12 20:49:27 -06:00
if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) ||
MIPS: traps: Ensure L1 & L2 ECC checking match for CM3 systems On systems with CM3, we must ensure that the L1 & L2 ECC enables are set to the same value. This is presumed by the hardware & cache corruption can occur when it is not the case. Support enabling & disabling the L2 ECC checking on CM3 systems where this is controlled via a GCR, and ensure that it matches the state of L1 ECC checking. Remove I6400 from the switch statement it will no longer hit, and which was incorrect since the L2 ECC enable bit isn't in the CP0 ErrCtl register. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14413/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-17 09:01:07 -06:00
!(cp0_ectl & ERRCTL_PE)) {
/*
* One of L1 or L2 ECC checking isn't supported,
* so we cannot enable either.
*/
l1parity = l2parity = 0;
}
/* Configure L1 ECC checking */
if (l1parity)
cp0_ectl |= ERRCTL_PE;
else
cp0_ectl &= ~ERRCTL_PE;
write_c0_ecc(cp0_ectl);
back_to_back_c0_hazard();
WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
/* Configure L2 ECC checking */
if (l2parity)
MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts There's no reason for us not to use BIT() & GENMASK() in asm/mips-cm.h when declaring macros corresponding to register fields. This patch modifies our definitions to do so. The *_SHF definitions are removed entirely - they duplicate information found in the masks, are infrequently used & can be replaced with use of __ffs() where needed. The *_MSK definitions then lose their _MSK suffix which is now somewhat redundant, and users are modified to match. The field definitions are moved to follow the appropriate register's accessor functions, which helps to keep the field definitions in order & to find the appropriate fields for a given register. Whilst here a comment is added describing each register & including its name, which is helpful both for linking the register back to hardware documentation & for grepping purposes. This also cleans up a couple of issues that became obvious as a result of making the changes described above: - We previously had definitions for GCR_Cx_RESET_EXT_BASE & a phony copy of that named GCR_RESET_EXT_BASE - a register which does not exist. The bad definitions were added by commit 497e803ebf98 ("MIPS: smp-cps: Ensure secondary cores start with EVA disabled") and made use of from boot_core(), which is now modified to use the GCR_Cx_RESET_EXT_BASE definitions. - We had a typo in CM_GCR_ERROR_CAUSE_ERRINGO_MSK - we now correctly define this as inFo rather than inGo. Now that we don't duplicate field information between _SHF & _MSK definitions, and keep the fields next to the register accessors, it will be much easier to spot & prevent any similar oddities being introduced in the future. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Thomas Gleixner <tglx@linutronix.de Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17001/ Patchwork: https://patchwork.linux-mips.org/patch/17216/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-12 20:49:27 -06:00
gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN;
MIPS: traps: Ensure L1 & L2 ECC checking match for CM3 systems On systems with CM3, we must ensure that the L1 & L2 ECC enables are set to the same value. This is presumed by the hardware & cache corruption can occur when it is not the case. Support enabling & disabling the L2 ECC checking on CM3 systems where this is controlled via a GCR, and ensure that it matches the state of L1 ECC checking. Remove I6400 from the switch statement it will no longer hit, and which was incorrect since the L2 ECC enable bit isn't in the CP0 ErrCtl register. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14413/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-17 09:01:07 -06:00
else
MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts There's no reason for us not to use BIT() & GENMASK() in asm/mips-cm.h when declaring macros corresponding to register fields. This patch modifies our definitions to do so. The *_SHF definitions are removed entirely - they duplicate information found in the masks, are infrequently used & can be replaced with use of __ffs() where needed. The *_MSK definitions then lose their _MSK suffix which is now somewhat redundant, and users are modified to match. The field definitions are moved to follow the appropriate register's accessor functions, which helps to keep the field definitions in order & to find the appropriate fields for a given register. Whilst here a comment is added describing each register & including its name, which is helpful both for linking the register back to hardware documentation & for grepping purposes. This also cleans up a couple of issues that became obvious as a result of making the changes described above: - We previously had definitions for GCR_Cx_RESET_EXT_BASE & a phony copy of that named GCR_RESET_EXT_BASE - a register which does not exist. The bad definitions were added by commit 497e803ebf98 ("MIPS: smp-cps: Ensure secondary cores start with EVA disabled") and made use of from boot_core(), which is now modified to use the GCR_Cx_RESET_EXT_BASE definitions. - We had a typo in CM_GCR_ERROR_CAUSE_ERRINGO_MSK - we now correctly define this as inFo rather than inGo. Now that we don't duplicate field information between _SHF & _MSK definitions, and keep the fields next to the register accessors, it will be much easier to spot & prevent any similar oddities being introduced in the future. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Thomas Gleixner <tglx@linutronix.de Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17001/ Patchwork: https://patchwork.linux-mips.org/patch/17216/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-12 20:49:27 -06:00
gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN;
MIPS: traps: Ensure L1 & L2 ECC checking match for CM3 systems On systems with CM3, we must ensure that the L1 & L2 ECC enables are set to the same value. This is presumed by the hardware & cache corruption can occur when it is not the case. Support enabling & disabling the L2 ECC checking on CM3 systems where this is controlled via a GCR, and ensure that it matches the state of L1 ECC checking. Remove I6400 from the switch statement it will no longer hit, and which was incorrect since the L2 ECC enable bit isn't in the CP0 ErrCtl register. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14413/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-17 09:01:07 -06:00
write_gcr_err_control(gcr_ectl);
gcr_ectl = read_gcr_err_control();
MIPS: CM: Use BIT/GENMASK for register fields, order & drop shifts There's no reason for us not to use BIT() & GENMASK() in asm/mips-cm.h when declaring macros corresponding to register fields. This patch modifies our definitions to do so. The *_SHF definitions are removed entirely - they duplicate information found in the masks, are infrequently used & can be replaced with use of __ffs() where needed. The *_MSK definitions then lose their _MSK suffix which is now somewhat redundant, and users are modified to match. The field definitions are moved to follow the appropriate register's accessor functions, which helps to keep the field definitions in order & to find the appropriate fields for a given register. Whilst here a comment is added describing each register & including its name, which is helpful both for linking the register back to hardware documentation & for grepping purposes. This also cleans up a couple of issues that became obvious as a result of making the changes described above: - We previously had definitions for GCR_Cx_RESET_EXT_BASE & a phony copy of that named GCR_RESET_EXT_BASE - a register which does not exist. The bad definitions were added by commit 497e803ebf98 ("MIPS: smp-cps: Ensure secondary cores start with EVA disabled") and made use of from boot_core(), which is now modified to use the GCR_Cx_RESET_EXT_BASE definitions. - We had a typo in CM_GCR_ERROR_CAUSE_ERRINGO_MSK - we now correctly define this as inFo rather than inGo. Now that we don't duplicate field information between _SHF & _MSK definitions, and keep the fields next to the register accessors, it will be much easier to spot & prevent any similar oddities being introduced in the future. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Thomas Gleixner <tglx@linutronix.de Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/17001/ Patchwork: https://patchwork.linux-mips.org/patch/17216/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-08-12 20:49:27 -06:00
gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN;
MIPS: traps: Ensure L1 & L2 ECC checking match for CM3 systems On systems with CM3, we must ensure that the L1 & L2 ECC enables are set to the same value. This is presumed by the hardware & cache corruption can occur when it is not the case. Support enabling & disabling the L2 ECC checking on CM3 systems where this is controlled via a GCR, and ensure that it matches the state of L1 ECC checking. Remove I6400 from the switch statement it will no longer hit, and which was incorrect since the L2 ECC enable bit isn't in the CP0 ErrCtl register. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14413/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-10-17 09:01:07 -06:00
WARN_ON(!!gcr_ectl != l2parity);
pr_info("Cache parity protection %sabled\n",
l1parity ? "en" : "dis");
return;
}
[MIPS] Allow hardwiring of the CPU type to a single type for optimization. This saves a few k on systems which only ever ship with a single CPU type. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 16:46:15 -06:00
switch (current_cpu_type()) {
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
case CPU_24K:
[MIPS] Add missing 34K processor IDs The 34K is very much like a 24K on steroids. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-27 08:50:32 -06:00
case CPU_34K:
[MIPS] Add support for MIPS CMP platform. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 10:14:26 -06:00
case CPU_74K:
case CPU_1004K:
MIPS: Add 1074K CPU support explicitly. The 1074K is a multiprocessing coherent processing system (CPS) based on modified 74K cores. This patch makes the 1074K an actual unique CPU type, instead of a 74K derivative, which it is not. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6389/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-17 14:03:50 -07:00
case CPU_1074K:
MIPS: Add support for interAptiv cores The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6163/
2013-11-27 03:07:53 -07:00
case CPU_INTERAPTIV:
MIPS: Add support for the proAptiv cores The proAptiv Multiprocessing System is a power efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The proAptiv Multiprocessing System combines a deep pipeline with multi-issue out of order execution for improved computational throughput. The proAptiv Multiprocessing System can contain one to six MIPS32r3 proAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6134/
2013-11-14 09:12:27 -07:00
case CPU_PROAPTIV:
MIPS: Add cases for CPU_P5600 Add a CPU_P5600 case to various switch statements, doing the same thing as for CPU_PROAPTIV. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6408/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-01-22 09:19:38 -07:00
case CPU_P5600:
MIPS: Add cases for CPU_QEMU_GENERIC Add a CPU_QEMU_GENERIC case to various switch statements. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-11-24 05:59:01 -07:00
case CPU_QEMU_GENERIC:
MIPS: Add P6600 cases to CPU switch statements Add cases supporting the P6600 CPU to various switch statements in core MIPS kernel code that define behaviour dependent upon the CPU. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Joshua Kinard <kumba@gentoo.org> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Petri Gynther <pgynther@google.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12343/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-02-02 20:26:38 -07:00
case CPU_P6600:
[MIPS] Add support for MIPS CMP platform. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-28 10:14:26 -06:00
{
unsigned long errctl;
unsigned int l1parity_present, l2parity_present;
errctl = read_c0_ecc();
errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
/* probe L1 parity support */
write_c0_ecc(errctl | ERRCTL_PE);
back_to_back_c0_hazard();
l1parity_present = (read_c0_ecc() & ERRCTL_PE);
/* probe L2 parity support */
write_c0_ecc(errctl|ERRCTL_L2P);
back_to_back_c0_hazard();
l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
if (l1parity_present && l2parity_present) {
if (l1parity)
errctl |= ERRCTL_PE;
if (l1parity ^ l2parity)
errctl |= ERRCTL_L2P;
} else if (l1parity_present) {
if (l1parity)
errctl |= ERRCTL_PE;
} else if (l2parity_present) {
if (l2parity)
errctl |= ERRCTL_L2P;
} else {
/* No parity available */
}
printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
write_c0_ecc(errctl);
back_to_back_c0_hazard();
errctl = read_c0_ecc();
printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
if (l1parity_present)
printk(KERN_INFO "Cache parity protection %sabled\n",
(errctl & ERRCTL_PE) ? "en" : "dis");
if (l2parity_present) {
if (l1parity_present && l1parity)
errctl ^= ERRCTL_L2P;
printk(KERN_INFO "L2 cache parity protection %sabled\n",
(errctl & ERRCTL_L2P) ? "en" : "dis");
}
}
break;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
case CPU_5KC:
MIPS: Don't panic on 5KEc. It's a bloody bog standard MIPS64R2 core with just a new PrId ID. Iow that essentially means Linux just panics because it doesn't know how to name the core. [ralf@linux-mips.org: Split original patch into several smaller patches.] Signed-off-by: Leonid Yegoshin <yegoshin@mips.com> Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3792/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-07-06 13:56:01 -06:00
case CPU_5KE:
MIPS: Add CPU support for Loongson1B Loongson 1B is a 32-bit SoC designed by Institute of Computing Technology (ICT) and the Chinese Academy of Sciences (CAS), which implements the MIPS32 release 2 instruction set. [ralf@linux-mips.org: But which is not strictly a MIPS32 compliant device which also is why it identifies itself with the Legacy Vendor ID in the PrID register. When applying the patch I shoveled some code around to keep things in alphabetical order and avoid forward declarations.] Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: To: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: wuzhangjin@gmail.com Cc: zhzhl555@gmail.com Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/3976/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-06-20 13:05:32 -06:00
case CPU_LOONGSON1:
On 24K we did always disable cache parity protection - obviously not the greatest thing to do. Try to enable parity protection, check if we actually succeeded and print a message about the outcome of this. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-03-01 11:15:08 -07:00
write_c0_ecc(0x80000000);
back_to_back_c0_hazard();
/* Set the PE bit (bit 31) in the c0_errctl register. */
printk(KERN_INFO "Cache parity protection %sabled\n",
(read_c0_ecc() & 0x80000000) ? "en" : "dis");
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
break;
case CPU_20KC:
case CPU_25KF:
/* Clear the DE bit (bit 16) in the c0_status register. */
printk(KERN_INFO "Enable cache parity protection for "
"MIPS 20KC/25KF CPUs.\n");
clear_c0_status(ST0_DE);
break;
default:
break;
}
}
asmlinkage void cache_parity_error(void)
{
const int field = 2 * sizeof(unsigned long);
unsigned int reg_val;
/* For the moment, report the problem and hang. */
printk("Cache error exception:\n");
printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
reg_val = read_c0_cacheerr();
printk("c0_cacheerr == %08x\n", reg_val);
printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
reg_val & (1<<30) ? "secondary" : "primary",
reg_val & (1<<31) ? "data" : "insn");
MIPS: kernel: traps: Add MIPS R6 related definitions Add MIPS R6 support to cache and ftlb exceptions, as well as to the hwrena and ebase register configuration. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-11-14 04:25:30 -07:00
if ((cpu_has_mips_r2_r6) &&
MIPS: Fix typo when reporting cache and ftlb errors for ImgTec cores Introduced by the following two commits: 75b5b5e0a262790fa11043fe45700499c7e3d818 "MIPS: Add support for FTLBs" 6de20451857ed14a4eecc28d08f6de5925d1cf96 "MIPS: Add printing of ES bit for Imgtec cores when cache error occurs" Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Reported-by: Matheus Almeida <Matheus.Almeida@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: stable@vger.kernel.org # v3.14+ Patchwork: https://patchwork.linux-mips.org/patch/6980/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-05-21 05:35:00 -06:00
((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
MIPS: Add printing of ES bit for Imgtec cores when cache error occurs. The cacheer register is always implemented in the same way in the MIPS32r2 Imgtec cores so print the ES bit when an cache error occurs. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6041/
2013-10-10 02:58:59 -06:00
pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
reg_val & (1<<29) ? "ED " : "",
reg_val & (1<<28) ? "ET " : "",
reg_val & (1<<27) ? "ES " : "",
reg_val & (1<<26) ? "EE " : "",
reg_val & (1<<25) ? "EB " : "",
reg_val & (1<<24) ? "EI " : "",
reg_val & (1<<23) ? "E1 " : "",
reg_val & (1<<22) ? "E0 " : "");
} else {
pr_err("Error bits: %s%s%s%s%s%s%s\n",
reg_val & (1<<29) ? "ED " : "",
reg_val & (1<<28) ? "ET " : "",
reg_val & (1<<26) ? "EE " : "",
reg_val & (1<<25) ? "EB " : "",
reg_val & (1<<24) ? "EI " : "",
reg_val & (1<<23) ? "E1 " : "",
reg_val & (1<<22) ? "E0 " : "");
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
Fixup a few lose ends in explicit support for MIPS R1/R2. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-07 09:58:15 -06:00
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
if (reg_val & (1<<22))
printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
if (reg_val & (1<<23))
printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
#endif
panic("Can't handle the cache error!");
}
MIPS: Add support for FTLBs The Fixed Page Size TLB (FTLB) is a set-associative dual entry TLB. Its purpose is to reduce the number of TLB misses by increasing the effective TLB size and keep the implementation complexity to minimum levels. A supported core can have both VTLB and FTLB. Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6139/
2013-11-14 09:12:31 -07:00
asmlinkage void do_ftlb(void)
{
const int field = 2 * sizeof(unsigned long);
unsigned int reg_val;
/* For the moment, report the problem and hang. */
MIPS: kernel: traps: Add MIPS R6 related definitions Add MIPS R6 support to cache and ftlb exceptions, as well as to the hwrena and ebase register configuration. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-11-14 04:25:30 -07:00
if ((cpu_has_mips_r2_r6) &&
MIPS: Loongson: Add Loongson-3A R2 basic support Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R2 revision of Loongson-3A: - Primary cache includes I-Cache, D-Cache and V-Cache (Victim Cache). - I-Cache, D-Cache and V-Cache are 16-way set-associative, linesize is 64 bytes. - 64 entries of VTLB (classic TLB), 1024 entries of FTLB (8-way set-associative). - Supports DSP/DSPv2 instructions, UserLocal register and Read-Inhibit/ Execute-Inhibit. [ralf@linux-mips.org: Resolved merge conflicts.] Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12751/ Patchwork: https://patchwork.linux-mips.org/patch/13136/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-03-02 18:45:09 -07:00
(((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
MIPS: Add support for FTLBs The Fixed Page Size TLB (FTLB) is a set-associative dual entry TLB. Its purpose is to reduce the number of TLB misses by increasing the effective TLB size and keep the implementation complexity to minimum levels. A supported core can have both VTLB and FTLB. Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6139/
2013-11-14 09:12:31 -07:00
pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
read_c0_ecc());
pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
reg_val = read_c0_cacheerr();
pr_err("c0_cacheerr == %08x\n", reg_val);
if ((reg_val & 0xc0000000) == 0xc0000000) {
pr_err("Decoded c0_cacheerr: FTLB parity error\n");
} else {
pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
reg_val & (1<<30) ? "secondary" : "primary",
reg_val & (1<<31) ? "data" : "insn");
}
} else {
pr_err("FTLB error exception\n");
}
/* Just print the cacheerr bits for now */
cache_parity_error();
}
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
* SDBBP EJTAG debug exception handler.
* We skip the instruction and return to the next instruction.
*/
void ejtag_exception_handler(struct pt_regs *regs)
{
const int field = 2 * sizeof(unsigned long);
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
unsigned long depc, old_epc, old_ra;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
unsigned int debug;
[MIPS] Use KERN_DEBUG to log the SDBBP messages Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-30 05:32:37 -06:00
printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
depc = read_c0_depc();
debug = read_c0_debug();
[MIPS] Use KERN_DEBUG to log the SDBBP messages Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-30 05:32:37 -06:00
printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
if (debug & 0x80000000) {
/*
* In branch delay slot.
* We cheat a little bit here and use EPC to calculate the
* debug return address (DEPC). EPC is restored after the
* calculation.
*/
old_epc = regs->cp0_epc;
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
old_ra = regs->regs[31];
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
regs->cp0_epc = depc;
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
compute_return_epc(regs);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
depc = regs->cp0_epc;
regs->cp0_epc = old_epc;
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
regs->regs[31] = old_ra;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
} else
depc += 4;
write_c0_depc(depc);
#if 0
[MIPS] Use KERN_DEBUG to log the SDBBP messages Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-30 05:32:37 -06:00
printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
write_c0_debug(debug | 0x100);
#endif
}
/*
* NMI exception handler.
MIPS: Add NMI notifier Allow the board support code to register a raw notifier callback for NMI, similar to what is done for CU2 exceptions. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2958/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-11-15 18:25:44 -07:00
* No lock; only written during early bootup by CPU 0.
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
*/
MIPS: Add NMI notifier Allow the board support code to register a raw notifier callback for NMI, similar to what is done for CU2 exceptions. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2958/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-11-15 18:25:44 -07:00
static RAW_NOTIFIER_HEAD(nmi_chain);
int register_nmi_notifier(struct notifier_block *nb)
{
return raw_notifier_chain_register(&nmi_chain, nb);
}
treewide: convert uses of ATTRIB_NORETURN to __noreturn Use the more commonly used __noreturn instead of ATTRIB_NORETURN. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: Joe Perches <joe@perches.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Haavard Skinnemoen <hskinnemoen@gmail.com> Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no> Cc: Tony Luck <tony.luck@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Chris Metcalf <cmetcalf@tilera.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2012-01-12 18:17:21 -07:00
void __noreturn nmi_exception_handler(struct pt_regs *regs)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
{
MIPS: Print correct PC in trace dump after NMI exception An NMI exception delivered from YAMON delivers the PC in ErrorPC instead of EPC. It's also necessary to clear the Status.BEV bit for the page fault exception handler to work properly. [ralf@linux-mips: Let the assembler do the loading of the mask value rather than the convoluted explicit %hi/%lo manual relocation sequence from the original patch.] Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6035/ Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6084/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-10-08 05:39:31 -06:00
char str[100];
MIPS: add nmi_enter() + nmi_exit() to nmi_exception_handler() We need to enter NMI context when NMI interrupt fires. Signed-off-by: Petri Gynther <pgynther@google.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11323/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-10-19 12:49:52 -06:00
nmi_enter();
MIPS: Add NMI notifier Allow the board support code to register a raw notifier callback for NMI, similar to what is done for CU2 exceptions. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2958/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-11-15 18:25:44 -07:00
raw_notifier_call_chain(&nmi_chain, 0, regs);
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 02:45:45 -06:00
bust_spinlocks(1);
MIPS: Print correct PC in trace dump after NMI exception An NMI exception delivered from YAMON delivers the PC in ErrorPC instead of EPC. It's also necessary to clear the Status.BEV bit for the page fault exception handler to work properly. [ralf@linux-mips: Let the assembler do the loading of the mask value rather than the convoluted explicit %hi/%lo manual relocation sequence from the original patch.] Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6035/ Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6084/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-10-08 05:39:31 -06:00
snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
smp_processor_id(), regs->cp0_epc);
regs->cp0_epc = read_c0_errorepc();
die(str, regs);
MIPS: add nmi_enter() + nmi_exit() to nmi_exception_handler() We need to enter NMI context when NMI interrupt fires. Signed-off-by: Petri Gynther <pgynther@google.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11323/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-10-19 12:49:52 -06:00
nmi_exit();
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
#define VECTORSPACING 0x100 /* for EI/VI mode */
unsigned long ebase;
MIPS: KVM: Restore host EBase from ebase variable The host kernel's exception vector base address is currently saved in the VCPU structure at creation time, and restored on a guest exit. However it doesn't change and can already be easily accessed from the 'ebase' variable (arch/mips/kernel/traps.c), so drop the host_ebase member of kvm_vcpu_arch, export the 'ebase' variable to modules and load from there instead. This does result in a single extra instruction (lui) on the guest exit path, but simplifies the code a bit and removes the redundant storage of the host exception base address. Credit for the idea goes to Cavium's VZ KVM implementation. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-09 07:19:14 -06:00
EXPORT_SYMBOL_GPL(ebase);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
unsigned long exception_handlers[32];
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
unsigned long vi_handlers[64];
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: Annotate set_except_vector with __init All call sites of set_except_vector are already annotated with __init, so annotate that one too. Signed-off-by: Regards, Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org To: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/888/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-01-28 07:21:42 -07:00
void __init *set_except_vector(int n, void *addr)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
{
unsigned long handler = (unsigned long) addr;
Merge branch 'mti-next' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
2013-05-09 09:57:30 -06:00
unsigned long old_handler;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
#ifdef CONFIG_CPU_MICROMIPS
/*
* Only the TLB handlers are cache aligned with an even
* address. All other handlers are on an odd address and
* require no modification. Otherwise, MIPS32 mode will
* be entered when handling any TLB exceptions. That
* would be bad...since we must stay in microMIPS mode.
*/
if (!(handler & 0x1))
handler |= 1;
#endif
Merge branch 'mti-next' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
2013-05-09 09:57:30 -06:00
old_handler = xchg(&exception_handlers[n], handler);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
if (n == 0 && cpu_has_divec) {
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
#ifdef CONFIG_CPU_MICROMIPS
unsigned long jump_mask = ~((1 << 27) - 1);
#else
MIPS: Deal with larger physical offsets AR7 has a larger physical offset than other MIPS based systems and therefore needs to setup its handlers beyond the usual KSEG0 range. When running the kernel in mapped mode this modification is also required. Remove function comment which is now incorrect. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Eugene Konev <ejka@imfi.kspu.ru> Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org To: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/889/ Patchwork: http://patchwork.linux-mips.org/patch/932/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-01-28 07:22:37 -07:00
unsigned long jump_mask = ~((1 << 28) - 1);
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
#endif
MIPS: Deal with larger physical offsets AR7 has a larger physical offset than other MIPS based systems and therefore needs to setup its handlers beyond the usual KSEG0 range. When running the kernel in mapped mode this modification is also required. Remove function comment which is now incorrect. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Eugene Konev <ejka@imfi.kspu.ru> Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org To: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/889/ Patchwork: http://patchwork.linux-mips.org/patch/932/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-01-28 07:22:37 -07:00
u32 *buf = (u32 *)(ebase + 0x200);
unsigned int k0 = 26;
if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
uasm_i_j(&buf, handler & ~jump_mask);
uasm_i_nop(&buf);
} else {
UASM_i_LA(&buf, k0, handler);
uasm_i_jr(&buf, k0);
uasm_i_nop(&buf);
}
local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
}
return (void *)old_handler;
}
MIPS: Make tlb exception handler definitions and declarations match. The code was written as it is because it's more expressive, a bit easier. But it's always been dirty, if not a bug. But we can't cheat with LTO compilers, so this results in: [...] LDFINAL vmlinux.o In file included from arch/mips/kernel/topology.c:604:0, from arch/mips/kernel/time.c:212, from arch/mips/kernel/syscall.c:300, from arch/mips/kernel/signal.c:853, from arch/mips/kernel/setup.c:1030, from arch/mips/kernel/reset.c:354, from arch/mips/kernel/ptrace.c:562, from arch/mips/kernel/process.c:770, from arch/mips/kernel/irq.c:350, from arch/mips/kernel/branch.c:321, from arch/mips/kernel/cpu-probe.c:1370, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/thread_info.h:345, from arch/mips/sgi-ip22/ip22-gio.c:660, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/sgialib.h:219, from arch/mips/sgi-ip22/ip22-reset.c:224, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/paccess.h:116, from arch/mips/sgi-ip22/ip22-nvram.c:334, from include/linux/kernel_stat.h:79, from arch/mips/sgi-ip22/ip22-int.c:592, from arch/mips/sgi-ip22/ip22-hpc.c:470, from arch/mips/sgi-ip22/ip22-mc.c:135, from init/init_task.c:54, from init/calibrate.c:744, from init/noinitramfs.c:62, from init/do_mounts.c:573, from init/version.c:1009, from init/main.c:777, from :729: arch/mips/kernel/traps.c:63:49: error: variable ‘handle_tlbl’ redeclared as function In file included from arch/mips/mm/page.c:310:0, from arch/mips/mm/mmap.c:208, from arch/mips/mm/init.c:641, from arch/mips/mm/gup.c:811, from arch/mips/mm/fault.c:659, from include/linux/module.h:682, from arch/mips/mm/dma-default.c:161, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/thread_info.h:397, from arch/mips/kernel/i8253.c:538, from arch/mips/kernel/proc.c:145, from arch/mips/kernel/irq_cpu.c:129, from arch/mips/kernel/i8259.c:229, from include/uapi/linux/elf.h:251, from arch/mips/kernel/mips_ksyms.c:129, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/time.h:50, from arch/mips/kernel/cevt-r4k.c:90, from arch/mips/kernel/vdso.c:136, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/thread_info.h:351, from arch/mips/kernel/unaligned.c:809, from arch/mips/kernel/traps.c:1720, from arch/mips/kernel/topology.c:684, from arch/mips/kernel/time.c:212, from arch/mips/kernel/syscall.c:300, from arch/mips/kernel/signal.c:853, from arch/mips/kernel/setup.c:1030, from arch/mips/kernel/reset.c:354, from arch/mips/kernel/ptrace.c:562, from arch/mips/kernel/process.c:770, from arch/mips/kernel/irq.c:350, from arch/mips/kernel/branch.c:321, from arch/mips/kernel/cpu-probe.c:1370, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/thread_info.h:345, from arch/mips/sgi-ip22/ip22-gio.c:660, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/sgialib.h:219, from arch/mips/sgi-ip22/ip22-reset.c:224, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/paccess.h:116, from arch/mips/sgi-ip22/ip22-nvram.c:334, from include/linux/kernel_stat.h:79, from arch/mips/sgi-ip22/ip22-int.c:592, from arch/mips/sgi-ip22/ip22-hpc.c:470, from arch/mips/sgi-ip22/ip22-mc.c:135, from init/init_task.c:54, from init/calibrate.c:744, from init/noinitramfs.c:62, from init/do_mounts.c:573, from init/version.c:1009, from init/main.c:777, from :729: arch/mips/mm/tlbex.c:1448:5: note: previously declared here In file included from arch/mips/kernel/topology.c:604:0, from arch/mips/kernel/time.c:212, from arch/mips/kernel/syscall.c:300, from arch/mips/kernel/signal.c:853, from arch/mips/kernel/setup.c:1030, from arch/mips/kernel/reset.c:354, from arch/mips/kernel/ptrace.c:562, from arch/mips/kernel/process.c:770, from arch/mips/kernel/irq.c:350, from arch/mips/kernel/branch.c:321, from arch/mips/kernel/cpu-probe.c:1370, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/thread_info.h:345, from arch/mips/sgi-ip22/ip22-gio.c:660, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/sgialib.h:219, from arch/mips/sgi-ip22/ip22-reset.c:224, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/paccess.h:116, from arch/mips/sgi-ip22/ip22-nvram.c:334, from include/linux/kernel_stat.h:79, from arch/mips/sgi-ip22/ip22-int.c:592, from arch/mips/sgi-ip22/ip22-hpc.c:470, from arch/mips/sgi-ip22/ip22-mc.c:135, from init/init_task.c:54, from init/calibrate.c:744, from init/noinitramfs.c:62, from init/do_mounts.c:573, from init/version.c:1009, from init/main.c:777, from :729: arch/mips/kernel/traps.c:62:49: error: variable ‘handle_tlbm’ redeclared as function In file included from arch/mips/mm/page.c:310:0, from arch/mips/mm/mmap.c:208, from arch/mips/mm/init.c:641, from arch/mips/mm/gup.c:811, from arch/mips/mm/fault.c:659, from include/linux/module.h:682, from arch/mips/mm/dma-default.c:161, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/thread_info.h:397, from arch/mips/kernel/i8253.c:538, from arch/mips/kernel/proc.c:145, from arch/mips/kernel/irq_cpu.c:129, from arch/mips/kernel/i8259.c:229, from include/uapi/linux/elf.h:251, from arch/mips/kernel/mips_ksyms.c:129, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/time.h:50, from arch/mips/kernel/cevt-r4k.c:90, from arch/mips/kernel/vdso.c:136, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/thread_info.h:351, from arch/mips/kernel/unaligned.c:809, from arch/mips/kernel/traps.c:1720, from arch/mips/kernel/topology.c:684, from arch/mips/kernel/time.c:212, from arch/mips/kernel/syscall.c:300, from arch/mips/kernel/signal.c:853, from arch/mips/kernel/setup.c:1030, from arch/mips/kernel/reset.c:354, from arch/mips/kernel/ptrace.c:562, from arch/mips/kernel/process.c:770, from arch/mips/kernel/irq.c:350, from arch/mips/kernel/branch.c:321, from arch/mips/kernel/cpu-probe.c:1370, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/thread_info.h:345, from arch/mips/sgi-ip22/ip22-gio.c:660, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/sgialib.h:219, from arch/mips/sgi-ip22/ip22-reset.c:224, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/paccess.h:116, from arch/mips/sgi-ip22/ip22-nvram.c:334, from include/linux/kernel_stat.h:79, from arch/mips/sgi-ip22/ip22-int.c:592, from arch/mips/sgi-ip22/ip22-hpc.c:470, from arch/mips/sgi-ip22/ip22-mc.c:135, from init/init_task.c:54, from init/calibrate.c:744, from init/noinitramfs.c:62, from init/do_mounts.c:573, from init/version.c:1009, from init/main.c:777, from :729: arch/mips/mm/tlbex.c:1450:5: note: previously declared here In file included from arch/mips/kernel/topology.c:604:0, from arch/mips/kernel/time.c:212, from arch/mips/kernel/syscall.c:300, from arch/mips/kernel/signal.c:853, from arch/mips/kernel/setup.c:1030, from arch/mips/kernel/reset.c:354, from arch/mips/kernel/ptrace.c:562, from arch/mips/kernel/process.c:770, from arch/mips/kernel/irq.c:350, from arch/mips/kernel/branch.c:321, from arch/mips/kernel/cpu-probe.c:1370, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/thread_info.h:345, from arch/mips/sgi-ip22/ip22-gio.c:660, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/sgialib.h:219, from arch/mips/sgi-ip22/ip22-reset.c:224, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/paccess.h:116, from arch/mips/sgi-ip22/ip22-nvram.c:334, from include/linux/kernel_stat.h:79, from arch/mips/sgi-ip22/ip22-int.c:592, from arch/mips/sgi-ip22/ip22-hpc.c:470, from arch/mips/sgi-ip22/ip22-mc.c:135, from init/init_task.c:54, from init/calibrate.c:744, from init/noinitramfs.c:62, from init/do_mounts.c:573, from init/version.c:1009, from init/main.c:777, from :729: arch/mips/kernel/traps.c:64:49: error: variable ‘handle_tlbs’ redeclared as function In file included from arch/mips/mm/page.c:310:0, from arch/mips/mm/mmap.c:208, from arch/mips/mm/init.c:641, from arch/mips/mm/gup.c:811, from arch/mips/mm/fault.c:659, from include/linux/module.h:682, from arch/mips/mm/dma-default.c:161, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/thread_info.h:397, from arch/mips/kernel/i8253.c:538, from arch/mips/kernel/proc.c:145, from arch/mips/kernel/irq_cpu.c:129, from arch/mips/kernel/i8259.c:229, from include/uapi/linux/elf.h:251, from arch/mips/kernel/mips_ksyms.c:129, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/time.h:50, from arch/mips/kernel/cevt-r4k.c:90, from arch/mips/kernel/vdso.c:136, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/thread_info.h:351, from arch/mips/kernel/unaligned.c:809, from arch/mips/kernel/traps.c:1720, from arch/mips/kernel/topology.c:684, from arch/mips/kernel/time.c:212, from arch/mips/kernel/syscall.c:300, from arch/mips/kernel/signal.c:853, from arch/mips/kernel/setup.c:1030, from arch/mips/kernel/reset.c:354, from arch/mips/kernel/ptrace.c:562, from arch/mips/kernel/process.c:770, from arch/mips/kernel/irq.c:350, from arch/mips/kernel/branch.c:321, from arch/mips/kernel/cpu-probe.c:1370, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/thread_info.h:345, from arch/mips/sgi-ip22/ip22-gio.c:660, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/sgialib.h:219, from arch/mips/sgi-ip22/ip22-reset.c:224, from /fluff/home/ralf/src/linux/lto/linux-misc/arch/mips/include/asm/paccess.h:116, from arch/mips/sgi-ip22/ip22-nvram.c:334, from include/linux/kernel_stat.h:79, from arch/mips/sgi-ip22/ip22-int.c:592, from arch/mips/sgi-ip22/ip22-hpc.c:470, from arch/mips/sgi-ip22/ip22-mc.c:135, from init/init_task.c:54, from init/calibrate.c:744, from init/noinitramfs.c:62, from init/do_mounts.c:573, from init/version.c:1009, from init/main.c:777, from :729: arch/mips/mm/tlbex.c:1449:5: note: previously declared here lto1: fatal error: errors during merging of translation units compilation terminated. lto-wrapper: /usr/bin/mips-linux-gcc returned 1 exit status /usr/lib64/gcc/mips-linux/4.7.1/../../../../mips-linux/bin/ld: lto-wrapper failed collect2: error: ld returned 1 exit status make: *** [vmlinux] Error 1 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-07 17:21:34 -07:00
static void do_default_vi(void)
[MIPS] Fix warning by moving do_default_vi into CONFIG_CPU_MIPSR2_SRS This fixes the warning: arch/mips/kernel/traps.c:931: warning: 'do_default_vi' defined but not used Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-05-21 08:45:38 -06:00
{
show_regs(get_irq_regs());
panic("Caught unexpected vectored interrupt.");
}
[MIPS] Define and use vi_handler_t for vectored interrupt handlers. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-05-06 11:31:18 -06:00
static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
{
unsigned long handler;
unsigned long old_handler = vi_handlers[n];
[MIPS] Fix shadow register support. Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-08 11:02:29 -07:00
int srssets = current_cpu_data.srsets;
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
u16 *h;
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
unsigned char *b;
MIPS: Use BUG_ON() where possible. Based on original patch by Stoyan Gaydarov <stoyboyker@gmail.com> which missed a few places. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-30 06:49:44 -06:00
BUG_ON(!cpu_has_veic && !cpu_has_vint);
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
if (addr == NULL) {
handler = (unsigned long) do_default_vi;
srs = 0;
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 02:45:45 -06:00
} else
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
handler = (unsigned long) addr;
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
vi_handlers[n] = handler;
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
[MIPS] Fix shadow register support. Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-08 11:02:29 -07:00
if (srs >= srssets)
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
panic("Shadow register set %d not supported", srs);
if (cpu_has_veic) {
if (board_bind_eic_interrupt)
[MIPS] Fix "no space between function name and open parenthesis" warnings. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 16:46:15 -06:00
board_bind_eic_interrupt(n, srs);
[MIPS] MT: Improved multithreading support. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-05 02:45:45 -06:00
} else if (cpu_has_vint) {
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
/* SRSMap is only defined if shadow sets are implemented */
[MIPS] Fix shadow register support. Shadow register support would not possibly have worked on multicore systems. The support code for it was also depending not on MIPS R2 but VSMP or SMTC kernels even though it makes perfect sense with UP kernels. SR sets are a scarce resource and the expected usage pattern is that users actually hardcode the register set numbers in their code. So fix the allocator by ditching it. Move the remaining CPU probe bits into the generic CPU probe. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-08 11:02:29 -07:00
if (srssets > 1)
[MIPS] Fix "no space between function name and open parenthesis" warnings. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 16:46:15 -06:00
change_c0_srsmap(0xf << n*4, srs << n*4);
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
}
if (srs == 0) {
/*
* If no shadow set is selected then use the default handler
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
* that does normal register saving and standard interrupt exit
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
*/
extern char except_vec_vi, except_vec_vi_lui;
extern char except_vec_vi_ori, except_vec_vi_end;
[MIPS] Fix potential latency problem due to non-atomic cpu_wait. If an interrupt happened between checking of NEED_RESCHED and WAIT instruction, adjust EPC to restart from checking of NEED_RESCHED. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-11 10:05:18 -07:00
extern char rollback_except_vec_vi;
MIPS: Idle: Do address fiddlery in helper functions. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-21 09:30:36 -06:00
char *vec_start = using_rollback_handler() ?
[MIPS] Fix potential latency problem due to non-atomic cpu_wait. If an interrupt happened between checking of NEED_RESCHED and WAIT instruction, adjust EPC to restart from checking of NEED_RESCHED. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-11 10:05:18 -07:00
&rollback_except_vec_vi : &except_vec_vi;
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
const int lui_offset = &except_vec_vi_lui - vec_start + 2;
const int ori_offset = &except_vec_vi_ori - vec_start + 2;
#else
[MIPS] Fix potential latency problem due to non-atomic cpu_wait. If an interrupt happened between checking of NEED_RESCHED and WAIT instruction, adjust EPC to restart from checking of NEED_RESCHED. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-11 10:05:18 -07:00
const int lui_offset = &except_vec_vi_lui - vec_start;
const int ori_offset = &except_vec_vi_ori - vec_start;
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
#endif
const int handler_len = &except_vec_vi_end - vec_start;
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
if (handler_len > VECTORSPACING) {
/*
* Sigh... panicing won't help as the console
* is probably not configured :(
*/
[MIPS] Fix "no space between function name and open parenthesis" warnings. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 16:46:15 -06:00
panic("VECTORSPACING too small");
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
}
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
set_handler(((unsigned long)b - ebase), vec_start,
#ifdef CONFIG_CPU_MICROMIPS
(handler_len - 1));
#else
handler_len);
#endif
h = (u16 *)(b + lui_offset);
*h = (handler >> 16) & 0xffff;
h = (u16 *)(b + ori_offset);
*h = (handler & 0xffff);
[MIPS] Fix WARNING: at kernel/smp.c:290 trap_init issues flush_icache_range(), which uses ipi functions to get icache flushing done on all cpus. But this is done before interrupts are enabled and caused WARN_ON messages. This changeset introduces a new local_flush_icache_range() and uses it before interrupts (and additional CPUs) are enabled to avoid this problem. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-08-04 12:53:57 -06:00
local_flush_icache_range((unsigned long)b,
(unsigned long)(b+handler_len));
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
}
else {
/*
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
* In other cases jump directly to the interrupt handler. It
* is the handler's responsibility to save registers if required
* (eg hi/lo) and return from the exception using "eret".
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
*/
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
u32 insn;
h = (u16 *)b;
/* j handler */
#ifdef CONFIG_CPU_MICROMIPS
insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
#else
insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
#endif
h[0] = (insn >> 16) & 0xffff;
h[1] = insn & 0xffff;
h[2] = 0;
h[3] = 0;
[MIPS] Fix WARNING: at kernel/smp.c:290 trap_init issues flush_icache_range(), which uses ipi functions to get icache flushing done on all cpus. But this is done before interrupts are enabled and caused WARN_ON messages. This changeset introduces a new local_flush_icache_range() and uses it before interrupts (and additional CPUs) are enabled to avoid this problem. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-08-04 12:53:57 -06:00
local_flush_icache_range((unsigned long)b,
(unsigned long)(b+8));
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
return (void *)old_handler;
}
[MIPS] Define and use vi_handler_t for vectored interrupt handlers. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-05-06 11:31:18 -06:00
void *set_vi_handler(int n, vi_handler_t addr)
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
{
[MIPS] Some formatting fixes. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-29 06:12:58 -07:00
return set_vi_srs_handler(n, addr, 0);
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
}
[MIPS] Fix configuration of R2 CPU features and multithreading. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-05 10:24:46 -06:00
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
extern void tlb_init(void);
[MIPS] time: Move R4000 clockevent device code to separate configurable file Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-18 10:48:11 -06:00
/*
* Timer interrupt
*/
int cp0_compare_irq;
MIPS: Oprofile: Fix build as a module. When building oprofile as a module for R10000 or R7000 class processors, E9000 or MIPSxx class cores since 3572a2c37f667ee49333f8863722b8f43eac506b [MIPS: make oprofile use cp0_perfcount_irq if it is set] an ERROR: "cp0_compare_irq" [arch/mips/oprofile/oprofile.ko] undefined! error will happen. Fixed by exporting cp0_compare_irq. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-07-19 01:13:52 -06:00
EXPORT_SYMBOL_GPL(cp0_compare_irq);
MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs The MIPS processor is limited to 64 external interrupt sources. Using a greater number without IRQ sharing requires reading platform-specific registers. On such platforms, reading the IntCtl register to determine which interrupt corresponds to a timer interrupt will not work. On MIPSR2 systems there is a solution - the TI bit in the Cause register, specifically indicates that a timer interrupt has occured. This patch uses that bit to detect interrupts for MIPSR2 processors, which may be expected to work regardless of how the timer interrupt may be routed in the hardware. Signed-off-by: David VomLehn (dvomlehn@cisco.com) To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/804/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-12-21 18:49:22 -07:00
int cp0_compare_irq_shift;
[MIPS] time: Move R4000 clockevent device code to separate configurable file Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-18 10:48:11 -06:00
/*
* Performance counter IRQ or -1 if shared with timer
*/
int cp0_perfcount_irq;
EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
MIPS: Read CPU IRQ line that FDC to routed to Read the CPU IRQ line reportedly used for the Fast Debug Channel (FDC) interrupt from the IntCtl register and store it in cp0_fdc_irq where platform implementations of the new weak platform function get_c0_fdc_int() can refer to it. [ralf@linux-mips.org: Fixed conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/9140/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-29 04:14:07 -07:00
/*
* Fast debug channel IRQ or -1 if not present
*/
int cp0_fdc_irq;
EXPORT_SYMBOL_GPL(cp0_fdc_irq);
MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code commit 3747069b25e419f6b51395f48127e9812abc3596 upstream. The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. Here, we remove all the MIPS __cpuinit from C code and __CPUINIT from asm files. MIPS is interesting in this respect, because there are also uasm users hiding behind their own renamed versions of the __cpuinit macros. [1] https://lkml.org/lkml/2013/5/20/589 [ralf@linux-mips.org: Folded in Paul's followup fix.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5494/ Patchwork: https://patchwork.linux-mips.org/patch/5495/ Patchwork: https://patchwork.linux-mips.org/patch/5509/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-18 07:38:59 -06:00
static int noulri;
[MIPS] Add noulri kernel argument to disable "rdhwr $29" usermode support. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-03 03:43:56 -06:00
static int __init ulri_disable(char *s)
{
pr_info("Disabling ulri\n");
noulri = 1;
return 1;
}
__setup("noulri", ulri_disable);
MIPS: traps: Add CPU PM callback for trap configuration Implement a CPU power management callback for restoring trap related CPU configuration after CPU power up from a low power state. The following state is restored: - Status register - HWREna register - Exception vector configuration registers - Context/XContext register Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-03-04 03:20:43 -07:00
/* configure STATUS register */
static void configure_status(void)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
{
/*
* Disable coprocessors and select 32-bit or 64-bit addressing
* and the 16/32 or 32/32 FPR register model. Reset the BEV
* flag that some firmware may have left set and the TS bit (for
* IP27). Set XX for ISA IV code to work.
*/
MIPS: traps: Add CPU PM callback for trap configuration Implement a CPU power management callback for restoring trap related CPU configuration after CPU power up from a low power state. The following state is restored: - Status register - HWREna register - Exception vector configuration registers - Context/XContext register Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-03-04 03:20:43 -07:00
unsigned int status_set = ST0_CU0;
[PATCH] mips: clean up 32/64-bit configuration Start cleaning 32-bit vs. 64-bit configuration. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-03 16:56:16 -06:00
#ifdef CONFIG_64BIT
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
#endif
MIPS: Fix ISA level which causes secondary cache init bypassing and more The commit a96102be70 introduced set_isa() where compatible ISA info is also set aside from the one gets passed in. It means, for example, 1004K will have MIPS_CPU_ISA_M32R2/M32R1/II/I flags. This leads to things like the following inappropriate: if (c->isa_level == MIPS_CPU_ISA_M32R1 || c->isa_level == MIPS_CPU_ISA_M32R2 || c->isa_level == MIPS_CPU_ISA_M64R1 || c->isa_level == MIPS_CPU_ISA_M64R2) This patch fixes it. Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-04-01 12:14:28 -06:00
if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
status_set |= ST0_XX;
[MIPS] Ensure that ST0_FR is never set on a 32 bit kernel Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-12-13 15:42:19 -07:00
if (cpu_has_dsp)
status_set |= ST0_MX;
[MIPS] Clear ST0_RE on bootup. The reset state is undefined and some firmware doesn't clear this bit possibly resulting in crashes on entry into userland. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-06 18:20:43 -07:00
change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
status_set);
MIPS: traps: Add CPU PM callback for trap configuration Implement a CPU power management callback for restoring trap related CPU configuration after CPU power up from a low power state. The following state is restored: - Status register - HWREna register - Exception vector configuration registers - Context/XContext register Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-03-04 03:20:43 -07:00
}
MIPS: KVM: Don't hardcode restored HWREna KVM modifies CP0_HWREna during guest execution so it can trap and emulate RDHWR instructions, however it always restores the hardcoded value 0x2000000F. This assumes the presence of the UserLocal register, and the absence of any implementation dependent or future HW registers. Fix by exporting the value that traps.c write into CP0_HWREna, and loading from there instead of hard coding. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-15 12:29:53 -06:00
unsigned int hwrena;
EXPORT_SYMBOL_GPL(hwrena);
MIPS: traps: Add CPU PM callback for trap configuration Implement a CPU power management callback for restoring trap related CPU configuration after CPU power up from a low power state. The following state is restored: - Status register - HWREna register - Exception vector configuration registers - Context/XContext register Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-03-04 03:20:43 -07:00
/* configure HWRENA register */
static void configure_hwrena(void)
{
MIPS: KVM: Don't hardcode restored HWREna KVM modifies CP0_HWREna during guest execution so it can trap and emulate RDHWR instructions, however it always restores the hardcoded value 0x2000000F. This assumes the presence of the UserLocal register, and the absence of any implementation dependent or future HW registers. Fix by exporting the value that traps.c write into CP0_HWREna, and loading from there instead of hard coding. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-15 12:29:53 -06:00
hwrena = cpu_hwrena_impl_bits;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: kernel: traps: Add MIPS R6 related definitions Add MIPS R6 support to cache and ftlb exceptions, as well as to the hwrena and ebase register configuration. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-11-14 04:25:30 -07:00
if (cpu_has_mips_r2_r6)
MIPS: Clean up RDHWR handling No preprocessor definitions are used in the handling of the registers accessible with the RDHWR instruction, nor the corresponding bits in the CP0 HWREna register. Add definitions for both the register numbers (MIPS_HWR_*) and HWREna bits (MIPS_HWRENA_*) in asm/mipsregs.h and make use of them in the initialisation of HWREna and emulation of the RDHWR instruction. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: David Daney <david.daney@cavium.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-15 12:29:52 -06:00
hwrena |= MIPS_HWRENA_CPUNUM |
MIPS_HWRENA_SYNCISTEP |
MIPS_HWRENA_CC |
MIPS_HWRENA_CCRES;
[MIPS] Enable support for the userlocal hardware register Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10 10:33:02 -06:00
MIPS: Allow UserLocal on MIPS_R1 processors Some MIPS32R1 processors implement UserLocal (RDHWR $29) to accelerate programs that make extensive use of thread-local storage. Therefore, setting up the HWRENA register should not depend on cpu_has_mips_r2. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
2010-10-16 15:22:38 -06:00
if (!noulri && cpu_has_userlocal)
MIPS: Clean up RDHWR handling No preprocessor definitions are used in the handling of the registers accessible with the RDHWR instruction, nor the corresponding bits in the CP0 HWREna register. Add definitions for both the register numbers (MIPS_HWR_*) and HWREna bits (MIPS_HWRENA_*) in asm/mipsregs.h and make use of them in the initialisation of HWREna and emulation of the RDHWR instruction. Signed-off-by: James Hogan <james.hogan@imgtec.com> Acked-by: Ralf Baechle <ralf@linux-mips.org> Cc: David Daney <david.daney@cavium.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-06-15 12:29:52 -06:00
hwrena |= MIPS_HWRENA_ULR;
[MIPS] Enable support for the userlocal hardware register Which will cut down the cost of RDHWR $29 which is used to obtain the TLS pointer and so far being emulated in software down to a single cycle operation. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10 10:33:02 -06:00
MIPS: Allow UserLocal on MIPS_R1 processors Some MIPS32R1 processors implement UserLocal (RDHWR $29) to accelerate programs that make extensive use of thread-local storage. Therefore, setting up the HWRENA register should not depend on cpu_has_mips_r2. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
2010-10-16 15:22:38 -06:00
if (hwrena)
write_c0_hwrena(hwrena);
MIPS: traps: Add CPU PM callback for trap configuration Implement a CPU power management callback for restoring trap related CPU configuration after CPU power up from a low power state. The following state is restored: - Status register - HWREna register - Exception vector configuration registers - Context/XContext register Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-03-04 03:20:43 -07:00
}
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
MIPS: traps: Add CPU PM callback for trap configuration Implement a CPU power management callback for restoring trap related CPU configuration after CPU power up from a low power state. The following state is restored: - Status register - HWREna register - Exception vector configuration registers - Context/XContext register Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-03-04 03:20:43 -07:00
static void configure_exception_vector(void)
{
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
if (cpu_has_veic || cpu_has_vint) {
MIPS: R2: Fix problem with code that incorrectly modifies ebase. Commit 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e had a change that incorrectly modified ebase. This backs out the lines that modified ebase. In addition, the ebase exception vector is now allocated with correct alignment and the ebase register updated according to the architecture specification. Based on original patch by David VomLehn <dvomlehn@cisco.com>. Signed-off-by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-20 16:33:55 -06:00
unsigned long sr = set_c0_status(ST0_BEV);
MIPS: traps: Ensure full EBase is written On CPUs which support the EBase WG (write gate) flag, the most significant bits of the exception base can be changed. Firmware running on a VP(E) using MIPS rproc may change EBase to point into the user segment where the firmware is located such that it can service interrupts. When control is transferred back to the kernel the EBase must be switched back into the kernel segment, such that the kernel's exception vectors are used. Similarly when vectored interrupts (vint) or vectored external interrupt controllers (veic) are enabled an exception vector is allocated from bootmem, and written to the EBase register. Due to the WG flag being clear, only bits 29:12 will be written. Asside from the rproc case above this is normally fine (as it will usually be a low allocation within the KSeg0 range, however when Enhanced Virtual Addressing (EVA) is enabled the allocation may be outside of the traditional KSeg0/KSeg1 address range, resulting in the wrong EBase being written. Correct both cases (configure_exception_vector() for the boot CPU, and per_cpu_trap_init() for secondary CPUs) to write EBase with the WG flag first if supported. On the Malta EVA configuration, KSeg0 is mapped to physical address 0, and memory is allocated from the KUSeg segment which is mapped to physical address 0x80000000, which physically aliases the RAM at 0. This only worked due to the exception base address aliasing the same underlying RAM that was written to & cache flushed, and due to flush_icache_range() going beyond the call of duty and flushing from the L2 cache too (due to the differing physical addresses). Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14150/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-09-01 10:30:09 -06:00
/* If available, use WG to set top bits of EBASE */
if (cpu_has_ebase_wg) {
#ifdef CONFIG_64BIT
write_c0_ebase_64(ebase | MIPS_EBASE_WG);
#else
write_c0_ebase(ebase | MIPS_EBASE_WG);
#endif
}
[MIPS] Fix "no space between function name and open parenthesis" warnings. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 16:46:15 -06:00
write_c0_ebase(ebase);
MIPS: R2: Fix problem with code that incorrectly modifies ebase. Commit 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e had a change that incorrectly modified ebase. This backs out the lines that modified ebase. In addition, the ebase exception vector is now allocated with correct alignment and the ebase register updated according to the architecture specification. Based on original patch by David VomLehn <dvomlehn@cisco.com>. Signed-off-by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-20 16:33:55 -06:00
write_c0_status(sr);
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
/* Setting vector spacing enables EI/VI mode */
[MIPS] Fix "no space between function name and open parenthesis" warnings. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 16:46:15 -06:00
change_c0_intctl(0x3e0, VECTORSPACING);
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
}
MT bulletproofing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-08-17 07:44:26 -06:00
if (cpu_has_divec) {
if (cpu_has_mipsmt) {
unsigned int vpflags = dvpe();
set_c0_cause(CAUSEF_IV);
evpe(vpflags);
} else
set_c0_cause(CAUSEF_IV);
}
MIPS: traps: Add CPU PM callback for trap configuration Implement a CPU power management callback for restoring trap related CPU configuration after CPU power up from a low power state. The following state is restored: - Status register - HWREna register - Exception vector configuration registers - Context/XContext register Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-03-04 03:20:43 -07:00
}
void per_cpu_trap_init(bool is_boot_cpu)
{
unsigned int cpu = smp_processor_id();
configure_status();
configure_hwrena();
configure_exception_vector();
[MIPS] Don't drag a platform specific header into generic arch code. For some platforms it's definitions may conflict. So that's the one-liner. The rest is 10 square kilometers of collateral damage fixup this include used to paper over. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-06-20 15:27:10 -06:00
/*
* Before R2 both interrupt numbers were fixed to 7, so on R2 only:
*
* o read IntCtl.IPTI to determine the timer interrupt
* o read IntCtl.IPPCI to determine the performance counter interrupt
MIPS: Read CPU IRQ line that FDC to routed to Read the CPU IRQ line reportedly used for the Fast Debug Channel (FDC) interrupt from the IntCtl register and store it in cp0_fdc_irq where platform implementations of the new weak platform function get_c0_fdc_int() can refer to it. [ralf@linux-mips.org: Fixed conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/9140/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-29 04:14:07 -07:00
* o read IntCtl.IPFDC to determine the fast debug channel interrupt
[MIPS] Don't drag a platform specific header into generic arch code. For some platforms it's definitions may conflict. So that's the one-liner. The rest is 10 square kilometers of collateral damage fixup this include used to paper over. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-06-20 15:27:10 -06:00
*/
MIPS: kernel: traps: Add MIPS R6 related definitions Add MIPS R6 support to cache and ftlb exceptions, as well as to the hwrena and ebase register configuration. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
2014-11-14 04:25:30 -07:00
if (cpu_has_mips_r2_r6) {
MIPS: traps: Make sure secondary cores have a sane ebase register We shouldn't trust that the secondary cores will have a sane ebase register (either from the bootloader or during the hardware design phase) so use the ebase address as calculated by the boot CPU. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Petri Gynther <pgynther@google.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12328/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-02-02 20:15:22 -07:00
/*
* We shouldn't trust a secondary core has a sane EBASE register
* so use the one calculated by the boot CPU.
*/
MIPS: traps: Ensure full EBase is written On CPUs which support the EBase WG (write gate) flag, the most significant bits of the exception base can be changed. Firmware running on a VP(E) using MIPS rproc may change EBase to point into the user segment where the firmware is located such that it can service interrupts. When control is transferred back to the kernel the EBase must be switched back into the kernel segment, such that the kernel's exception vectors are used. Similarly when vectored interrupts (vint) or vectored external interrupt controllers (veic) are enabled an exception vector is allocated from bootmem, and written to the EBase register. Due to the WG flag being clear, only bits 29:12 will be written. Asside from the rproc case above this is normally fine (as it will usually be a low allocation within the KSeg0 range, however when Enhanced Virtual Addressing (EVA) is enabled the allocation may be outside of the traditional KSeg0/KSeg1 address range, resulting in the wrong EBase being written. Correct both cases (configure_exception_vector() for the boot CPU, and per_cpu_trap_init() for secondary CPUs) to write EBase with the WG flag first if supported. On the Malta EVA configuration, KSeg0 is mapped to physical address 0, and memory is allocated from the KUSeg segment which is mapped to physical address 0x80000000, which physically aliases the RAM at 0. This only worked due to the exception base address aliasing the same underlying RAM that was written to & cache flushed, and due to flush_icache_range() going beyond the call of duty and flushing from the L2 cache too (due to the differing physical addresses). Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14150/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-09-01 10:30:09 -06:00
if (!is_boot_cpu) {
/* If available, use WG to set top bits of EBASE */
if (cpu_has_ebase_wg) {
#ifdef CONFIG_64BIT
write_c0_ebase_64(ebase | MIPS_EBASE_WG);
#else
write_c0_ebase(ebase | MIPS_EBASE_WG);
#endif
}
MIPS: traps: Make sure secondary cores have a sane ebase register We shouldn't trust that the secondary cores will have a sane ebase register (either from the bootloader or during the hardware design phase) so use the ebase address as calculated by the boot CPU. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Petri Gynther <pgynther@google.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12328/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-02-02 20:15:22 -07:00
write_c0_ebase(ebase);
MIPS: traps: Ensure full EBase is written On CPUs which support the EBase WG (write gate) flag, the most significant bits of the exception base can be changed. Firmware running on a VP(E) using MIPS rproc may change EBase to point into the user segment where the firmware is located such that it can service interrupts. When control is transferred back to the kernel the EBase must be switched back into the kernel segment, such that the kernel's exception vectors are used. Similarly when vectored interrupts (vint) or vectored external interrupt controllers (veic) are enabled an exception vector is allocated from bootmem, and written to the EBase register. Due to the WG flag being clear, only bits 29:12 will be written. Asside from the rproc case above this is normally fine (as it will usually be a low allocation within the KSeg0 range, however when Enhanced Virtual Addressing (EVA) is enabled the allocation may be outside of the traditional KSeg0/KSeg1 address range, resulting in the wrong EBase being written. Correct both cases (configure_exception_vector() for the boot CPU, and per_cpu_trap_init() for secondary CPUs) to write EBase with the WG flag first if supported. On the Malta EVA configuration, KSeg0 is mapped to physical address 0, and memory is allocated from the KUSeg segment which is mapped to physical address 0x80000000, which physically aliases the RAM at 0. This only worked due to the exception base address aliasing the same underlying RAM that was written to & cache flushed, and due to flush_icache_range() going beyond the call of duty and flushing from the L2 cache too (due to the differing physical addresses). Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14150/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-09-01 10:30:09 -06:00
}
MIPS: traps: Make sure secondary cores have a sane ebase register We shouldn't trust that the secondary cores will have a sane ebase register (either from the bootloader or during the hardware design phase) so use the ebase address as calculated by the boot CPU. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: Petri Gynther <pgynther@google.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12328/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-02-02 20:15:22 -07:00
MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs The MIPS processor is limited to 64 external interrupt sources. Using a greater number without IRQ sharing requires reading platform-specific registers. On such platforms, reading the IntCtl register to determine which interrupt corresponds to a timer interrupt will not work. On MIPSR2 systems there is a solution - the TI bit in the Cause register, specifically indicates that a timer interrupt has occured. This patch uses that bit to detect interrupts for MIPSR2 processors, which may be expected to work regardless of how the timer interrupt may be routed in the hardware. Signed-off-by: David VomLehn (dvomlehn@cisco.com) To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/804/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-12-21 18:49:22 -07:00
cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
MIPS: Read CPU IRQ line that FDC to routed to Read the CPU IRQ line reportedly used for the Fast Debug Channel (FDC) interrupt from the IntCtl register and store it in cp0_fdc_irq where platform implementations of the new weak platform function get_c0_fdc_int() can refer to it. [ralf@linux-mips.org: Fixed conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/9140/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-29 04:14:07 -07:00
cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
if (!cp0_fdc_irq)
cp0_fdc_irq = -1;
[MIPS] Fix timer/performance interrupt detection Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-06-21 05:59:57 -06:00
} else {
cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
MIPS: Provide a symbol for the legacy performance counter interrupt. Based on https://patchwork.linux-mips.org/patch/3576 - but this really deserves its own patchset and the symbol should also be used :) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-07-06 15:56:00 -06:00
cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
[MIPS] Fix timer/performance interrupt detection Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-06-21 05:59:57 -06:00
cp0_perfcount_irq = -1;
MIPS: Read CPU IRQ line that FDC to routed to Read the CPU IRQ line reportedly used for the Fast Debug Channel (FDC) interrupt from the IntCtl register and store it in cp0_fdc_irq where platform implementations of the new weak platform function get_c0_fdc_int() can refer to it. [ralf@linux-mips.org: Fixed conflict.] Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: James Hogan <james.hogan@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/9140/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-01-29 04:14:07 -07:00
cp0_fdc_irq = -1;
[MIPS] Don't drag a platform specific header into generic arch code. For some platforms it's definitions may conflict. So that's the one-liner. The rest is 10 square kilometers of collateral damage fixup this include used to paper over. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-06-20 15:27:10 -06:00
}
MIPS: MemoryMapID (MMID) Support Introduce support for using MemoryMapIDs (MMIDs) as an alternative to Address Space IDs (ASIDs). The major difference between the two is that MMIDs are global - ie. an MMID uniquely identifies an address space across all coherent CPUs. In contrast ASIDs are non-global per-CPU IDs, wherein each address space is allocated a separate ASID for each CPU upon which it is used. This global namespace allows a new GINVT instruction be used to globally invalidate TLB entries associated with a particular MMID across all coherent CPUs in the system, removing the need for IPIs to invalidate entries with separate ASIDs on each CPU. The allocation scheme used here is largely borrowed from arm64 (see arch/arm64/mm/context.c). In essence we maintain a bitmap to track available MMIDs, and MMIDs in active use at the time of a rollover to a new MMID version are preserved in the new version. The allocation scheme requires efficient 64 bit atomics in order to perform reasonably, so this support depends upon CONFIG_GENERIC_ATOMIC64=n (ie. currently it will only be included in MIPS64 kernels). The first, and currently only, available CPU with support for MMIDs is the MIPS I6500. This CPU supports 16 bit MMIDs, and so for now we cap our MMIDs to 16 bits wide in order to prevent the bitmap growing to absurd sizes if any future CPU does implement 32 bit MMIDs as the architecture manuals suggest is recommended. When MMIDs are in use we also make use of GINVT instruction which is available due to the global nature of MMIDs. By executing a sequence of GINVT & SYNC 0x14 instructions we can avoid the overhead of an IPI to each remote CPU in many cases. One complication is that GINVT will invalidate wired entries (in all cases apart from type 0, which targets the entire TLB). In order to avoid GINVT invalidating any wired TLB entries we set up, we make sure to create those entries using a reserved MMID (0) that we never associate with any address space. Also of note is that KVM will require further work in order to support MMIDs & GINVT, since KVM is involved in allocating IDs for guests & in configuring the MMU. That work is not part of this patch, so for now when MMIDs are in use KVM is disabled. Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org
2019-02-01 18:43:28 -07:00
if (cpu_has_mmid)
cpu_data[cpu].asid_cache = 0;
else if (!cpu_data[cpu].asid_cache)
MIPS: Retrieve ASID masks using function accepting struct cpuinfo_mips In preparation for supporting variable ASID masks, retrieve ASID masks using functions in asm/cpu-info.h which accept struct cpuinfo_mips. This will allow those functions to determine the ASID mask based upon the CPU in a later patch. This also allows for the r3k & r8k cases to be handled in Kconfig, which is arguably cleaner than the previous #ifdefs. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Radim Krčmář <rkrcmar@redhat.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13210/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-05-06 07:36:23 -06:00
cpu_data[cpu].asid_cache = asid_first_version(cpu);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
mm: add new mmgrab() helper Apart from adding the helper function itself, the rest of the kernel is converted mechanically using: git grep -l 'atomic_inc.*mm_count' | xargs sed -i 's/atomic_inc(&\(.*\)->mm_count);/mmgrab\(\1\);/' git grep -l 'atomic_inc.*mm_count' | xargs sed -i 's/atomic_inc(&\(.*\)\.mm_count);/mmgrab\(\&\1\);/' This is needed for a later patch that hooks into the helper, but might be a worthwhile cleanup on its own. (Michal Hocko provided most of the kerneldoc comment.) Link: http://lkml.kernel.org/r/20161218123229.22952-1-vegard.nossum@oracle.com Signed-off-by: Vegard Nossum <vegard.nossum@oracle.com> Acked-by: Michal Hocko <mhocko@suse.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: David Rientjes <rientjes@google.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2017-02-27 15:30:07 -07:00
mmgrab(&init_mm);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
current->active_mm = &init_mm;
BUG_ON(current->mm);
enter_lazy_tlb(&init_mm, current);
MIPS: kernel: traps: Fix broken indentation Fix broken indentation caused by the SMTC removal commit b633648c5ad3cfbda0b3daea50d2135d44899259 ("MIPS: MT: Remove SMTC support") Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Fixes: b633648c5ad3c ("MIPS: MT: Remove SMTC support") Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10581/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-06-24 02:29:20 -06:00
/* Boot CPU's cache setup in setup_arch(). */
if (!is_boot_cpu)
cpu_cache_init();
tlb_init();
MIPS: Use C0_KScratch (if present) to hold PGD pointer. Decide at runtime to use either Context or KScratch to hold the PGD pointer. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1876/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-12-21 15:19:11 -07:00
TLBMISS_HANDLER_SETUP();
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
/* Install CPU exception handler */
MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code commit 3747069b25e419f6b51395f48127e9812abc3596 upstream. The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. Here, we remove all the MIPS __cpuinit from C code and __CPUINIT from asm files. MIPS is interesting in this respect, because there are also uasm users hiding behind their own renamed versions of the __cpuinit macros. [1] https://lkml.org/lkml/2013/5/20/589 [ralf@linux-mips.org: Folded in Paul's followup fix.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5494/ Patchwork: https://patchwork.linux-mips.org/patch/5495/ Patchwork: https://patchwork.linux-mips.org/patch/5509/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-18 07:38:59 -06:00
void set_handler(unsigned long offset, void *addr, unsigned long size)
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
{
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
#ifdef CONFIG_CPU_MICROMIPS
memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
#else
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
memcpy((void *)(ebase + offset), addr, size);
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
#endif
[MIPS] Fix WARNING: at kernel/smp.c:290 trap_init issues flush_icache_range(), which uses ipi functions to get icache flushing done on all cpus. But this is done before interrupts are enabled and caused WARN_ON messages. This changeset introduces a new local_flush_icache_range() and uses it before interrupts (and additional CPUs) are enabled to avoid this problem. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-08-04 12:53:57 -06:00
local_flush_icache_range(ebase + offset, ebase + offset + size);
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
}
format-security: move static strings to const While examining output from trial builds with -Wformat-security enabled, many strings were found that should be defined as "const", or as a char array instead of char pointer. This makes some static analysis easier, by producing fewer false positives. As these are all trivial changes, it seemed best to put them all in a single patch rather than chopping them up per maintainer. Link: http://lkml.kernel.org/r/20170405214711.GA5711@beast Signed-off-by: Kees Cook <keescook@chromium.org> Acked-by: Jes Sorensen <jes@trained-monkey.org> [runner.c] Cc: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@armlinux.org.uk> Cc: "Maciej W. Rozycki" <macro@linux-mips.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: David Airlie <airlied@linux.ie> Cc: Yisen Zhuang <yisen.zhuang@huawei.com> Cc: Salil Mehta <salil.mehta@huawei.com> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Jiri Slaby <jslaby@suse.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: Rasmus Villemoes <linux@rasmusvillemoes.dk> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Felipe Balbi <felipe.balbi@linux.intel.com> Cc: Jarod Wilson <jarod@redhat.com> Cc: Florian Westphal <fw@strlen.de> Cc: Antonio Quartulli <a@unstable.cc> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Kejian Yan <yankejian@huawei.com> Cc: Daode Huang <huangdaode@hisilicon.com> Cc: Qianqian Xie <xieqianqian@huawei.com> Cc: Philippe Reynes <tremyfr@gmail.com> Cc: Colin Ian King <colin.king@canonical.com> Cc: Eric Dumazet <edumazet@google.com> Cc: Christian Gromm <christian.gromm@microchip.com> Cc: Andrey Shvetsov <andrey.shvetsov@k2l.de> Cc: Jason Litzinger <jlitzingerdev@gmail.com> Cc: WANG Cong <xiyou.wangcong@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2017-05-08 16:59:05 -06:00
static const char panic_null_cerr[] =
"Trying to set NULL cache error exception handler\n";
[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 16:46:05 -06:00
MIPS: R2: Fix broken installation of cache error handler. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-28 11:48:23 -07:00
/*
* Install uncached CPU exception handler.
* This is suitable only for the cache error exception which is the only
* exception handler that is being run uncached.
*/
MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code commit 3747069b25e419f6b51395f48127e9812abc3596 upstream. The __cpuinit type of throwaway sections might have made sense some time ago when RAM was more constrained, but now the savings do not offset the cost and complications. For example, the fix in commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time") is a good example of the nasty type of bugs that can be created with improper use of the various __init prefixes. After a discussion on LKML[1] it was decided that cpuinit should go the way of devinit and be phased out. Once all the users are gone, we can then finally remove the macros themselves from linux/init.h. Note that some harmless section mismatch warnings may result, since notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c) and are flagged as __cpuinit -- so if we remove the __cpuinit from the arch specific callers, we will also get section mismatch warnings. As an intermediate step, we intend to turn the linux/init.h cpuinit related content into no-ops as early as possible, since that will get rid of these warnings. In any case, they are temporary and harmless. Here, we remove all the MIPS __cpuinit from C code and __CPUINIT from asm files. MIPS is interesting in this respect, because there are also uasm users hiding behind their own renamed versions of the __cpuinit macros. [1] https://lkml.org/lkml/2013/5/20/589 [ralf@linux-mips.org: Folded in Paul's followup fix.] Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5494/ Patchwork: https://patchwork.linux-mips.org/patch/5495/ Patchwork: https://patchwork.linux-mips.org/patch/5509/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-18 07:38:59 -06:00
void set_uncached_handler(unsigned long offset, void *addr,
[MIPS] Fix loads of section missmatches Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-03-08 02:56:28 -07:00
unsigned long size)
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
{
MIPS: Use CKSEG1ADDR for uncached handler "MIPS: Calculate proper ebase value for 64-bit kernels" 9af43ea080dd5d6c7b34f38261780e5dd43537bc (lmo) rsp. f6be75d03c8870be91e6e2a195648ece04b6bb16 (kernel.org) broke some 64-bit MIPS systems. Before this we were using XKPHYS/cached as ebase and computed the uncached xphsys/unchached address for that area. After that commit ebase became a 32-bit compat address and convert does not work anymore. We now should use CKSEG1 for this. CKSEG1ADDR does just that in 32-bit and 64-bit. Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> To: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1149/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-04-27 14:53:30 -06:00
unsigned long uncached_ebase = CKSEG1ADDR(ebase);
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 16:46:05 -06:00
if (!addr)
panic(panic_null_cerr);
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
memcpy((void *)(uncached_ebase + offset), addr, size);
}
[MIPS] Fast path for rdhwr emulation for TLS Add special short path for emulationg RDHWR which is used to support TLS. Add an extra prologue for cpu_has_vtag_icache case. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-11 02:50:29 -06:00
static int __initdata rdhwr_noopt;
static int __init set_rdhwr_noopt(char *str)
{
rdhwr_noopt = 1;
return 1;
}
__setup("rdhwr_noopt", set_rdhwr_noopt);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
void __init trap_init(void)
{
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
extern char except_vec3_generic;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
extern char except_vec4;
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
extern char except_vec3_r4000;
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
unsigned long i;
[MIPS] Fix potential latency problem due to non-atomic cpu_wait. If an interrupt happened between checking of NEED_RESCHED and WAIT instruction, adjust EPC to restart from checking of NEED_RESCHED. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-11 10:05:18 -07:00
check_wait();
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: R2: Fix problem with code that incorrectly modifies ebase. Commit 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e had a change that incorrectly modified ebase. This backs out the lines that modified ebase. In addition, the ebase exception vector is now allocated with correct alignment and the ebase register updated according to the architecture specification. Based on original patch by David VomLehn <dvomlehn@cisco.com>. Signed-off-by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-20 16:33:55 -06:00
if (cpu_has_veic || cpu_has_vint) {
unsigned long size = 0x200 + VECTORSPACING*64;
MIPS: traps: Convert ebase to KSEG0 When allocating boot memory for the exception vector when vectored interrupts (vint) or vectored external interrupt controllers (veic) are enabled, try to ensure that the virtual address resides in KSeg0 (and WARN should that not be possible). This will be helpful on MIPS64 cores supporting the CP0_EBase Write Gate (WG) bit once we start using the WG bit to write the full ebase into CP0_EBase, as we ideally need to avoid hitting the architecturally poorly defined exception base for Cache Errors when CP0_EBase is in XKPhys. An exception is made for Enhanced Virtual Addressing (EVA) kernels which allow segments to be rearranged and to become uncached during cache error handling, making it valid for ebase to be elsewhere. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14149/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-09-01 10:30:08 -06:00
phys_addr_t ebase_pa;
MIPS: R2: Fix problem with code that incorrectly modifies ebase. Commit 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e had a change that incorrectly modified ebase. This backs out the lines that modified ebase. In addition, the ebase exception vector is now allocated with correct alignment and the ebase register updated according to the architecture specification. Based on original patch by David VomLehn <dvomlehn@cisco.com>. Signed-off-by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-20 16:33:55 -06:00
ebase = (unsigned long)
arch: use memblock_alloc() instead of memblock_alloc_from(size, align, 0) The last parameter of memblock_alloc_from() is the lower limit for the memory allocation. When it is 0, the call is equivalent to memblock_alloc(). Link: http://lkml.kernel.org/r/1548057848-15136-13-git-send-email-rppt@linux.ibm.com Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Acked-by: Paul Burton <paul.burton@mips.com> # MIPS part Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Christophe Leroy <christophe.leroy@c-s.fr> Cc: Christoph Hellwig <hch@lst.de> Cc: "David S. Miller" <davem@davemloft.net> Cc: Dennis Zhou <dennis@kernel.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Greentime Hu <green.hu@gmail.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Guan Xuetao <gxt@pku.edu.cn> Cc: Guo Ren <guoren@kernel.org> Cc: Guo Ren <ren_guo@c-sky.com> [c-sky] Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Juergen Gross <jgross@suse.com> [Xen] Cc: Mark Salter <msalter@redhat.com> Cc: Matt Turner <mattst88@gmail.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Michal Simek <monstr@monstr.eu> Cc: Petr Mladek <pmladek@suse.com> Cc: Richard Weinberger <richard@nod.at> Cc: Rich Felker <dalias@libc.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Stafford Horne <shorne@gmail.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2019-03-12 00:29:50 -06:00
memblock_alloc(size, 1 << fls(size));
treewide: add checks for the return value of memblock_alloc*() Add check for the return value of memblock_alloc*() functions and call panic() in case of error. The panic message repeats the one used by panicing memblock allocators with adjustment of parameters to include only relevant ones. The replacement was mostly automated with semantic patches like the one below with manual massaging of format strings. @@ expression ptr, size, align; @@ ptr = memblock_alloc(size, align); + if (!ptr) + panic("%s: Failed to allocate %lu bytes align=0x%lx\n", __func__, size, align); [anders.roxell@linaro.org: use '%pa' with 'phys_addr_t' type] Link: http://lkml.kernel.org/r/20190131161046.21886-1-anders.roxell@linaro.org [rppt@linux.ibm.com: fix format strings for panics after memblock_alloc] Link: http://lkml.kernel.org/r/1548950940-15145-1-git-send-email-rppt@linux.ibm.com [rppt@linux.ibm.com: don't panic if the allocation in sparse_buffer_init fails] Link: http://lkml.kernel.org/r/20190131074018.GD28876@rapoport-lnx [akpm@linux-foundation.org: fix xtensa printk warning] Link: http://lkml.kernel.org/r/1548057848-15136-20-git-send-email-rppt@linux.ibm.com Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Anders Roxell <anders.roxell@linaro.org> Reviewed-by: Guo Ren <ren_guo@c-sky.com> [c-sky] Acked-by: Paul Burton <paul.burton@mips.com> [MIPS] Acked-by: Heiko Carstens <heiko.carstens@de.ibm.com> [s390] Reviewed-by: Juergen Gross <jgross@suse.com> [Xen] Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> [m68k] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa] Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Christophe Leroy <christophe.leroy@c-s.fr> Cc: Christoph Hellwig <hch@lst.de> Cc: "David S. Miller" <davem@davemloft.net> Cc: Dennis Zhou <dennis@kernel.org> Cc: Greentime Hu <green.hu@gmail.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Guan Xuetao <gxt@pku.edu.cn> Cc: Guo Ren <guoren@kernel.org> Cc: Mark Salter <msalter@redhat.com> Cc: Matt Turner <mattst88@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Michal Simek <monstr@monstr.eu> Cc: Petr Mladek <pmladek@suse.com> Cc: Richard Weinberger <richard@nod.at> Cc: Rich Felker <dalias@libc.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: Russell King <linux@armlinux.org.uk> Cc: Stafford Horne <shorne@gmail.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2019-03-12 00:30:31 -06:00
if (!ebase)
panic("%s: Failed to allocate %lu bytes align=0x%x\n",
__func__, size, 1 << fls(size));
MIPS: traps: Convert ebase to KSEG0 When allocating boot memory for the exception vector when vectored interrupts (vint) or vectored external interrupt controllers (veic) are enabled, try to ensure that the virtual address resides in KSeg0 (and WARN should that not be possible). This will be helpful on MIPS64 cores supporting the CP0_EBase Write Gate (WG) bit once we start using the WG bit to write the full ebase into CP0_EBase, as we ideally need to avoid hitting the architecturally poorly defined exception base for Cache Errors when CP0_EBase is in XKPhys. An exception is made for Enhanced Virtual Addressing (EVA) kernels which allow segments to be rearranged and to become uncached during cache error handling, making it valid for ebase to be elsewhere. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Leonid Yegoshin <leonid.yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14149/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-09-01 10:30:08 -06:00
/*
* Try to ensure ebase resides in KSeg0 if possible.
*
* It shouldn't generally be in XKPhys on MIPS64 to avoid
* hitting a poorly defined exception base for Cache Errors.
* The allocation is likely to be in the low 512MB of physical,
* in which case we should be able to convert to KSeg0.
*
* EVA is special though as it allows segments to be rearranged
* and to become uncached during cache error handling.
*/
ebase_pa = __pa(ebase);
if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
ebase = CKSEG0ADDR(ebase_pa);
MIPS: R2: Fix problem with code that incorrectly modifies ebase. Commit 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e had a change that incorrectly modified ebase. This backs out the lines that modified ebase. In addition, the ebase exception vector is now allocated with correct alignment and the ebase register updated according to the architecture specification. Based on original patch by David VomLehn <dvomlehn@cisco.com>. Signed-off-by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-20 16:33:55 -06:00
} else {
MIPS: traps: tidy up ebase calculation Rather than #ifdef on CONFIG_KVM_GUEST & redefine the guest kseg0 base locally, make use of the CAC_BASE macro which has the correct value in both cases. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/11183/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-09-22 11:15:22 -06:00
ebase = CAC_BASE;
MIPS: traps: 64bit kernels should read CP0_EBase 64bit When reading the CP0_EBase register containing the WG (write gate) bit, the ebase variable should be set to the full value of the register, i.e. on a 64-bit kernel the full 64-bit width of the register via read_cp0_ebase_64(), and on a 32-bit kernel the full 32-bit width including bits 31:30 which may be writeable. Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14148/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-09-01 10:30:07 -06:00
if (cpu_has_mips_r2_r6) {
if (cpu_has_ebase_wg) {
#ifdef CONFIG_64BIT
ebase = (read_c0_ebase_64() & ~0xfff);
#else
ebase = (read_c0_ebase() & ~0xfff);
#endif
} else {
ebase += (read_c0_ebase() & 0x3ffff000);
}
}
MIPS: Consider value of c0_ebase when computing value of exception base. It just so happens to be zero on all currently supported systems so this hasn't bitten yet ... [Ralf: Original patch from Cavium; handling of set_uncached_handler() and de-ifdef'ed trap_init() implementation by me.] Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-23 18:56:35 -06:00
}
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
MIPS: microMIPS: Fix improper definition of ISA exception bit. The ISA exception bit selects whether exceptions are taken in classic or microMIPS mode. This bit is Config3.ISAOnExc and was improperly defined as bits 16 and 17 instead of just bit 16. A new function was added so that platforms could set this bit when running a kernel compiled with only microMIPS instructions. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5377/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-06-05 15:25:17 -06:00
if (cpu_has_mmips) {
unsigned int config3 = read_c0_config3();
if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
else
write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
}
MIPS: Add board_ebase_setup() Some systems need to relocate the MIPS exception vector base during trap initialization. Add a hook to make this possible. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2959/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-11-15 18:25:45 -07:00
if (board_ebase_setup)
board_ebase_setup();
MIPS: Move cache setup to setup_arch(). commit 97ce2c88f9ad42e3c60a9beb9fca87abf3639faa (jump-label: initialize jump-label subsystem much earlier) breaks MIPS. The jump_label_init() call was moved before trap_init() which is where we initialize flush_icache_range(). In order to be good citizens, we move cache initialization earlier so that we don't jump through a null flush_icache_range function pointer when doing the jump label initialization. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3822/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-05-15 01:04:50 -06:00
per_cpu_trap_init(true);
MIPS: Let early memblock_alloc*() allocate memories bottom-up After switched to NO_BOOTMEM, there are several boot failures. Some of them have been fixed and some of them haven't. I find that many of them are because of memory allocations are top-down, while the old behavior is bottom-up. This patch let early memblock_alloc*() allocate memories bottom-up to avoid some potential problems. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Fixes: bcec54bf3118 ("mips: switch to NO_BOOTMEM") Patchwork: https://patchwork.linux-mips.org/patch/21069/ References: https://patchwork.linux-mips.org/patch/21031/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <james.hogan@mips.com> Cc: Steven J . Hill <Steven.Hill@cavium.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com>
2018-11-09 20:50:14 -07:00
memblock_set_bottom_up(false);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
* Copy the generic exception handlers to their final destination.
MIPS: Fix misspellings in comments. Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com> Cc: linux-mips@linux-mips.org Cc: trivial@kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12617/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2016-02-25 01:44:58 -07:00
* This will be overridden later as suitable for a particular
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
* configuration.
*/
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
set_handler(0x180, &except_vec3_generic, 0x80);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
* Setup default vectors
*/
for (i = 0; i <= 31; i++)
set_except_vector(i, handle_reserved);
/*
* Copy the EJTAG debug exception vector handler code to it's final
* destination.
*/
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
if (cpu_has_ejtag && board_ejtag_handler_setup)
[MIPS] Fix "no space between function name and open parenthesis" warnings. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 16:46:15 -06:00
board_ejtag_handler_setup();
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
* Only some CPUs have the watch exceptions.
*/
if (cpu_has_watch)
MIPS: Use EXCCODE_ constants with set_except_vector() The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-12-16 16:49:35 -07:00
set_except_vector(EXCCODE_WATCH, handle_watch);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
* Initialise interrupt handlers
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
*/
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
if (cpu_has_veic || cpu_has_vint) {
int nvec = cpu_has_veic ? 64 : 8;
for (i = 0; i < nvec; i++)
[MIPS] Some formatting fixes. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-29 06:12:58 -07:00
set_vi_handler(i, NULL);
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
}
else if (cpu_has_divec)
set_handler(0x200, &except_vec4, 0x8);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
/*
* Some CPUs can enable/disable for cache parity detection, but does
* it different ways.
*/
parity_protection_init();
/*
* The Data Bus Errors / Instruction Bus Errors are signaled
* by external hardware. Therefore these two exceptions
* may have board specific handlers.
*/
if (board_be_init)
board_be_init();
MIPS: Use EXCCODE_ constants with set_except_vector() The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-12-16 16:49:35 -07:00
set_except_vector(EXCCODE_INT, using_rollback_handler() ?
rollback_handle_int : handle_int);
set_except_vector(EXCCODE_MOD, handle_tlbm);
set_except_vector(EXCCODE_TLBL, handle_tlbl);
set_except_vector(EXCCODE_TLBS, handle_tlbs);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: Use EXCCODE_ constants with set_except_vector() The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-12-16 16:49:35 -07:00
set_except_vector(EXCCODE_ADEL, handle_adel);
set_except_vector(EXCCODE_ADES, handle_ades);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: Use EXCCODE_ constants with set_except_vector() The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-12-16 16:49:35 -07:00
set_except_vector(EXCCODE_IBE, handle_ibe);
set_except_vector(EXCCODE_DBE, handle_dbe);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
MIPS: Use EXCCODE_ constants with set_except_vector() The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-12-16 16:49:35 -07:00
set_except_vector(EXCCODE_SYS, handle_sys);
set_except_vector(EXCCODE_BP, handle_bp);
MIPS: Check TLB before handle_ri_rdhwr() for Loongson-3 Loongson-3's micro TLB (ITLB) is not strictly a subset of JTLB. That means: when a JTLB entry is replaced by hardware, there may be an old valid entry exists in ITLB. So, a TLB miss exception may occur while handle_ri_rdhwr() is running because it try to access EPC's content. However, handle_ri_rdhwr() doesn't clear EXL, which makes a TLB Refill exception be treated as a TLB Invalid exception and tlbp may fail. In this case, if FTLB (which is usually set-associative instead of set- associative) is enabled, a tlbp failure will cause an invalid tlbwi, which will hang the whole system. This patch rename handle_ri_rdhwr_vivt to handle_ri_rdhwr_tlbp and use it for Loongson-3. It try to solve the same problem described as below, but more straightforwards. https://patchwork.linux-mips.org/patch/12591/ I think Loongson-2 has the same problem, but it has no FTLB, so we just keep it as is. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Rui Wang <wangr@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhc@lemote.com> Cc: linux-mips@linux-mips.org Cc: stable@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/15753/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2017-03-16 07:00:26 -06:00
if (rdhwr_noopt)
set_except_vector(EXCCODE_RI, handle_ri);
else {
if (cpu_has_vtag_icache)
set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
else if (current_cpu_type() == CPU_LOONGSON3)
set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
else
set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
}
MIPS: Use EXCCODE_ constants with set_except_vector() The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-12-16 16:49:35 -07:00
set_except_vector(EXCCODE_CPU, handle_cpu);
set_except_vector(EXCCODE_OV, handle_ov);
set_except_vector(EXCCODE_TR, handle_tr);
set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
More AP / SP bits for the 34K, the Malta bits and things. Still wants a little polishing. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-07-14 09:57:16 -06:00
if (board_nmi_handler_setup)
board_nmi_handler_setup();
Support the MIPS32 / MIPS64 DSP ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-05-31 05:49:19 -06:00
if (cpu_has_fpu && !cpu_has_nofpuex)
MIPS: Use EXCCODE_ constants with set_except_vector() The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-12-16 16:49:35 -07:00
set_except_vector(EXCCODE_FPE, handle_fpe);
Support the MIPS32 / MIPS64 DSP ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-05-31 05:49:19 -06:00
MIPS: Use EXCCODE_ constants with set_except_vector() The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-12-16 16:49:35 -07:00
set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions Use the regular tlb_do_page_fault_0 (no write) handler to handle the RI and XI exceptions. Also skip the RI/XI validation check on TLB load handler since it's redundant when the CPU has unique RI/XI exceptions. Singed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7339/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-15 07:09:56 -06:00
if (cpu_has_rixiex) {
MIPS: Use EXCCODE_ constants with set_except_vector() The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-12-16 16:49:35 -07:00
set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions Use the regular tlb_do_page_fault_0 (no write) handler to handle the RI and XI exceptions. Also skip the RI/XI validation check on TLB load handler since it's redundant when the CPU has unique RI/XI exceptions. Singed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7339/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-07-15 07:09:56 -06:00
}
MIPS: Use EXCCODE_ constants with set_except_vector() The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-12-16 16:49:35 -07:00
set_except_vector(EXCCODE_MSADIS, handle_msa);
set_except_vector(EXCCODE_MDMX, handle_mdmx);
Support the MIPS32 / MIPS64 DSP ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-05-31 05:49:19 -06:00
if (cpu_has_mcheck)
MIPS: Use EXCCODE_ constants with set_except_vector() The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-12-16 16:49:35 -07:00
set_except_vector(EXCCODE_MCHECK, handle_mcheck);
Support the MIPS32 / MIPS64 DSP ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-05-31 05:49:19 -06:00
Virtual SMP support for the 34K. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-08-17 11:44:08 -06:00
if (cpu_has_mipsmt)
MIPS: Use EXCCODE_ constants with set_except_vector() The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-12-16 16:49:35 -07:00
set_except_vector(EXCCODE_THREAD, handle_mt);
Virtual SMP support for the 34K. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-08-17 11:44:08 -06:00
MIPS: Use EXCCODE_ constants with set_except_vector() The first argument to set_except_vector is the ExcCode, which we now have definitions for. Lets make use of them. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11894/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2015-12-16 16:49:35 -07:00
set_except_vector(EXCCODE_DSPDIS, handle_dsp);
Support the MIPS32 / MIPS64 DSP ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-05-31 05:49:19 -06:00
MIPS: Introduce board_cache_error_setup() hook. This is used in subsequent patches. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3819/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-05-15 01:04:46 -06:00
if (board_cache_error_setup)
board_cache_error_setup();
Support the MIPS32 / MIPS64 DSP ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-05-31 05:49:19 -06:00
if (cpu_has_vce)
/* Special exception: R4[04]00 uses also the divec space. */
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
set_handler(0x180, &except_vec3_r4000, 0x100);
Support the MIPS32 / MIPS64 DSP ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-05-31 05:49:19 -06:00
else if (cpu_has_4kex)
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
set_handler(0x180, &except_vec3_generic, 0x80);
Support the MIPS32 / MIPS64 DSP ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-05-31 05:49:19 -06:00
else
MIPS: microMIPS: Add support for exception handling. All exceptions must be taken in microMIPS mode, never in classic MIPS mode or the kernel falls apart. A few NOP instructions are used to maintain the correct alignment of microMIPS versions of the exception vectors. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
2013-03-25 11:15:55 -06:00
set_handler(0x080, &except_vec3_generic, 0x80);
Support the MIPS32 / MIPS64 DSP ASE. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-05-31 05:49:19 -06:00
[MIPS] Fix WARNING: at kernel/smp.c:290 trap_init issues flush_icache_range(), which uses ipi functions to get icache flushing done on all cpus. But this is done before interrupts are enabled and caused WARN_ON messages. This changeset introduces a new local_flush_icache_range() and uses it before interrupts (and additional CPUs) are enabled to avoid this problem. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-08-04 12:53:57 -06:00
local_flush_icache_range(ebase, ebase + 0x400);
[MIPS] Fix data bus error recovery With -ffunction-section the entries in __dbe_table aren't no longer sorted, so the lookup of exception addresses in do_be() failed for some addresses. To avoid this we now sort __dbe_table. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-08-04 11:44:34 -06:00
sort_extable(__start___dbe_table, __stop___dbe_table);
MIPS: Modularize COP2 handling Away with the daemons of ifdef; get ready for future COP2 users. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/708/
2009-11-23 18:24:58 -07:00
MIPS: Provide more elevant interface cu2_notifier for CP2 extensions. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: https://patchwork.linux-mips.org/patch/1504/
2010-08-05 06:25:59 -06:00
cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-16 16:20:36 -06:00
}
MIPS: traps: Add CPU PM callback for trap configuration Implement a CPU power management callback for restoring trap related CPU configuration after CPU power up from a low power state. The following state is restored: - Status register - HWREna register - Exception vector configuration registers - Context/XContext register Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
2014-03-04 03:20:43 -07:00
static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
void *v)
{
switch (cmd) {
case CPU_PM_ENTER_FAILED:
case CPU_PM_EXIT:
configure_status();
configure_hwrena();
configure_exception_vector();
/* Restore register with CPU number for TLB handlers */
TLBMISS_HANDLER_RESTORE();
break;
}
return NOTIFY_OK;
}
static struct notifier_block trap_pm_notifier_block = {
.notifier_call = trap_pm_notifier,
};
static int __init trap_pm_init(void)
{
return cpu_pm_register_notifier(&trap_pm_notifier_block);
}
arch_initcall(trap_pm_init);