Driver will enumerate all res@fps to user, but for ov5640,
when it work in DVP mode, 1080P only can reach 15fps. For
2592x1944, no matter which mode it works, it only support
about 8fps. So driver need to clarify these info and report
the real capability to user.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
Accroding to ov5640 datasheet, 2592x1944 only support 7.5fps.
But actually, it can reach about 8. For 1080P@30fps in DVP
mode, it can reach 1080P@15fsp, so adding valid mode and fps
checking before streaming.
Signed-off-by: Guoniu.zhou <guoniu.zhou@nxp.com>
FPGA on LX2160AQDS/LX2160ARDB connected on I2C bus, so add qixis driver
which is basically an i2c client driver to control FPGA.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
In sleep mode, the clocks of CPU core and unused IP blocks are turned
off (IP blocks allowed to wake up system will running).
Some QorIQ SoCs like MPC8536, P1022 and T104x, have deep sleep PM mode
in addtion to the sleep PM mode. While in deep sleep mode,
additionally, the power supply is removed from CPU core and most IP
blocks. Only the blocks needed to wake up the chip out of deep sleep
are ON.
This feature supports 32-bit and 36-bit address space.
The sleep mode is equal to the Standby state in Linux. The deep sleep
mode is equal to the Suspend-to-RAM state of Linux Power Management.
Command to enter sleep mode.
echo standby > /sys/power/state
Command to enter deep sleep mode.
echo mem > /sys/power/state
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Various e500 core have different cache architecture, so they
need different cache flush operations. Therefore, add a callback
function cpu_flush_caches to the struct cpu_spec. The cache flush
operation for the specific kind of e500 is selected at init time.
The callback function will flush all caches in the current cpu.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[PowerPC part]
QEIC was supported on PowerPC, and dependent on PPC,
Now it is supported on other platforms, so remove PPCisms.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
[PowerPC part]
The codes of qe_ic init from a variety of platforms are redundant,
merge them to a common function and put it to irqchip/irq-qeic.c
For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
"qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);".
qe_ic_cascade_muxed_mpic was used for boards has the same interrupt
number for low interrupt and high interrupt, qe_ic_init has checked
if "low interrupt == high interrupt"
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Add below functions for ARM platform which are used by ehci fsl driver:
1. spin_event_timeout function
2. set/clear bits functions
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
Hrtimer based broadcast is used on ARM platform. It can be
registered as the tick broadcast device in the absence of
a real external clock device.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
On i.MX8M SOC family, we can support LPDDR4, DDR4 or DDR3L, we may need
to support different setpoint for audio & low bus mode on different DDR type,
So update the code to get all the supported setpoint info from ATF.
The maximum setpoints that can be supported by hardware is 4, if the drate
for a setpoint is '0', that means this setpoint is not enabled. We can use
these info to find out the lowest drate setpoint for audio & low bus mode.
BuildInfo:
- ATF 59fe78cfe7
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
During system counter frequency change, the counter will stop, it
takes several mS even up to 20mS to finish the frequency change, if
system enters STOP mode before the frequency change done, system
counter will NOT run during STOP mode, then it will case system time
inaccurate and sometimes cause below RCU stall, so system can ONLY
enter STOP mode after the system counter frequency change done by
checking the ACK of frequency change.
rtc_testapp_6 0 TINFO : Waiting 50 seconds for alarm.......
fec 30be0000.ethernet eth0: Link is Down
PM: suspend devices took 0.670 seconds
Disabling non-boot CPUs ...
Enabling non-boot CPUs ...
rcu: INFO: rcu_sched self-detected stall on CPU
rcu: 0-...!: (1 ticks this GP) idle=1f6/1/0x40000002 softirq=5240/5240 fqs=0
(t=4903 jiffies g=3737 q=4)
rcu: rcu_sched kthread starved for 4903 jiffies! g3737 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 ->0
rcu: RCU grace-period kthread stack dump:
rcu_sched I 0 10 2 0x00000000
[<c0d85a9c>] (__schedule) from [<c0d85e64>] (schedule+0x50/0xc4)
[<c0d85e64>] (schedule) from [<c0d8b8fc>] (schedule_timeout+0x1b8/0x37c)
[<c0d8b8fc>] (schedule_timeout) from [<c01b9f2c>] (rcu_gp_kthread+0x8cc/0x1678)
[<c01b9f2c>] (rcu_gp_kthread) from [<c015f12c>] (kthread+0x114/0x14c)
[<c015f12c>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20)
Exception stack(0xd80fdfb0 to 0xd80fdff8)
dfa0: 00000000 00000000 00000000 00000000
dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
NMI backtrace for cpu 0
CPU: 0 PID: 834 Comm: rtc_testapp_6 Not tainted 5.4.0-rc7-03214-g56a9ca3 #105
Hardware name: Freescale i.MX7 Dual (Device Tree)
[<c01126e4>] (unwind_backtrace) from [<c010cf3c>] (show_stack+0x10/0x14)
[<c010cf3c>] (show_stack) from [<c0d691dc>] (dump_stack+0xe4/0x118)
[<c0d691dc>] (dump_stack) from [<c0d70678>] (nmi_cpu_backtrace+0xac/0xbc)
[<c0d70678>] (nmi_cpu_backtrace) from [<c0d70768>] (nmi_trigger_cpumask_backtrace+0xe0/0x130)
[<c0d70768>] (nmi_trigger_cpumask_backtrace) from [<c01be188>] (rcu_dump_cpu_stacks+0x9c/0xd8)
[<c01be188>] (rcu_dump_cpu_stacks) from [<c01bd254>] (rcu_sched_clock_irq+0x940/0xbec)
[<c01bd254>] (rcu_sched_clock_irq) from [<c01c5758>] (update_process_times+0x2c/0x54)
[<c01c5758>] (update_process_times) from [<c01d9cf0>] (tick_sched_timer+0x5c/0xc0)
[<c01d9cf0>] (tick_sched_timer) from [<c01c6bf8>] (__hrtimer_run_queues+0x140/0x548)
[<c01c6bf8>] (__hrtimer_run_queues) from [<c01c792c>] (hrtimer_interrupt+0x134/0x2bc)
[<c01c792c>] (hrtimer_interrupt) from [<c097eb00>] (arch_timer_handler_phys+0x2c/0x34)
[<c097eb00>] (arch_timer_handler_phys) from [<c01a6b1c>] (handle_percpu_devid_irq+0xd4/0x384)
[<c01a6b1c>] (handle_percpu_devid_irq) from [<c01a072c>] (generic_handle_irq+0x20/0x34)
[<c01a072c>] (generic_handle_irq) from [<c01a0d34>] (__handle_domain_irq+0x64/0xe0)
[<c01a0d34>] (__handle_domain_irq) from [<c0548510>] (gic_handle_irq+0x4c/0xa0)
[<c0548510>] (gic_handle_irq) from [<c0101a70>] (__irq_svc+0x70/0x98)
Exception stack(0xd8cedd00 to 0xd8cedd48)
dd00: 00000001 d88a5d20 00000000 200a0013 00000000 00000000 c1b3f6f0 0000002a
dd20: d8cec000 00000000 c1b3dbf8 c1b3d6f8 c16c82bc d8cedd50 c018fe50 c019dd68
dd40: 200a0013 ffffffff
[<c0101a70>] (__irq_svc) from [<c019dd68>] (console_unlock+0x4e0/0x634)
[<c019dd68>] (console_unlock) from [<c019f6c8>] (vprintk_emit+0xf4/0x2d0)
[<c019f6c8>] (vprintk_emit) from [<c019f8c8>] (vprintk_default+0x24/0x2c)
[<c019f8c8>] (vprintk_default) from [<c019fe9c>] (printk+0x2c/0x54)
[<c019fe9c>] (printk) from [<c013b560>] (enable_nonboot_cpus+0x38/0x2cc)
[<c013b560>] (enable_nonboot_cpus) from [<c019b4d0>] (suspend_devices_and_enter+0x374/0xa44)
[<c019b4d0>] (suspend_devices_and_enter) from [<c019be8c>] (pm_suspend+0x2ec/0x3d0)
[<c019be8c>] (pm_suspend) from [<c019a088>] (state_store+0x68/0xc8)
[<c019a088>] (state_store) from [<c033305c>] (kernfs_fop_write+0xfc/0x1e0)
[<c033305c>] (kernfs_fop_write) from [<c029d278>] (__vfs_write+0x2c/0x1d0)
[<c029d278>] (__vfs_write) from [<c02a0184>] (vfs_write+0xa0/0x180)
[<c02a0184>] (vfs_write) from [<c02a03e0>] (ksys_write+0x5c/0xd8)
[<c02a03e0>] (ksys_write) from [<c0101000>] (ret_fast_syscall+0x0/0x28)
Exception stack(0xd8cedfa8 to 0xd8cedff0)
dfa0: 00036294 00021590 00000004 bef5cd29 00000007 00000000
dfc0: 00036294 00021590 b6fc0d20 00000004 00000000 00000000 b6fc2fa4 00000000
dfe0: 00000004 bef5c8e8 b6f35d4f b6ec1d16
CPU1 is up
imx6q-pcie 33800000.pcie: Phy link never came up
imx6q-pcie 33800000.pcie: pcie link is down after resume.
mmc1: queuing unknown CIS tuple 0x80 (2 bytes)
mmc1: queuing unknown CIS tuple 0x80 (7 bytes)
mmc1: queuing unknown CIS tuple 0x80 (6 bytes)
PM: resume devices took 0.220 seconds
OOM killer enabled.
Restarting tasks ... done.
PM: suspend exit
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
on i.MX8QM 1.0/1.1,TLB maintenance through DVM messages over ARADDR channel,
some bits (see the following) will be corrupted:
ASID[15:12] VA[48:45] VA[44:41] VA[39:36]
This issue will result in the TLB aintenance across the clusters not working
as expected due to some VA and ASID bits get corrupted
The SW workaround is: use the vmalle1is if VA larger than 36bits or
ASID[15:12] is not zero, otherwise, we use original TLB maintenance path.
Note: To simplify the code, we did not check VA[40] bit specifically
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
SOC revision on older imx8mq is not available in fuses so on anything
other than B1 current code just reports "unknown".
TF-A already handles this by parsing the ROM and exposes the value
through a SMC call. Call this instead of reimplementing the workaround
in the kernel itself.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Tested-by: Clark Wang <xiaoning.wang@nxp.com>
(cherry picked from commit e814909ddca3067d089a8bd62084aae851387f79)
The GPC power domain driver add GENPD_FLAG_RPM_ALWAYS_ON to
the i.MX6QP's PU power domain flag, that means it is always ON
for runtime PM but can be OFF during suspend, so no need to
explicitly power ON/OFF PU power for i.MX6QP during suspend/resume
to avoid below dump:
Unable to handle kernel NULL pointer dereference at virtual address 00000044
pgd = 20824a30
[00000044] *pgd=4e36d831
Internal error: Oops: 17 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 732 Comm: sh Tainted: G W 5.3.0-rc3-next-20190809-01770-g0a0b3ec-dir3
Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
PC is at regmap_update_bits_base+0x10/0x74
LR is at imx6_pm_domain_power_on+0xbc/0x1b4
pc : [<c070887c>] lr : [<c05e18e4>] psr: 600001d3
sp : e9339d68 ip : e9338000 fp : c1a24158
r10: c1308b08 r9 : 00000260 r8 : c1308b08
r7 : c1426120 r6 : c1426120 r5 : c1373580 r4 : 00000000
r3 : 00000001 r2 : 00000001 r1 : 00000260 r0 : 00000000
Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment none
Control: 10c5387d Table: 3949404a DAC: 00000051
Process sh (pid: 732, stack limit = 0x8ba716d6)
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Init ENET RGMII tx clock source, set GPR5[9] to select clock from
internal PLL_enet. And set phy VDDIO to 1.8V that get better signal
quality.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: d7a171fcf5218166f558428610ca8e9cb9f7e830)
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
The management data input/output (MDIO) bus where often high-speed,
open-drain operation is required. i.MX7D TO1.0 ENET MDIO pin has no
open drain as IC ticket number: TKT252980, i.MX7D TO1.1 fix the issue.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit: a747abd5f01d278b91d1b6ee6628e1935cb7b23c)
Conflicts:
arch/arm/mach-imx/mach-imx7d.c
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Enet get MAC address order:
From module parameters or kernel command line -> device tree ->
pfuse -> mac registers set by bootloader -> random mac address.
When there have no "fec.macaddr" parameters set in kernel command
line, enet driver get MAC address from device tree. And then if
the MAC address set in device tree and is valid, enet driver get
MAC address from device tree. Otherwise,enet get MAarch/arm/mach-imx
/mach-imx6q.c address from
pfuse. So, in the condition, update the MAC address (read from pfuse)
to device tree.
Cherry-pick & Merge patches from:
149ac988a25b8d8eb86d05679cbb7b42819ff7a1 &
3269e5c06bdb2f7ab9bd5afa9bbfe46d872197d3
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Add i.MX7ULP suspend/resume support, including standby mode
and mem mode, mapped to VLPS and VLLS mode.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
The imx8m_pm_domain driver is used by i.MX8M SOC family, so enable
the IMX8M_PM_DOMAINS config for ARCH_MXC platform by default.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Because that the mailbox MU driver is used in i.MX RPMSG implementation.
There is a confliction between this MU driver and the mailbox MU driver.
To back-compaible with LPM of iMX6SX, iMX7D and iMX7ULP.
Rename the compatible node of this MU driver.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
The 100MTS low bus mode can be only supported by i.MX8MQ Rev2.1 and
future TO. So necessary check is added to identify the chip revision
when doing busfreq mode switch.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Use soc_device_metch instead of global imx_get_soc_revision
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
This reverts commit 7560cff21b7b92127675d5e955874af2827a9bca.
drivers/soc/imx/busfreq-imx8mq.o: In function `reduce_bus_freq':
/home/b29396/Work/linux/dash-linux-devel/build_v8/../drivers/soc/imx/busfreq-imx8mq.c:193: undefined reference to `imx_get_soc_revision'
/home/b29396/Work/linux/dash-linux-devel/build_v8/../drivers/soc/imx/busfreq-imx8mq.c:120: undefined reference to `imx_get_soc_revision'
drivers/soc/imx/busfreq-imx8mq.o: In function `set_high_bus_freq':
/home/b29396/Work/linux/dash-linux-devel/build_v8/../drivers/soc/imx/busfreq-imx8mq.c:327: undefined reference to `imx_get_soc_revision'
/home/b29396/Work/linux/dash-linux-devel/Makefile:1052: recipe for target 'vmlinux' failed
make[1]: *** [vmlinux] Error 1
upstream kernel did not export imx_get_soc_revision for mx8.
Need find a better way to support for both mx8m and mx8.
This patch fixes coverity issue of "divide by 0".
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit ed044f6d78156ae603dd732f15c5268d3f545605)
The 100MTS low bus mode can be only supported by i.MX8MQ Rev2.1 and
future TO. So necessary check is added to identify the chip revision
when doing busfreq mode switch.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit a906afb17d445b40f6c70fa2a2c3b6707ada0e47)
add busfreq support on i.MX8MM. when system is running at low bus or
audio bus mode, the dram & bus clock will be reduced to a lower rate:
NOC: 150MHZ, AXI: 24MHz, AXI 20MHZ, DRAM core clock: 25MHz.
when system is running at high bus mode, all the bus clock and dram
clock will be restore to the highest one.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 4984e653a6e86f7b6e2e6c195be53da8dcb5f8fd)
Guoniu.zhou