In order to avoid the name problem going forward with
integration with Qcom, Qcom has their own dsp and hifi
is competitor, so the hifi name should not be used in
our code.
So use the name of dsp instead of hifi to fix this
problem.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
The logic of 'if' check for the mult is wrong, this will lead
to set rate to PLL type failed. Additionally, remove the
unnecessary 'CLK_IS_CRITICAL' flags.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Correct pixel and ipg clock register for CI_PI ss
Reviewed-by: ranjani.vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Confirm with IC, HS400 MAX clock Freq for Instance 0 is 198Mhz
and for Instance 1 is 192MHz, so set the usdhc parent clock at
396MHz, due to current APLL is config to 529.2MHz, use the formula
APLL_PFD clock = APLL * 18 / i, the nearest clock is 381.024MHz when
the i is 25, so the usdhc root clock is 190.512MHz.
But eMMC HS400 can't pass stress test at 190.512MHz, will meet CRC
error sometimes, only when down to 176.4MHz can pass the stress test.
This patch make the usdhc0 and usdhc1 root clock both source from
IMX7ULP_CLK_APLL_PFD1, and set this APLL_PFD1 clcok rate at 352.8MHz,
and set the USDHC0 root clock at 352.8MHz, and set the USDHC1 root
clock at 176.4MHz.
Also remove the clk_prepare_enable() and clk_disable_unprepare() for
APLL_PFD2, bacause U-Boot already gate off APLL_PFD1, not need to do
this again.
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
- To save power consumption, PHY related CLKs can be
gated off after the configurations are done.
- The impedance ratio should be configured refer to
differnet REXT values.
0x6c <--> REXT valuse is 85Ohms
Default values 0x80 <--> REXT value is 100Ohms.
- IMX8QM_HSIO_PHY_X1_APB_CLK is mandatory required when
access SATA PHY registers. Change the power domain to SATA.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
The sc api error code is not compatible with Linux error code,
directly returning the sc api error code to caller is wrong.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
If spinlock debug is enabled there are BUG_ON asserts in
place for default values on the spinlock_t members.
DEFINE_SPINLOCK declares and initializes the spinlock and
avoids triggering those.
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Tested-by: Marius Vlad <marius-cristian.vlad@nxp.com>
Acked-By: Marius Vlad <marius-cristian.vlad@nxp.com>
commit 97b8a6eed4eee19ec8a60dedfffc2f5f3d8933c5
Author: Chuck Cannon <chuck.cannon@freescale.com>
Date: Tue Feb 6 08:54:16 2018 -0600
Add unique ID API call. Required to get info needed for SECO fuse
programming. Added info command to DM.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
According to the clk digram in section 24.6 Core, Platform and System Bus
clocks in reference manual, the correct available periph_bus_sels should be
{ "dummy", "sosc_bus_clk", "mpll", "firc_bus_clk", "rosc", "nic1_bus",
"nic1_div", "spll_bus_clk", }.
And the real tpm/pwm/lpuart parent clock should be IMX7ULP_CLK_SOSC_BUS_CLK
while some others should be IMX7ULP_CLK_FIRC_BUS_CLK, So update dts as well.
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
According to the clk digram in section 24.6 Core, Platform and System Bus
clocks in reference manual, periph_slow_sels should be better renamed to
periph_bus_sels to avoid confusing.
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Add missing sosc_bus_clk/firc_bus_clk/spll_bus_clk clocks which will be used
by other devices later.
All these clocks use the same divider as ddr_div, so ulp_div_table is used.
Besides that, all these clocks need to be controlled by M4, so
CLK_DIVIDER_READ_ONLY is also specified.
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
According to reference manual, none of them should specify CLK_SET_RATE_GATE,
So switch them to imx_clk_divider_flags with only CLK_SET_RATE_PARENT kept.
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
According to reference manual, all these mux clocks requires operation
with their parent clocks were enabled previously.
So switch them to imx_clk_mux2 type which has CLK_OPS_PARENT_ENABLE
flag. Also remark some critical clocks in case they're disabled.
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
According RM, ddr_div clock actually is not CLK_DIVIDER_ONE_BASED type,
we need use a clk_div_table to handle its special divider value.
Besides that, due to 0 DDRDIV means output is disabled, so we also need
specify CLK_DIVIDER_ZERO_GATE for it.
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Current imx_clk_composite used for GPIO clock definition is wrong
as GPIO has no mux support according to reference manual.
Instead, we can only use imx_clk_gate for it.
This patch also fixes some code indent issue.
Fixes: ("1a86f07ce6a2 MLK-13485-4 clk: imx7ulp: add gpio port control clocks")
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Since patch ("gpio-vf610: add getting necessary clocks support"),
GPIO clocks will be handled by its driver.
No need put them in clks_init_on which should be only for system
critical clocks.
Fixes: ("1a86f07ce6a2 MLK-13485-4 clk: imx7ulp: add gpio port control clocks")
Acked-by: Peter Chen <peter.chen@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Kernel already supports fractional divider and we switched to it.
See: drivers/clk/clk-fractional-divider.c
So no need keep our private clk-frac-divider copy now which functions
the same, delete it.
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Kernel already supports fractional divider.
See: drivers/clk/clk-fractional-divider.c
After patch: ("clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED
flag support"), it can supports ZERO based dividers now which be used by
IMX ULP.
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
The orphan clocks reparent operation should be moved after the critical
clocks enabled, otherwise it may get a chance to disable a newly
registered critical clock which triggers the following warning.
Assuming we have two clocks: A and B, B is the parent of A.
Clock A has flag: CLK_OPS_PARENT_ENABLE
Clock B has flag: CLK_IS_CRITICAL
Step 1:
Clock A is registered, then it becomes orphan.
Step 2:
Clock B is registered. Before clock B reach the critical clock enable
operation, orphan A will find the newly registered parent B and do
reparent operation, then parent B will be finally disabled in
__clk_set_parent_after() due to CLK_OPS_PARENT_ENABLE flag as there's
still no users of B which will then trigger the following warning.
[ 0.000000] WARNING: CPU: 0 PID: 0 at drivers/clk/clk.c:597 clk_core_disable+0xb4/0xe0
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.11.0-rc1-00056-gdff1f66-dirty #1373
[ 0.000000] Hardware name: Generic DT based system
[ 0.000000] Backtrace:
[ 0.000000] [<c010c4bc>] (dump_backtrace) from [<c010c764>] (show_stack+0x18/0x1c)
[ 0.000000] r6:600000d3 r5:00000000 r4:c0e26358 r3:00000000
[ 0.000000] [<c010c74c>] (show_stack) from [<c040599c>] (dump_stack+0xb4/0xe8)
[ 0.000000] [<c04058e8>] (dump_stack) from [<c0125c94>] (__warn+0xd8/0x104)
[ 0.000000] r10:c0c21cd0 r9:c048aa78 r8:00000255 r7:00000009 r6:c0c1cd90 r5:00000000
[ 0.000000] r4:00000000 r3:c0e01d34
[ 0.000000] [<c0125bbc>] (__warn) from [<c0125d74>] (warn_slowpath_null+0x28/0x30)
[ 0.000000] r9:00000000 r8:ef00bf80 r7:c165ac4c r6:ef00bf80 r5:ef00bf80 r4:ef00bf80
[ 0.000000] [<c0125d4c>] (warn_slowpath_null) from [<c048aa78>] (clk_core_disable+0xb4/0xe0)
[ 0.000000] [<c048a9c4>] (clk_core_disable) from [<c048be88>] (clk_core_disable_lock+0x20/0x2c)
[ 0.000000] r4:000000d3 r3:c0e0af00
[ 0.000000] [<c048be68>] (clk_core_disable_lock) from [<c048c224>] (clk_core_disable_unprepare+0x14/0x28)
[ 0.000000] r5:00000000 r4:ef00bf80
[ 0.000000] [<c048c210>] (clk_core_disable_unprepare) from [<c048c270>] (__clk_set_parent_after+0x38/0x54)
[ 0.000000] r4:ef00bd80 r3:000010a0
[ 0.000000] [<c048c238>] (__clk_set_parent_after) from [<c048daa8>] (clk_register+0x4d0/0x648)
[ 0.000000] r6:ef00d500 r5:ef00bf80 r4:ef00bd80 r3:ef00bfd4
[ 0.000000] [<c048d5d8>] (clk_register) from [<c048dc30>] (clk_hw_register+0x10/0x1c)
[ 0.000000] r9:00000000 r8:00000003 r7:00000000 r6:00000824 r5:00000001 r4:ef00d500
[ 0.000000] [<c048dc20>] (clk_hw_register) from [<c048e698>] (_register_divider+0xcc/0x120)
[ 0.000000] [<c048e5cc>] (_register_divider) from [<c048e730>] (clk_register_divider+0x44/0x54)
[ 0.000000] r10:00000004 r9:00000003 r8:00000001 r7:00000000 r6:00000003 r5:00000001
[ 0.000000] r4:f0810030
[ 0.000000] [<c048e6ec>] (clk_register_divider) from [<c0d3ff58>] (imx7ulp_clocks_init+0x558/0xe98)
[ 0.000000] r7:c0e296f8 r6:c165c808 r5:00000000 r4:c165c808
[ 0.000000] [<c0d3fa00>] (imx7ulp_clocks_init) from [<c0d24db0>] (of_clk_init+0x118/0x1e0)
[ 0.000000] r10:00000001 r9:c0e01f68 r8:00000000 r7:c0e01f60 r6:ef7f8974 r5:ef0035c0
[ 0.000000] r4:00000006
[ 0.000000] [<c0d24c98>] (of_clk_init) from [<c0d04a50>] (time_init+0x2c/0x38)
[ 0.000000] r10:efffed40 r9:c0d61a48 r8:c0e78000 r7:c0e07900 r6:ffffffff r5:c0e78000
[ 0.000000] r4:00000000
[ 0.000000] [<c0d04a24>] (time_init) from [<c0d00b8c>] (start_kernel+0x218/0x394)
[ 0.000000] [<c0d00974>] (start_kernel) from [<6000807c>] (0x6000807c)
[ 0.000000] r10:00000000 r9:410fc075 r8:6000406a r7:c0e0c930 r6:c0d61a44 r5:c0e07918
[ 0.000000] r4:c0e78294
[ 0.000000] ---[ end trace 0000000000000000 ]---
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and
denominator value in register are start from 0.
This can be used to support frac dividers like below:
Divider output clock = Divider input clock x [(frac +1) / (div +1)]
where frac/div in register is:
000b - Divide by 1.
001b - Divide by 2.
010b - Divide by 3.
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
For dividers with zero indicating clock is disabled, instead of giving a
warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not
set" in exist code, we'd like to introduce enable/disable function for it.
e.g.
000b - Clock disabled
001b - Divide by 1
010b - Divide by 2
...
Set rate when the clk is disabled will cache the rate request and only
when the clk is enabled will the driver actually program the hardware to
have the requested divider value. Similarly, when the clk is disabled we'll
write a 0 there, but when the clk is enabled we'll restore whatever rate
(divider) was chosen last.
It does mean that recalc rate will be sort of odd, because when the clk is
off it will return 0, and when the clk is on it will return the right rate.
So to make things work, we'll need to return the cached rate in recalc rate
when the clk is off and read the hardware when the clk is on.
NOTE for the default off divider, the recalc rate will still return 0 as
there's still no proper preset rate. Enable such divider will give user
a reminder error message.
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Clk core using different locks for clk_enable/disable and clk_set_rate.
Driver should protect them if accessing the same resource.
Fixes: 78ef764871d6 ("MLK-13441-5 ARM: imx: add new clk types")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Give a warning when get an invalid pfd index.
Cc: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
According to reference manual, pfdv2 can't set rate without gating clock.
So we should add CLK_SET_RATE_GATE flag accordingly.
Fixes: 78ef764871d6 ("MLK-13441-5 ARM: imx: add new clk types")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Currently using 'div' name for the PLL multiplier defined in RM which is a
bit confusing. So fix it.
Fixes: 78ef764871d6 ("MLK-13441-5 ARM: imx: add new clk types")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
There's no meaning to add members for fixed register offset and mask.
This using seems to be derived from MX6 PLL code but not suitable for
ULP up till now.
Cc: Anson Huang <Anson.Huang@nxp.com>
Fixes: 78ef764871d6 ("MLK-13441-5 ARM: imx: add new clk types")
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
According to reference manual, the Valid MULT values are 33, 27, 22,
20, 17, 16. Not the ranges from 16 to 30 currently used.
Fixes: 78ef764871d6 ("MLK-13441-5 ARM: imx: add new clk types")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
PLL_EN bit set means pll enabled, not disabled.
Fixes: 78ef764871d6 ("MLK-13441-5 ARM: imx: add new clk types")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
According to reference manual, this pll can't set rate without gating
clock. So we should add CLK_SET_RATE_GATE flag accordingly.
Cc: Anson Huang <Anson.Huang@nxp.com>
Cc: Bai Ping <ping.bai@nxp.com>
Fixes: 78ef764871d6 ("MLK-13441-5 ARM: imx: add new clk types")
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
'CKIL' clock name is derived from MX6 SoC series which is invalid for
MX7ULP (can't find it from RM). Changing it to the correct 'ROSC'
which is defined in RM.
The exist 'OSC' name is also changed accordingly which should be SOSC
(System OSC).
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
On i.MX7ULP B0 chip, nic1_divbus's parent is changed to
from nic0_div directly, update it accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Currently the clock parent actually is failed to be restored in power
domain driver due to the set_parent will bail out early as the clk core
already cached the same old parent.
Implement a CLK_SET_PARENT_NOCACHE flag in clk core and register all
SC mux clocks with this flag to make sure the clk core won't bypass
the SC clock parent setting.
[ Aisheng: "Add commit message" ]
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
On i.MX7ULP B0 chip, snvs is located in M4 domain, remove
snvs clock from linux clock tree;
Use SMC PMCTRL RUNM field for ARM clock mux instead
of reserved register in SCG, as when CPU frequency changes,
RUNM field will switch between RUN and HSRUN, ARM clock
source will be changed accordingly, so RUNM can be used as
a clock mux.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
The CCGR RAWNAND is shared by apbh-dma and gpmi clocks, so must use
imx_clk_gate2_shared2 to produce two clocks. Otherwise, apbh-dma clock
won't be enabled individually.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Add uSDHC clock MUX to allow uSDHC driver to select
parent, currently only support PLL0 and PLL1 as
uSDHC clock's parent.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Haibo Chen <haibo.chen@nxp.com>
When the system reaches the passive critical trip point, VPU device cooling
need to change the clock rate on the fly. So change the VPU related clocks
flags to make sure the clock rate can be changed successfully.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Keep TZASC clock on. With TEE enabled, TZASC enabled, if disable
tzasc clock, system may hang up.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Add CLKO2 for i.MX8MQ
Set parent for MIPI CSI1/2 CORE/PHY_REF/ESC
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
reduce the NOC, main AXI and AHB bus clock frequency to save power when DDR enter low
frequency mode. VDDSOC is ~195mA during video play, and ~180mA in idle.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
The Video PLL2 has a output enable bit to do clk gate,
So we need to register this gate to save power.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Add missing clocks for MIPI-DSI SS: RX_ESC and TX_ESC
Also added the posibility to select clock parents for MIPI-DSI versus
LVDS.
The SCFW was changed, so now the LVDS pixel and phy clocks need to
specify their parrents.
Also, the TX_ESC and RX_ESC clocks from MIPI-DSI need to specify their
parrents in DTS files.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Support M4/A53 work together
1. add imx_src_is_m4_enabled
2. introduce a new dts dedicated for m4
3. add more pwm nodes
4. Since clk initialization is at very early stage, add m4 enabled check
in the beginning of clk code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
On i.MX8MQ, the dram core clock can be sourced from dram_pll or
the dram_alt clock, when sourced from the dram_alt, it has a fix
divider(1/4). When the DDRC core clock is lower than 800MHz, we
can swith the core clock to dram_alt source.
The dram apb clock's mux option 2 should be sys1_pll_40m, so fixed it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Correct the pd of the sata phy pclk.
BuildInfo:
- SCFW 9559d5ec, IMX-MKIMAGE 06bc2767, ATF
- U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g6dc7b0f
Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
The resource id of HDMI I2S clock is SC_R_HDMI_I2S, and SAI HDMITX
and HDMIRX clock need FUNCTION_NAME paremeter.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Right now the imx8qm clock provider hardcodes physical addresses. In
virtualization scenarios the intermediate physical addresses visible
from a guest can be different. In theory a 1:1 mapping could be done but
that in xen it would overlap with hardcoded guest ram starting at
0x40000000.
Solve this by adding a property with a common offset for all lpcg
areas. This should be set in the guest dts.
In theory each lpcg block could be remapped with it's own offset but
that is not supported.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
Registering clocks for unowned resources can result in lots of pointless
scfw errors and potential faults when attempting to use LPCG.
Solve this by checking ownership via sc_rm_is_resource_owned and
returning -ENODEV from clock registration functions. The top-level clock
provider is also modified so that it accepts such errors silently.
This is intended for xen but could also be useful for SCFW partitioning.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
All this does is replace the cast from physical address with a macro in
order to make later changes easier.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
This can happen in virtualization scenarios, so just skip registering
the associated clocks instead of failing to boot.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
DC clocks can choose their clock source between PLL1, PLL2 and
bypass input.
This patch introduces a multiplexer in the dc clock topology to
allow this choice and introduces one set of parents that will be used
for both display0 and display1 clocks.
Clock paths tested:
1. PLL2(dc0_pll1_clk)->DC0_DISP1(dc0_disp1_clk)->LVDS
2. BYP(dc0_bypass0_clk)->DC0_DISP1(dc0_disp1_clk)->LVDS
(BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0)
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Reviewed by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
Display clocks can choose their parrent between various clock sources
(ex pll1, pll2, bypass).
This patch adds a new mux type that uses the underlying support in scfw
to set/get a parent.
(BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0)
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Reviewed by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
This is a change similar to:
'commit 01fdf7bf572b ("MLK-16281-2: clk-imx8qm: Fix GPT clock hierarchy")'
There are five gpt modules on imx8qm (gpt0 .. gpt4).
Of these, gpt2 and gpt4 clock hierarchies are inconsistent
with the rest.
Having the per clocks (gpt_hf_clk and gpt_clk) as children of the
peripheral access clock (ipg_s) and bus sync slave clock
(ipg_slv_clk)
ensures that the latter are enabled when the driver enables the
gpt_clk
(or hf).
This patch reconciles these two gpt clock trees with the rest.
Before:
gpt_2_div
gpt_2_hf_clk
gpt_2_ipg_s_clk
gpt_2_ipg_slv_clk
gpt_2_clk
gpt_4_div
gpt_4_hf_clk
gpt_4_clk
gpt_4_ipg_s_clk
gpt_4_ipg_slv_clk
After:
gpt_2_div
gpt_2_ipg_s_clk
gpt_2_ipg_slv_clk
gpt_2_hf_clk
gpt_2_clk
gpt_4_div
gpt_4_ipg_s_clk
gpt_4_ipg_slv_clk
gpt_4_hf_clk
gpt_4_clk
Apply this change for imx8qxp also which has the same inconsistency
regarding the gpt clocks.
(BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE imx8-mu, ATF 0)
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
The current clk_mux_set_parent_scu() implementation returns error
if device power domain is not enabled. As consequence of this the
existing "assigned-clock-parents" DTS functionality cannot be used for
clk_mux. In order to avoid returning error in "set_parent" the code is
refactored as follows:
a) On "set_parent" the "mux->reg" value is prepared and stored in
"mux->val" field. The "mux->reg" is updated if power domain is enabled,
or triggered for update on "prepare" subsequent call otherwise.
b) On "prepare" the power domain status check is performed and "mux->val"
is stored in "mux->reg" if triggered for update.
c) On "get_parent" the "mux->reg" is not read anymore and "mux->val" is
used to get the "get_parent" output.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
There are five gpt modules on imx8qm (gpt0 .. gpt4).
Of these, gpt2 and gpt4 clock hierarchies are inconsistent with the
rest.
Having the per clocks (gpt_hf_clk and gpt_clk) as children of the
peripheral access clock (ipg_s) and bus sync slave clock (ipg_slv_clk)
ensures that the latter are enabled when the driver enables the gpt_clk
(or hf).
This patch reconciles these two gpt clock trees with the rest.
Before:
gpt_2_div
gpt_2_hf_clk
gpt_2_ipg_s_clk
gpt_2_ipg_slv_clk
gpt_2_clk
gpt_4_div
gpt_4_hf_clk
gpt_4_clk
gpt_4_ipg_s_clk
gpt_4_ipg_slv_clk
After:
gpt_2_div
gpt_2_ipg_s_clk
gpt_2_ipg_slv_clk
gpt_2_hf_clk
gpt_2_clk
gpt_4_div
gpt_4_ipg_s_clk
gpt_4_ipg_slv_clk
gpt_4_hf_clk
gpt_4_clk
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Some gpt clocks are defined twice which results in:
gpt0_div
gpt0_clk
and also:
gpt_0_div
gpt_0_ipg_s_clk
gpt_0_ipg_slv_clk
gpt_0_hf_clk
gpt_0_clk
The second version is correct as per gpt lpcg cell.
This patch removes the first set of clocks.
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Previous code don't take care about the i.MX6QP revision update of
new TO. So improve the code to include future TO support for i.MX6QP.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Need to put the sentinel value to the end of the of_device_id array.
This patch also fixes the following KASAN complains when KASAN is enabled:
[ 0.671315] ==================================================================
[ 0.678400] BUG: KASAN: global-out-of-bounds in __of_match_node+0x70/0xb8 at addr ffff2000092958a8
[ 0.687321] Read of size 1 by task swapper/0/1
[ 0.691760] Address belongs to variable imx8qm_match+0xc8/0x260
[ 0.697666] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.11-03033-ge2e5fb2 #44
[ 0.704955] Hardware name: Freescale i.MX8QM ARM2 (DT)
[ 0.710081] Call trace:
[ 0.712528] [<ffff20000808b438>] dump_backtrace+0x0/0x278
[ 0.717907] [<ffff20000808b6c4>] show_stack+0x14/0x20
[ 0.722949] [<ffff2000085311ec>] dump_stack+0xa4/0xc8
[ 0.727990] [<ffff200008256cbc>] kasan_report_error+0x4c4/0x4d8
[ 0.733892] [<ffff2000082570f8>] kasan_report+0x40/0x48
[ 0.739103] [<ffff2000082552cc>] __asan_load1+0x4c/0x58
[ 0.744318] [<ffff200008d7ac28>] __of_match_node+0x70/0xb8
[ 0.749791] [<ffff200008d7aca8>] of_match_node+0x38/0x60
[ 0.755088] [<ffff200008d7d870>] of_match_device+0x30/0x50
[ 0.760565] [<ffff200008858dbc>] platform_match+0x6c/0x130
[ 0.766040] [<ffff200008855dec>] __device_attach_driver+0x5c/0x138
[ 0.772205] [<ffff200008852d18>] bus_for_each_drv+0xd0/0x130
[ 0.777852] [<ffff2000088557fc>] __device_attach+0x13c/0x1a0
[ 0.783499] [<ffff200008855f30>] device_initial_probe+0x10/0x18
[ 0.789406] [<ffff200008854608>] bus_probe_device+0xe0/0xf0
[ 0.794965] [<ffff200008851310>] device_add+0x5c8/0x818
[ 0.800176] [<ffff200008d7dc3c>] of_device_add+0x5c/0x88
[ 0.805477] [<ffff200008d7e854>] of_platform_device_create_pdata+0xb4/0x118
[ 0.812426] [<ffff200008d7e8cc>] of_platform_device_create+0x14/0x20
[ 0.818771] [<ffff200009913374>] arm_smmu_of_init+0x38/0x50
[ 0.824332] [<ffff200009913298>] of_iommu_init+0xa4/0x100
[ 0.829715] [<ffff200008083990>] do_one_initcall+0x90/0x1c8
[ 0.835278] [<ffff2000098c1034>] kernel_init_freeable+0x290/0x330
[ 0.841361] [<ffff20000905be28>] kernel_init+0x10/0x110
[ 0.846567] [<ffff200008083680>] ret_from_fork+0x10/0x50
[ 0.851860] Memory state around the buggy address:
[ 0.856648] ffff200009295780: fa fa fa fa 00 03 fa fa fa fa fa fa 00 00 00 00
[ 0.863854] ffff200009295800: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[ 0.871065] >ffff200009295880: 00 00 00 00 00 fa fa fa fa fa fa fa 00 00 00 00
[ 0.878270] ^
[ 0.882792] ffff200009295900: 02 fa fa fa fa fa fa fa 00 00 07 fa fa fa fa fa
[ 0.890003] ffff200009295980: 00 00 00 00 01 fa fa fa fa fa fa fa 00 00 00 00
[ 0.897208] ==================================================================
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
enable/disable are not allowed to sleep.
For clk_gate3_scu these functions use calls into scfw that may sleep.
Move this functionality into prepare/unprepare to avoid that.
Patch also adds is_prepared callback.
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Add support to get the clock rate of a gate clock. This is required
to save/restore devices clocks when they are powered up/down.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Define three root clocks for DCSS module:
.IMX8MQ_CLK_DISP_AXI_ROOT
.IMX8MQ_CLK_DISP_APB_ROOT
.IMX8MQ_CLK_DISP_RTRM_ROOT
These root clocks share one clock gate along with
'IMX8MQ_CLK_DISP_ROOT' clock. So change its type
to be shared gate clock too.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Peng Fan