Agis Zisimatos
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6dba8e700b
|
Replace single resistors with resistor network
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2022-04-11 09:58:56 +00:00 |
Agis Zisimatos
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0ea9754b22
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Fix FPGA symbol anotation and footprint
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-08 18:07:34 +03:00 |
Ilias Daradimos
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8eca352efe
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Restore footprints
Add RBF diode
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-04-08 14:09:25 +03:00 |
Agis Zisimatos
|
62e9a7579b
|
Add SERDES bank and connect supply voltaged to GND
* Add a fpga-power sheet
* Add auto updated kicad files
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-04-08 11:28:44 +03:00 |
Agis Zisimatos
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791fa839b6
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Remove unused test points
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2022-04-07 17:52:45 +00:00 |
Papadeas Pierros
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cb2ff9e057
|
Replace diode footprints and jumpers in CAN
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
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2022-04-07 15:30:01 +03:00 |
Ilias Daradimos
|
3ea2211549
|
Update footprints
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-04-07 11:21:18 +03:00 |
Ilias Daradimos
|
17e77121dc
|
Add latching mechanism
Signed-off-by: Ilias Daradimos <ilias@libre.space>
|
2022-04-07 11:07:47 +03:00 |
Ilias Daradimos
|
d9640c0ea0
|
Add RBF/Kill ports
Add can footprint
Signed-off-by: Ilias Daradimos <ilias@libre.space>
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2022-04-06 23:27:16 +03:00 |
Agis Zisimatos
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21e81aed53
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Fix connection of INITN and DONE
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-04-06 19:16:15 +03:00 |
Agis Zisimatos
|
5754075d13
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Add changes of auto updated KiCad files
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-04-06 18:50:03 +03:00 |
Agis Zisimatos
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625d39c64e
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Add missing pull-up resistor
Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-04-05 19:54:51 +03:00 |
Agis Zisimatos
|
94313541b0
|
Clean up the FPGA schematic from comments
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-05 19:54:51 +03:00 |
Agis Zisimatos
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bdd3c06adf
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Add decoupling capacitors in FPGA schematic
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-04-05 19:54:51 +03:00 |
Ilias Daradimos
|
80eade29ba
|
Change battery footprint
Signed-off-by: Ilias Daradimos <ilias@libre.space>
|
2022-04-05 16:00:20 +03:00 |
Ilias Daradimos
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cf1e87d61d
|
Assign footprints
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2022-04-05 14:39:51 +03:00 |
Agis Zisimatos
|
be0d0789f9
|
Add FPGA_INIT to MCU, fixes #13
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-04-05 11:27:50 +03:00 |
Agis Zisimatos
|
c3122ab59c
|
Add oscillator in FPGA
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-04-05 11:06:18 +03:00 |
Agis Zisimatos
|
fb9e050bc9
|
Add test points for GPIOs
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-04-05 11:06:18 +03:00 |
Agis Zisimatos
|
8b5c631826
|
Add MSPI as default boot mode and NOR flash
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-04-05 11:06:18 +03:00 |
Agis Zisimatos
|
0e86bb6f49
|
Add LED indicators for DONE and INITN
Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-04-05 11:06:18 +03:00 |
Agis Zisimatos
|
84e1cc8608
|
Implement FPGA JTAG
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-04-05 11:01:35 +03:00 |
Agis Zisimatos
|
e749327cc2
|
Place I/Q and SPI of FPGA
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-04-05 11:01:35 +03:00 |
aris12
|
51240ee009
|
add antenna deployment
|
2022-04-04 17:54:24 +03:00 |
aris12
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e76ce376e0
|
Add auto generated Kicad changes
|
2022-04-04 17:52:47 +03:00 |
Papadeas Pierros
|
bd4ef8fe52
|
Expose PV as top level sheet
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
|
2022-04-01 10:46:44 +03:00 |
Papadeas Pierros
|
929c19d30a
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Fix PWR flag
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
|
2022-03-30 16:37:00 +03:00 |
Agis Zisimatos
|
f524588635
|
Fix footprints that changed by previous commit
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-03-30 11:38:37 +03:00 |
Agis Zisimatos
|
420d3a0f91
|
Update symbols and footprints in power schematic
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-03-30 10:36:34 +03:00 |
Agis Zisimatos
|
fef6cc6ec3
|
Add pull-down resistor in load switch ON pin
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-03-29 19:48:29 +03:00 |
Agis Zisimatos
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6654506502
|
Add transceiver TCXO
Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/17
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-03-29 19:23:07 +03:00 |
Agis Zisimatos
|
95c29a28e7
|
Add current limit resistor value
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-03-29 19:05:22 +03:00 |
Agis Zisimatos
|
74dad42969
|
Fixes in FPGA power schematic
- Add ferrite bead part number
- Fixes ERC error in PG of 1.1V pin
- Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-03-29 18:20:43 +03:00 |
Papadeas Pierros
|
8fbf9d13b1
|
Assign footprints for power and mcu.
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
|
2022-03-29 16:55:13 +03:00 |
Vasilis Tsiligiannis
|
12a4feb2ed
|
Add LSF contribution guide
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
|
2022-03-28 10:27:31 +03:00 |
Agis Zisimatos
|
e73022566e
|
Select ferrite bead for TRX
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-03-23 17:24:58 +02:00 |
Agis Zisimatos
|
f03aa75813
|
Select I limit resistor
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-03-23 16:53:05 +02:00 |
Ilias Daradimos
|
055c01d8fa
|
Move GND power flag to top sheet
Update symbols
Signed-off-by: Ilias Daradimos <ilias@libre.space>
|
2022-03-22 13:23:56 +02:00 |
Ilias Daradimos
|
b8ad60e557
|
Reanotate sheets
Update symbol and port direction
Signed-off-by: Ilias Daradimos <ilias@libre.space>
|
2022-03-22 12:29:50 +02:00 |
Agis Zisimatos
|
57d5d87f9f
|
Fixes uuid, maybe it is bug from previous version
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-03-22 11:21:57 +02:00 |
Agis Zisimatos
|
9d3e6155ef
|
Add PSU for FPGA
Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-03-22 11:19:58 +02:00 |
Agis Zisimatos
|
0c57d0fecc
|
Add ferrite bead in 3V3 supply voltage
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-03-22 11:19:06 +02:00 |
Agis Zisimatos
|
334406da80
|
Add initial transceiver schematic
Fixes #https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/5
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
|
2022-03-17 21:17:23 +02:00 |
Papadeas Pierros
|
046229765a
|
Add interfaces between modules (closes #1)
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
|
2022-03-16 20:03:26 +02:00 |
Ilias Daradimos
|
5af3e504fc
|
Add PV charging
Added bus charging
Signed-off-by: Ilias Daradimos <ilias@libre.space>
|
2022-03-16 15:26:59 +02:00 |
Ilias Daradimos
|
cec9c42157
|
Add 3.3V PSU
Add Battery monitor
Add 2.5V regulator
Add 1.1V regulator
Signed-off-by: Ilias Daradimos <ilias@libre.space>
|
2022-03-16 15:26:05 +02:00 |
Ilias Daradimos
|
767a1432b2
|
Update battery-monitor.kicad_sch
|
2022-03-16 14:34:04 +02:00 |
Papadeas Pierros
|
d98f5d08a7
|
Add MCU module schematic
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
|
2022-03-15 19:25:35 +02:00 |
Vasilis Tsiligiannis
|
7308bbf9eb
|
Fix license to CERN-OHL-S
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
|
2022-03-02 16:17:38 +02:00 |
Vasilis Tsiligiannis
|
3c07252fae
|
Add initial KiCad project
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
|
2022-02-21 13:11:33 +02:00 |