spacecruft
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sidloc-transceiver
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14 Commits (spacecruft)

Author SHA1 Message Date
Agis Zisimatos 7dd800fd65 Fix net names, PN and add connector for FE 
Fixes #57, #56, #58, #59, #52, #65

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-07-19 18:49:46 +03:00
Agis Zisimatos 6780198daf Update BOM and create iBOM 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-05-02 14:38:21 +03:00
Agis Zisimatos 538108bb67 Fix TPS22950 footprint 
Add the correct one for LSF-KiCAD library

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-30 17:48:22 +03:00
Agis Zisimatos cc07c2347f Add in-series resistors in FPGA-SPI 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-30 14:29:44 +03:00
Agis Zisimatos 8fc3b2df0d Update in PCB from sidloc schematic 
* Change SPI CLK of FPGA to L18
* Fixes #44 and #45

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-26 17:04:15 +03:00
Agis Zisimatos aa2a8d5806 Route power of FPGA and finalize I/Q connections 
* Fixes #29 and #31
* Add TP in VIN 3.3V from external

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-26 13:13:08 +03:00
Agis Zisimatos 65c1553f29 Add SPI routing of FPGA 
* Route pull-up resistors of NOR flash
* Small fixes in AT86RF215, fixes #30
* Route pull-up and down resistors of JTAG

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-19 19:27:25 +03:00
Agis Zisimatos 961e955dbd Fix SPI_CLK connection 
It had connected to CS

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-18 21:10:33 +03:00
Agis Zisimatos bbb8da9459 Initial part placement 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-11 19:07:49 +03:00
Agis Zisimatos 0f946970ff Assign footprints 
Use PQ9ish template

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-08 22:09:47 +03:00
Agis Zisimatos c9c6807e57 Fix interface with MCU breadboard 
Fixes #19

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-07 19:01:15 +03:00
Agis Zisimatos b4a8816f07 Add PQ9ish template 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-07 13:42:06 +03:00
Agis Zisimatos 751f54fc0b Initialize schematics and define connectors 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-06 21:10:42 +03:00
Vasilis Tsiligiannis 1f24b26fbe Initialize empty KiCad project 
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
 2022-03-15 18:35:16 +02:00