Agis Zisimatos
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7dd800fd65
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Fix net names, PN and add connector for FE
Fixes #57, #56, #58, #59, #52, #65
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-07-19 18:49:46 +03:00 |
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Agis Zisimatos
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77dad4e17f
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Fix clock-in in FPGA pins
Fixes #28
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-30 13:13:09 +03:00 |
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Agis Zisimatos
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12dd47cf35
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Define stack-up and manufacturer rules
* Define also net classes and pre-define traces and vias
* Fixes #2
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-12 16:31:58 +03:00 |
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Agis Zisimatos
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b4a8816f07
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Add PQ9ish template
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-07 13:42:06 +03:00 |
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Agis Zisimatos
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751f54fc0b
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Initialize schematics and define connectors
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
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2022-04-06 21:10:42 +03:00 |
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Vasilis Tsiligiannis
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1f24b26fbe
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Initialize empty KiCad project
Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
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2022-03-15 18:35:16 +02:00 |