Agis Zisimatos
8fc3b2df0d
Update in PCB from sidloc schematic
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* Change SPI CLK of FPGA to L18
* Fixes #44 and #45
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-26 17:04:15 +03:00
Agis Zisimatos
aa2a8d5806
Route power of FPGA and finalize I/Q connections
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* Fixes #29 and #31
* Add TP in VIN 3.3V from external
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-26 13:13:08 +03:00
Agis Zisimatos
ecf17cc8eb
Add debug LED for FPGA in PCB
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Fixes #42
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-19 19:57:11 +03:00
Agis Zisimatos
65c1553f29
Add SPI routing of FPGA
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* Route pull-up resistors of NOR flash
* Small fixes in AT86RF215, fixes #30
* Route pull-up and down resistors of JTAG
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-19 19:27:25 +03:00
Agis Zisimatos
d22b3f5865
Route AT86RF215M, fixes #30
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Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-18 22:12:15 +03:00
Agis Zisimatos
1230dde0f7
Place and route NOR flash
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Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-12 18:01:06 +03:00
Agis Zisimatos
12dd47cf35
Define stack-up and manufacturer rules
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* Define also net classes and pre-define traces and vias
* Fixes #2
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-12 16:31:58 +03:00
Agis Zisimatos
bbb8da9459
Initial part placement
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Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-11 19:07:49 +03:00
Agis Zisimatos
0f946970ff
Assign footprints
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Use PQ9ish template
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-08 22:09:47 +03:00
Agis Zisimatos
b4a8816f07
Add PQ9ish template
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Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
2022-04-07 13:42:06 +03:00
Vasilis Tsiligiannis
1f24b26fbe
Initialize empty KiCad project
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Signed-off-by: Vasilis Tsiligiannis <acinonyx@openwrt.gr>
2022-03-15 18:35:16 +02:00