Similar with QXP MEK we switch to ASRC to support
multiple rates.
Thus we introduce:
- asrc clocks
- make asrc PD depend on esai PD
Reviewed-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
(cherry picked from commit d804a5cac96d7d6071a2b4808a6ebe262f20952c)
DCSS needs special display timings for MIPI-DSI panel in order to do a
proper display on it.
In order to not break other display controller using this panel, add
custom display-timings for this specific use-case
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
- Since the l1ss is not enabled yet, configure
the clkreq# as gpio on 8qm/qxp mek boards.
Re-configure the clkreq# as input and open
drain when l1ss is enabled later.
- Correct the perst# configurations of 8qm.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
(cherry picked from commit cb7ec372ae90798a46b11e979243c3f058d8b26f)
Correct the interrupt line for adv7535.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Tested-by: Robert Chiras <robert.chiras@nxp.com>
Acked-by: Fancy Fang <chen.fang@nxp.com>
Because now DSP supports ASRC we need to power up pd_asrc0
each time pd_esai0 is powered up.
Current power domain tree looks like this:
* pd_audio
* pd_audio_clk0
* pd_audio_clk1
* pd_dma0_chan6
* pd_dma0_chan7
* pd_esai0
* pd_dma0_chan0
* pd_dma0_chan1
[....]
* pd_asrc0
We need to make pd_asrc0 dependent on pd_esai0, thus we move
pd_dm0_chan6 node as a child of pd_asrc0.
Thus, the new power domain hierarch will look like this:
* pd_audio
* pd_audio_clk0
* pd_audio_clk1
* pd_dma0_chan0
* pd_dma0_chan1
[....]
* pd_asrc0
* pd_dma0_chan6
* pd_dma0_chan7
* pd_esai0
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 04c4825baad9344e5f3dfa1c69de3957199d3ab0)
We introduce ASRC clocks (only "ipg", "mem", "asrc0..3" are
relevant for us), then remove ASRC related EDMA channels and
interrupts lines because they will be managed by DSP.
There is one more step required: fire up the power domain for ASRC
this is tricky and will be done in the next patch.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit e9e613dc18a732e82227028f1c822862448ddc22)
Once 32Khz low power clock enable for Murata 1CQ module, Bluetooth core
may enter low power idle status that cause HCI communication error when
HCI device is down for 2 seconds after initialization.
Currently, remove the LP 32Khz input for the module.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Correct the pad confirations of the pcie perst and epdev_on
on 8qm/qxp platforms.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit 28d5b68c1fa7568a2444915b71fab12e8a2d4350)
ISI channel 0,1 or 2,3 could concatenate to support 4K image.
ISI channel 1,2 couldn't support such function,
otherwise image will lost line data.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
(cherry picked from commit 18d3cf890a41ac773aefddd2ebe285d4b0197f5d)
Keep wlreg_on regulator on during system suspended status due to
external wifi module power requirement. Also keep the old Murata
1CQ M.2 card support.
To set the PIN to "latch" status before the GPIO controller is power
off during suspend, and set the PIN to "PASS" status after GPIO
controller status restored during system resume back.
Reviewed-by: yang.tian <yang.tian@nxp.com>
Tested-by: yang.tian <yang.tian@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit: 015599e40fd5cc942f8f6a8d4b6c3475440a114e)
This patch fixes the interrupts used by ADV7535. Initial patch
configured the GPIO0 IO00 as IO pin for the DSI_INT, used by ADV7535,
but the correct one is IO01, since IO00 is used by PWM.
Fixes: c2f1eceb5629 ("arm64: dts: imx8qm/qxp mek: Configure interrupts
for adv7535")
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
M4 will run flexspi XIP image on iMX8MM. Thus, we have to disable flexspi
in M4 dedicated DTS, otherwise the M4 will crash because flexspi probe
in kernel will re-configure the controller.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
(cherry picked from commit 2a370901a663bb518303ed2d5e774f1faa41f5fd)
Fix the wrong configuration of "dmas" in dts. This leads the spi
transfer error in dma mode and cause this issue.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
For ECSPI test, add these two dts files.
imx6ul-14x14-evk-ecspi.dts: enable ecspi4 function. Because ethernet2
uses the same pins with ecspi4, so disable fec1/fec2.
imx6ul-14x14-evk-ecspi-slave.dts: Add "spi-slave" attribute to enable
slave mode.
Wire Connection:
J1704:
3 - SCS
4 - MOSI
5 - MISO
6 - SCK
7 - GND
Modify "Makefile" to build these two dts files.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
- Fix busfreq optee mode to not install the linux assembly function
used to synchronize all CPU in case of SMP mode
- Fix l2cache OPTEE/Linux share mutex operations
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
(cherry picked from commit 68f47bb3328e56c63d647f855fc654f4736658ce)
Default value must be prefixed by "0".
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit e1f214bd631bda58ab7850866447a53e4a479ac8)
Default value must be prefixed by "0".
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 1a8e10215cc07c83b0e26b55fef94aae18151633)
a) Default value must be prefixed by "0".
b) Map 2 pins case to rx=0xff tx=0x11.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit cb4d69f098ee003edc2dcfec7075b043a78345e6)
Default value must be prefixed by "0".
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit a38075f068fd07dda55cb5bb5d74450ba29d6483)
Default value must be prefixed by "0".
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit b81a9884f85f750673a4ee0da60096d330add7a5)
a) Default value must be prefixed by "0".
b) Map 2 pins case to rx=0xff tx=0x11.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit bb1d5eac8b6ba4371ec04f362071c06cd3f5066b)
Default value must be prefixed by "0".
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 5252bd4b838eaa849fafdfa42a9e322a012a1e98)
Default value must be prefixed by "0".
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 4ce702331a6c7b5a84fe4fdc210b62147e04fa84)
Configure the interrupt for ADV7535 so that it can generate interrupts
events for HDP when the HDMI cable is plugged in or out.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
disable intmux in m4 dts for it is component in m4 domain
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 252831d4b0699c9ee609613a7c00ab8f77bfbeb9)
disable intmux in m4 dts for it is component in m4 domain
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 2742df294bac6e1ccc1ed7e899c0b5c85a51ccbf)
On i.MX8MM DDR4 EVK board, the GPIO pin to control LED is
NAND_CE3_B, correct it to make LED work properly and avoid
below failure message during kernel boot up:
[ 3.274994] leds-gpio leds: Error applying setting, reverse things back
[ 3.275015] leds-gpio: probe of leds failed with error -22
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Rename fsl-imx8qxp-mek.dts to fsl-imx8qxp-mek.dtsi.
remove /dts-v1/ from dtsi.
Add memreserve for dom0 dts.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 491045dead2f3294cb5ca78a6e667af00495ae48)
HDMI power domain is under DC0, however DC0 is used by the first OS,
so domu has no permission to use HDMI.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
alloc_contig_range easily return -EBUSY when try to isolate pages,
there are lots of messages with PFNs busy when run GPU tests.
[ 622.370671] alloc_contig_range: [4ea70, 4ea7c) PFNs busy
[ 626.518072] alloc_contig_range: [4ea90, 4ea9c) PFNs busy
these problems are related wht CMA migration for fragments,
need enlarge GPU reserved size to reduce CMA fragments.
Signed-off-by: Xianzhong <xianzhong.li@nxp.com>
The dts file was removed but makefile was not updated so build broke.
Fix by removing from makefile.
Fixes: a9c2aa010d ("MLK-20252 ARM64: dts: correct imx8mm root memory")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Add rtc pl031 and a dummy clock node.
The pl031 is emulated by XEN, the address and interrupt is fixed in XEN.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
Correct the memory for root linux.
Because rpmsg reserved memory, we could not support 2nd Linux now with
the new memory. So remove the support for 2nd linux.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Flynn xu <flynn.xu@nxp.com>
Currently, the adma_lcdif clocks are wrong. Correct these clocks.
Fix suggestion received from:
Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Acked-by: Leonard Crestez <leonard.crestez@nxp.com>
i2c2 and i2c3 are work at 100KHz, so no need to set the pad to fast
slew rate, slow slew rate is enough.
This patch can also fix the synaptics_dsx touch work unstable issue.
When config the i2c bus pad to fast slew rate, synaptics_dsx touch
sometimes can't be recognized through i2c bus. Seems this touch
i2c slave device sensitive to the pad slew rate setting.
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
For imx8mq-evk board, B4 board change touch/mipi-hdmi connected i2c bus
from i2c1 to i2c3. The default dual-display dts file is for the B4
board.
This patch adds a new dts file to also support dual-display on B3 (or
lower) boards.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Configure imx8qm/qxp pin as RTC 32KHz clock output as the
low power clock source for some WIFI chip.
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
i.MX7ULP SoC revision is available from B0, the SIM_JTAG_ID
register bit[31:28] indicates SoC revision as below:
4b'0001 B0
4b'0010 B1
This register is NOT available on A0, tested on B1 chip
as below:
root@imx7ulpevk:~# cat /sys/devices/soc0/revision
2.1
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Ye Li <ye.li@nxp.com>
Daniel Baluta