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719753 Commits (e2565903d48495f413a98a40b59c25937617a8eb)

Author SHA1 Message Date
Ranjani Vaidyanathan e2565903d4 MLK-18220-5 dts:imx8qxp Remove all clock references from GPIO device entries. 
Controlling GPIO clocks in iMX8 is dependent on power domain,
and an unused GPIO's power domain is disabled during startup.
This makes it difficult for the GPIO driver to manage clocks for such
GPIOs. This causes failures during system suspend/resume when
GPIO registers are saved/restored.
These LPCG clocks will be always be in an enabled state, similar
to earlier iMX processors.

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
 2018-10-29 11:10:38 +08:00
Huang Chaofan b960aa0f2f MLK-18250 VPU: Add MU for vpu encoder and decoder power in dts for 
scfw xrdc enforcing, and add sync for v4l2 driver and firmware

Add MU for vpu encoder and decoder power in dts for scfw xrdc enforcing,
and add sync for v4l2 driver and firmware

Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
 2018-10-29 11:10:38 +08:00
Shengjiu Wang a925039f1a MLK-18245-2: ARM64: dts: refine the power domain tree for audio devices 
In the latest scfw design, the power domain of device should be explicit
enabled in kernel, otherwise there will be kernel dump.
For example, when using audio device to playback, the DMA channel's power
domain should be eanbled, but to avoid to call scfw API in driver, we need
to refine the tree of power domain, define the DMA channel's power domain
as audio device's parent.

And same requirement for DSP, the MU and DSP_RAM is required by DSP driver.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
 2018-10-29 11:10:38 +08:00
Shengjiu Wang c5e2eaa4f3 MLK-18245-1: ASoC: fsl_dsp: remove the explicit power enablement 
The driver don't need to explicit enable the power domain, which
can be done by runtime power management, when the power domain tree
defined in device tree.
in this case, the MU initialization can be moved to runtime pm function.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
 2018-10-29 11:10:38 +08:00
Bai Ping 187f4b5550 MLK-18247 clk: imx: add more pll frequency setting in clock rate table 
Add 1GHz, 800MHz, 700MHz, 600MHz pll clock rate setting in the pll
clock calculation table of imx8mm. These frequency point are needed
by VPU and GPU driver.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
 2018-10-29 11:10:38 +08:00
Robin Gong 0b15802774 MLK-18241-3: ARM64: dts: freescale: imx8qm: add edma channel power domain for LPUART 
Add edma channel power domain for LPUART to make sure the specific
edma channel power up in dma mode.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
 2018-10-29 11:10:38 +08:00
Robin Gong e7646e6245 MLK-18241-2: ARM64: dts: freescale: imx8qxp: add edma channel power domain for LPUART 
Add edma channel power domain for LPUART to make sure the specific
edma channel power up in dma mode.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
 2018-10-29 11:10:38 +08:00
Robin Gong 544928ede7 MLK-18241-1 ARM64: dts: freescale: imx8qxp: correct edma index 
Correct edma index for imx8qxp to mach the right rsrc id of scfw.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
 2018-10-29 11:10:38 +08:00
Liu Ying 02c1772cc9 MLK-18229-4 gpu: imx: dpu: fetchwarp: Cosmetic changes on fw_ops entries 
This patch contains cosmetic changes on fw_ops entries to make the
entries be more readable.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
 2018-10-29 11:10:38 +08:00
Liu Ying e993ef613c MLK-18229-3 gpu: imx: dpu: fetchdlayer: Cosmetic changes on fl_ops entries 
This patch contains cosmetic changes on fl_ops entries to make the
entries be more readable.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
 2018-10-29 11:10:38 +08:00
Liu Ying a5d632fcbd MLK-18229-2 gpu: imx: dpu: fetcheco: Cosmetic changes on fe_ops entries 
This patch contains cosmetic changes on fe_ops entries to make the
entries be more readable.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
 2018-10-29 11:10:38 +08:00
Liu Ying 23212af787 MLK-18229-1 gpu: imx: dpu: fetchdecode: Cosmetic changes on fd_ops entries 
This patch contains cosmetic changes on fd_ops entries to make the
entries be more readable.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
 2018-10-29 11:10:38 +08:00
Liu Ying 655b045091 MLK-18207 gpu: imx: framegen: Remove redundant pll and display clk rate get 
We get pll and display clock rates twice in framegen_cfg_videomode().
This patch removes the redundant code so that the rates are got once.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
 2018-10-29 11:10:38 +08:00
Liu Ying bf53f39d24 MLK-18211 gpu: imx: layerblend: Zero sec alpha when sec input is from scaler 
It turns out that local alpha value of the secondary input is set to
0xFF by the hardware if the secondary input is from scaler(hscaler or
vscaler).  This makes the layer on this secondary input accidentally
cover the layer with higher z-order(if it exists), even though the
layer with lower z-order doesn't supply local alpha.  This patch zeros
the secondary local alpha value to prevent the issue from happening.
Users are unlikely to expect local alpha to be correctly scaled, so
it looks fine to simply zero the alpha.  If we find the unlikely case,
the KMS driver may later explicitly do atomic check to invalidate the case.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
 2018-10-29 11:10:38 +08:00
Han Xu cf5c13cd51 MLK-18240: arm64: dts: change the i.MX8QXPB0 NAND iomux settings 
Set the corrrect NAND IOMXU for i.MX8QXPB0.

Signed-off-by: Han Xu <han.xu@nxp.com>
 2018-10-29 11:10:38 +08:00
Richard Zhu 7026163ec3 MLK-18238 ARM64: dts: imx8qm: add pd for rpmsg to avoid crash 
Add pd for rpmsg to avoid crash, after enable
xrdc blocking.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
 2018-10-29 11:10:38 +08:00
Richard Zhu 107bd0f462 MLK-18210 ARM64: dts: imx8qm: correct the pds of pcie 
HSIO MSIC/GPIO are powered by the pd_hsio_gpio domain.
Use the pd_hsio_gpio as the parent pd of the imx8 hsio to
make sure that the pd_hsio_gpio domain would be tuend on
when enable HSIO module.
BTW, PHY calibration of the PHYX2_1/PHYX1 is relied on the
results of the PHYX2_0.
So, all the HSIO PDs should be turned on when use PCIe
or SATA.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
 2018-10-29 11:10:38 +08:00
Frank Li cca5f8a446 MLK-18237-3 XRDC: JPEG ENC/DEC fix crash missed power resource 
[    5.184399] Unhandled fault: synchronous external abort (0x96000210) at 0xffff00000b000000
[    5.184824] (null): mxc_isi_capture_open, No remote pad found!
[    5.187470] (null): mxc_isi_capture_open, No remote pad found!
[    5.192734] (null): mxc_isi_capture_open, No remote pad found!
[    5.199931] (null): mxc_isi_capture_open, No remote pad found!
[    5.219447] Internal error: : 96000210 [#1] PREEMPT SMP
[    5.224681] Modules linked in:
[    5.227755] CPU: 2 PID: 3028 Comm: v4l_id Not tainted 4.9.88-04903-ga209cd8 #464
[    5.235162] Hardware name: Freescale i.MX8QXP MEK (DT)
[    5.240305] task: ffff80083411cb00 task.stack: ffff80083b7ac000
[    5.246254] PC is at clk_gate2_scu_enable+0x3c/0xa8

Signed-off-by: Frank Li <Frank.Li@nxp.com>
 2018-10-29 11:10:38 +08:00
Frank Li 8d45acb783 MLK-18237-2 XRDC: DSP: add mu power resource to avoid crash 
[    2.300213] Unhandled fault: synchronous external abort (0x96000210) at 0xffff000014dd0000
[    2.308584] Internal error: : 96000210 [#1] PREEMPT SMP
[    2.313813] Modules linked in:
[    2.316875] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.88-04903-ga209cd8 #464
[    2.324271] Hardware name: Freescale i.MX8QXP MEK (DT)
[    2.329407] task: ffff80083a088000 task.stack: ffff80083a034000
[    2.335329] PC is at MU_Init+0x0/0x38
[    2.338994] LR is at dsp_mu_init+0xb8/0x140

Signed-off-by: Frank Li <Frank.Li@nxp.com>
 2018-10-29 11:10:38 +08:00
Frank Li 417653db44 MLK-18237 XRDC: rpmsg: add power domain to avoid crash 
[    0.737561] Unhandled fault: synchronous external abort (0x96000210) at 0xffff00000c160000
[    0.745503] Internal error: : 96000210 [#1] PREEMPT SMP
[    0.750695] Modules linked in:
[    0.753739] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.88-04903-ga209cd8 #464
[    0.761118] Hardware name: Freescale i.MX8QXP MEK (DT)
[    0.766246] task: ffff80083a088000 task.stack: ffff80083a034000
[    0.772160] PC is at MU_Init+0x0/0x38
[    0.775805] LR is at imx_rpmsg_probe+0x22c/0x510

Signed-off-by: Frank Li <Frank.Li@nxp.com>
 2018-10-29 11:10:38 +08:00
Oliver Brown 70c788660a MLK-17893 drm: imx: hdp: Adjust HDMI Vswing 
The HDMI voltage swing needs to be increased for HDMI compliance.

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
 2018-10-29 11:10:38 +08:00
Oliver Brown 7561eb76c6 MLK-18195 gpu: imx: dpu: framegen: Correct PLL rate to get proper pclk rate 
This patch corrects pixel clock PLL rate calculation.

Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
 2018-10-29 11:10:38 +08:00
Guoniu.Zhou 6ff717106c MLK-18222: CI_PI: fix CI_PI lost half of frame issue 
As IC team recommended, it is better to set vsync pulse
width as 2 lines pixels, otherwise ISI will lost half
of frames.

Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Sandor.Yu <sandor.yu@nxp.com>
 2018-10-29 11:10:38 +08:00
Anson Huang 9baa2463b8 MLK-18224-2 ARM64: dts: freescale: imx8qxp: update MU IRQ number 
MU IRQ number is incorrect, update it.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Anson Huang 9e89c774c3 MLK-18224-1 ARM64: dts: freescale: imx8qm: update MU IRQ number 
MU IRQ number is incorrect, update it.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Anson Huang 45d79b497f MLK-18205-16 ARM64: dts: freescale: imx8mm: add cpu-freq support 
Add i.MX8MM OPP table to support cpu-freq.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Anson Huang 320586f215 MLK-18205-15 soc: imx: enable cpu-freq for i.MX8MM 
Enable cpu-freq driver for i.MX8MM.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Anson Huang be1c43512c MLK-18205-14 cpufreq: imx8mq: add pmic voltage scaling support 
i.MX8MM shares same cpu-freq driver with i.MX8MQ, but
its EVK board has a PMIC which can scale VDD_ARM voltage
according to voltage defined in dtb, add support for it.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Robin Gong f5372c9073 MLK-18205-13 ARM64: dts: freescale: imx8mm-evk: add ROHM BD71837 PMIC support 
Add ROHM BD71837 PMIC support for i.MX8MM EVK board.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Anson Huang 24c89ba879 MLK-18205-12 ARM64: defconfig: enable i.MX8MM by default 
Enable i.MX8MM SoC by default.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Anson Huang db01fcd928 MLK-18205-11 arm64: Kconfig: add i.MX8MM support 
Add i.MX8MM SoC support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Robin Gong a0171f0aa3 MLK-18205-10 ARM64: defconfig: select BD71837 PMIC by default 
Enable BD71837 PMIC by default.

Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Haoran.Wang 61200c6925 MLK-18205-9 Support BD71837 PMIC chip on i.MX platforms 
Signed-off-by: Haoran.Wang <elven.wang@nxp.com>
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 37f67d291e74a3428310cb5c98f556411042f810)
 2018-10-29 11:10:38 +08:00
Bai Ping 2535028723 MLK-18205-8 ARM64: dts: freescale: imx8mm: add cpu-idle support 
Add i.MX8MM cpu-idle support, level #1 is wfi,
level #2 is ARM power gated.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Anson Huang 7c0406a164 MLK-18205-7 soc: imx: add i.MX8MM SoC driver support 
Add i.MX8MM SoC ID driver support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Anson Huang f029b6aa1c MLK-18205-6 soc: imx: add i.MX8MM support 
Add i.MX8MM SoC support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Peng Fan 4fa37208c0 MLK-18205-5 clk: imx: add i.MX8MM clock driver support 
Add i.MX8MM clock driver support.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Anson Huang fb586f52be MLK-18205-4 pinctrl: freescale: add i.MX8MM pinctrl driver support 
Add i.MX8MM pinctrl driver support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Bai Ping 1745eb3d27 MLK-18205-3 ARM64: dts: freescale: add i.MX8MM dtb 
Add i.MX8MM dtsi and evk dtb support.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Peng Fan cd46acb1aa MLK-18205-2 dt-bindings: clock: add i.MX8MM clock header 
Add i.MX8MM clock definition.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Bai Ping 5682754862 MLK-18205-1 dt-bindings: pinctrl: add i.MX8MM pins header 
Add i.MX8MM pins definition.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
 2018-10-29 11:10:38 +08:00
Haibo Chen 253206b9ab MLK-18218 ARM: dts: imx7ulp-evk: delete property to support SD3.0 
commit b62dd733a100 ("MLK-18127 ARM: dts: imx7ulp-evk: few correction
for usdhc1") add property "no-1-8-v" for the usdhc1 which limit the
wifi. The sd slot on base board share this usdhc1, so the usdhc1
in imx7ulp-evk-sd1.dts also inherit this property.

delete the "no-1-8-v" property, then the sd slot can support SD3.0

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
 2018-10-29 11:10:38 +08:00
Ranjani Vaidyanathan c7b110368d MLK-18220-3 XRDC: Fix the power domains for Audio clocks. 
Ensure the audio clocks are associated with the correct power domain.

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
 2018-10-29 11:10:38 +08:00
Ranjani Vaidyanathan 9ff9793b58 MLK-18220-2 XRDC:Fix power domain and clock entries in DTS 
Ensure that every resource is associated with a power domain
and clocks required.

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
 2018-10-29 11:10:38 +08:00
Ranjani Vaidyanathan c1843f2a93 MLK-18220-1 XRDC: Add GPIO clocks to device tree node. 
Add clocks required by GPIO to the device tree entries.

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
 2018-10-29 11:10:38 +08:00
Shenwei Wang 3c32045351 MLK-18219: arm: dts: add PMU node for 7ULP boards 
Added the PMU node in the imx7ulp.dtsi, and enable
it by default.

Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
 2018-10-29 11:10:38 +08:00
Nitin Garg d88291db4e MLK-18197: Use MU1 for wake up IRQ requests 
Use correct MU for SCFW API calls to comply with boot
container intended usage. Since ATF uses MU0 and kernel
uses MU1, update the MU id in api calls.

Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
 2018-10-29 11:10:38 +08:00
Anson Huang e06889b73b MLK-18208-2 clk: imx: imx8qxp: remove unused clocks 
Latest SCFW has requirement that whenever trying
access a resource, its power MUST be turned ON,
otherwise, XRDC will block such access and cause
kernel dump like below, this patch removes those
unused clocks to avoid such dump during kernel clock
framework trying to disable unused clocks, as these
clocks' power domains are NOT enabled because no device
use them now.

[    7.236611] Unhandled fault: synchronous external abort (0x96000210) at 0xffff000009fb0000
[    7.244875] Internal error: : 96000210 [#1] PREEMPT SMP
[    7.250102] Modules linked in:
[    7.253165] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 4.9.88-04869-ga28143b-dirty #129
[    7.261082] Hardware name: Freescale i.MX8QXP MEK (DT)
[    7.266218] task: ffff80083a088000 task.stack: ffff80083a034000
[    7.272144] PC is at clk_gate2_scu_is_enabled+0x30/0x74
[    7.277365] LR is at clk_gate2_scu_is_enabled+0x5c/0x74
[    7.282585] pc : [<ffff0000084f462c>] lr : [<ffff0000084f4658>] pstate: 800000c5
[    7.289977] sp : ffff80083a037d40
[    7.293287] x29: ffff80083a037d40 x28: ffff0000091e3508
[    7.298612] x27: ffff0000093ea000 x26: ffff00000918045c
[    7.303937] x25: ffff0000091e3560 x24: ffff0000093ea000
[    7.309263] x23: ffff0000091743d0 x22: ffff0000094152f8
[    7.314588] x21: ffff000009415000 x20: ffff80083a48c500
[    7.319914] x19: ffff80083a48d800 x18: ffff000008e102f8
[    7.325239] x17: 0000000000000000 x16: 0000000000000000
[    7.330564] x15: 0000000000000000 x14: 0000000000000000
[    7.335890] x13: 0000000000000007 x12: 00000000000001ee
[    7.341215] x11: 0000000000000006 x10: 00000000000001ef
[    7.346541] x9 : 0000000000000006 x8 : 2c6e69616d6f645f
[    7.351866] x7 : 0000000000000020 x6 : ffff000008cb1400
[    7.357192] x5 : 0000000000000008 x4 : 0000000000000000
[    7.362517] x3 : 0000000000000000 x2 : 0000000000000001
[    7.367843] x1 : ffff000009fb0000 x0 : 0000000000000000
[    7.373167]
[    7.374655] Process swapper/0 (pid: 1, stack limit = 0xffff80083a034020)
[    7.381354] Stack: (0xffff80083a037d40 to 0xffff80083a038000)
[    7.387099] 7d40: ffff80083a037d60 ffff0000084e1994 0000000000000040 ffff80083a45c300
[    7.394934] 7d60: ffff80083a037d80 ffff0000084e1930 ffff80083a48c500 ffff80083a45c200
[    7.402770] 7d80: ffff80083a037da0 ffff0000084e1a0c ffff80083a4003a8 ffff80083a45c200
[    7.410606] 7da0: ffff80083a037dd0 ffff000008084144 ffff80083a034000 ffff0000084e19c8
[    7.418442] 7dc0: 0000000000000000 ffff0000091e34d0 ffff80083a037e40 ffff000009180d00
[    7.426278] 7de0: ffff000009251028 0000000000000007 0000000000000198 ffff0000091e34d0
[    7.434115] 7e00: ffff80083a037e00 ffff000008fd0198 ffff80083a037e20 ffff000008fcf9e8
[    7.441950] 7e20: 0000000700000007 0000000000000000 0000000000000000 ffff0000091743d0
[    7.449787] 7e40: ffff80083a037ea0 ffff000008c4b554 ffff000008c4b544 0000000000000000
[    7.457622] 7e60: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.465459] 7e80: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.473295] 7ea0: 0000000000000000 ffff000008083820 ffff000008c4b544 0000000000000000
[    7.481131] 7ec0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.488967] 7ee0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.496803] 7f00: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.504639] 7f20: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.512475] 7f40: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.520311] 7f60: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.528148] 7f80: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.535984] 7fa0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.543820] 7fc0: 0000000000000000 0000000000000005 0000000000000000 0000000000000000
[    7.551656] 7fe0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.559489] Call trace:
[    7.561933] Exception stack(0xffff80083a037b70 to 0xffff80083a037ca0)
[    7.568370] 7b60:                                   ffff80083a48d800 0000ffffffffffff
[    7.576199] 7b80: ffff80083a037d40 ffff0000084f462c 0000000000000007 ffff000000000000
[    7.584034] 7ba0: ffff000009fb0000 0000000000000000 ffff0000093f41c8 00000000000000c0
[    7.591871] 7bc0: ffff80083a037cc0 ffff80083a037cc0 ffff80083a037c80 00000000ffffffc8
[    7.599707] 7be0: ffff80083a037c10 ffff00000816f824 ffff80083a037cc0 ffff80083a037cc0
[    7.607543] 7c00: ffff80083a037c80 00000000ffffffc8 0000000000000000 ffff000009fb0000
[    7.615379] 7c20: 0000000000000001 0000000000000000 0000000000000000 0000000000000008
[    7.623215] 7c40: ffff000008cb1400 0000000000000020 2c6e69616d6f645f 0000000000000006
[    7.631051] 7c60: 00000000000001ef 0000000000000006 00000000000001ee 0000000000000007
[    7.638887] 7c80: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.646725] [<ffff0000084f462c>] clk_gate2_scu_is_enabled+0x30/0x74
[    7.652998] [<ffff0000084e1994>] clk_disable_unused_subtree+0x8c/0xc0
[    7.659442] [<ffff0000084e1930>] clk_disable_unused_subtree+0x28/0xc0
[    7.665888] [<ffff0000084e1a0c>] clk_disable_unused+0x44/0x130
[    7.671728] [<ffff000008084144>] do_one_initcall+0x38/0x128
[    7.677307] [<ffff000009180d00>] kernel_init_freeable+0x1ac/0x248
[    7.683403] [<ffff000008c4b554>] kernel_init+0x10/0xf8
[    7.688545] [<ffff000008083820>] ret_from_fork+0x10/0x30
[    7.693854] Code: b9418420 35000200 f9400e61 b40001c1 (b9400021)
[    7.699969] ---[ end trace 510c6d25aa9fc50a ]---
[    7.704600] note: swapper/0[1] exited with preempt_count 1
[    7.710119] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
[    7.710119]
[    7.719253] SMP: stopping secondary CPUs
[    7.723175] Kernel Offset: disabled
[    7.726662] Memory Limit: none
[    7.729715] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
[    7.729715]

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
 2018-10-29 11:10:38 +08:00
Anson Huang 4874b797d7 MLK-18208-1 clk: imx: imx8qm: remove unused clocks 
Latest SCFW has requirement that whenever trying
access a resource, its power MUST be turned ON,
otherwise, XRDC will block such access and cause
kernel dump like below, this patch removes those
unused clocks to avoid such dump during kernel clock
framework trying to disable unused clocks, as these
clocks' power domains are NOT enabled because no device
use them now.

[    7.300474] Unhandled fault: synchronous external abort (0x96000210) at 0xffff00000ab40000
[    7.308736] Internal error: : 96000210 [#1] PREEMPT SMP
[    7.313955] Modules linked in:
[    7.317018] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 4.9.88-04869-ga28143b-dirty #127
[    7.324936] Hardware name: Freescale i.MX8QM MEK (DT)
[    7.329984] task: ffff8008f60a8000 task.stack: ffff8008f6034000
[    7.335910] PC is at clk_gate2_scu_is_enabled+0x30/0x74
[    7.341131] LR is at clk_gate2_scu_is_enabled+0x5c/0x74
[    7.346352] pc : [<ffff0000084f4664>] lr : [<ffff0000084f4690>] pstate: 800001c5
[    7.353743] sp : ffff8008f6037d40
[    7.357053] x29: ffff8008f6037d40 x28: ffff0000091e3508
[    7.362379] x27: ffff0000093ea000 x26: ffff00000918045c
[    7.367704] x25: ffff0000091e3560 x24: ffff0000093ea000
[    7.373030] x23: ffff0000091743f0 x22: ffff0000094152f8
[    7.378355] x21: ffff000009415000 x20: ffff8008f6575d00
[    7.383680] x19: ffff8008f65b9900 x18: ffff000008e102f8
[    7.389006] x17: 0000000000000000 x16: 0000000000000000
[    7.394331] x15: 0000000000000000 x14: 0000000000000000
[    7.399657] x13: 0000000000000007 x12: 00000000000002ce
[    7.404982] x11: 0000000000000006 x10: 00000000000002cf
[    7.410307] x9 : 0000000000000006 x8 : 2c6e69616d6f645f
[    7.415633] x7 : 0000000000000020 x6 : ffff000008cb1400
[    7.420958] x5 : 0000000000000008 x4 : 0000000000000000
[    7.426284] x3 : 0000000000000000 x2 : 0000000000000001
[    7.431609] x1 : ffff00000ab40000 x0 : 0000000000000000
[    7.436935]
[    7.438421] Process swapper/0 (pid: 1, stack limit = 0xffff8008f6034020)
[    7.445120] Stack: (0xffff8008f6037d40 to 0xffff8008f6038000)
[    7.450864] 7d40: ffff8008f6037d60 ffff0000084e1994 0000000000000140 ffff8008f663be00
[    7.458691] 7d60: ffff8008f6037d80 ffff0000084e1930 ffff8008f6575d00 ffff8008f663bd00
[    7.466518] 7d80: ffff8008f6037da0 ffff0000084e1a0c ffff8008f66455a8 ffff8008f663bd00
[    7.474346] 7da0: ffff8008f6037dd0 ffff000008084144 ffff8008f6034000 ffff0000084e19c8
[    7.482173] 7dc0: 0000000000000000 ffff0000091e34d0 ffff8008f6037e40 ffff000009180d00
[    7.490000] 7de0: ffff000009251028 0000000000000007 0000000000000198 ffff0000091e34d0
[    7.497828] 7e00: ffff8008f6037e00 ffff000008fd0198 ffff8008f6037e20 ffff000008fcf9e8
[    7.505655] 7e20: 0000000700000007 0000000000000000 0000000000000000 ffff0000091743f0
[    7.513483] 7e40: ffff8008f6037ea0 ffff000008c4b62c ffff000008c4b61c 0000000000000000
[    7.521310] 7e60: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.529137] 7e80: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.536965] 7ea0: 0000000000000000 ffff000008083820 ffff000008c4b61c 0000000000000000
[    7.544792] 7ec0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.552619] 7ee0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.560447] 7f00: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.568274] 7f20: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.576102] 7f40: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.583929] 7f60: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.591757] 7f80: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.599584] 7fa0: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.607411] 7fc0: 0000000000000000 0000000000000005 0000000000000000 0000000000000000
[    7.615239] 7fe0: 0000000000000000 0000000000000000 ffffffffffffffff 7fff7f7fffffffff
[    7.623065] Call trace:
[    7.625508] Exception stack(0xffff8008f6037b70 to 0xffff8008f6037ca0)
[    7.631945] 7b60:                                   ffff8008f65b9900 0000ffffffffffff
[    7.639773] 7b80: ffff8008f6037d40 ffff0000084f4664 0000000000000007 ffff000000000000
[    7.647600] 7ba0: ffff00000ab40000 0000000000000000 ffff0000093f41c8 00000000000001c0
[    7.655428] 7bc0: ffff8008f6037cc0 ffff8008f6037cc0 ffff8008f6037c80 00000000ffffffc8
[    7.663255] 7be0: ffff8008f6037c10 ffff00000816f824 ffff8008f6037cc0 ffff8008f6037cc0
[    7.671083] 7c00: ffff8008f6037c80 00000000ffffffc8 0000000000000000 ffff00000ab40000
[    7.678910] 7c20: 0000000000000001 0000000000000000 0000000000000000 0000000000000008
[    7.686737] 7c40: ffff000008cb1400 0000000000000020 2c6e69616d6f645f 0000000000000006
[    7.694565] 7c60: 00000000000002cf 0000000000000006 00000000000002ce 0000000000000007
[    7.702392] 7c80: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
[    7.710221] [<ffff0000084f4664>] clk_gate2_scu_is_enabled+0x30/0x74
[    7.716486] [<ffff0000084e1994>] clk_disable_unused_subtree+0x8c/0xc0
[    7.722930] [<ffff0000084e1930>] clk_disable_unused_subtree+0x28/0xc0
[    7.729367] [<ffff0000084e1a0c>] clk_disable_unused+0x44/0x130
[    7.735199] [<ffff000008084144>] do_one_initcall+0x38/0x128
[    7.740778] [<ffff000009180d00>] kernel_init_freeable+0x1ac/0x248
[    7.746875] [<ffff000008c4b62c>] kernel_init+0x10/0xf8
[    7.752015] [<ffff000008083820>] ret_from_fork+0x10/0x30
[    7.757325] Code: b9418420 35000200 f9400e61 b40001c1 (b9400021)
[    7.763429] ---[ end trace bfe5d53d2c12087e ]---
[    7.768052] note: swapper/0[1] exited with preempt_count 1
[    7.773559] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
[    7.773559]
[    7.782689] SMP: stopping secondary CPUs
[    7.786616] Kernel Offset: disabled
[    7.790099] Memory Limit: none
[    7.793151] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
 2018-10-29 11:10:38 +08:00
Richard Zhu e0b9ee0d23 MLK-18180 ARM64: dts: correct the pad configurations of pcie 
The correct default should be 0x04000021. In which we have the open
drain input option for field [25:26] with a pull up resistor and low
drive strength. This will allow the end point device to drive low the
wake and clkreq signals when necessary and don't have the PCIe
driving back to the endpoint device.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
 2018-10-29 11:10:38 +08:00