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38 Commits (spacecruft)

Author SHA1 Message Date
Agis Zisimatos 250e636a27 Fix PN in TRX 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-07-29 16:19:24 +03:00
Agis Zisimatos bc2c925c7a Fixes in net names, PN, new hierirchical labels 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-07-19 14:52:07 +03:00
Agis Zisimatos cb77450ceb Add RC to delay the enable of 2V5 LDO 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-07-15 14:09:57 +03:00
Agis Zisimatos 871bc8ed23 Replace load switches 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-07-15 13:37:50 +03:00
Agis Zisimatos efe1cafcf9 Update BOM and delete wrong part description 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-05-02 14:22:23 +03:00
Agis Zisimatos d2c2e2270d Exclude test points form BOM 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-30 20:24:41 +03:00
Agis Zisimatos 276cab3b18 Fix connections in RN601 that helps in routing 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-30 14:21:21 +03:00
Agis Zisimatos a8ec6c893f Add in series termination in FPGA SPI 
Add as option because SPI runs out of board.

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-30 13:18:47 +03:00
Agis Zisimatos b07c5fff98 Fix clock-in pins 
Add them in clock compatible pins for PLL.

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-30 11:28:11 +03:00
Agis Zisimatos 9d9a499b54 Add hierarchical label FPGA_3V3 to use it in JTAG 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-26 13:55:56 +03:00
Agis Zisimatos 5b0f13295b Add missing capacitor to VCCIO bank-3 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-26 13:46:57 +03:00
Agis Zisimatos 05aedba620 Change SPI CLK pin to L18 from M20 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-26 13:31:17 +03:00
Agis Zisimatos 9b03d488d5 Add debug LED of FPGA 
Fixes #42

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-19 19:47:58 +03:00
Agis Zisimatos 651edca938 Split RN in NOR flash to single R's 
Helping in FPGA routing

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-19 14:58:39 +03:00
Agis Zisimatos c8a1410dfc Swap pins in RN of JTAG 
Helps in PCB routing

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-18 15:34:41 +03:00
Agis Zisimatos b143aba082 Add Bank-3 of FPGA for SPI 
Helps more in routing

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-18 15:14:00 +03:00
Agis Zisimatos 892b8d7188 Fix ERC errors of high level schematic 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-11 13:27:38 +03:00
Agis Zisimatos 6dba8e700b Replace single resistors with resistor network 2022-04-11 09:58:56 +00:00
Agis Zisimatos 0ea9754b22 Fix FPGA symbol anotation and footprint 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-08 18:07:34 +03:00
Agis Zisimatos 62e9a7579b Add SERDES bank and connect supply voltaged to GND 
* Add a fpga-power sheet
* Add auto updated kicad files

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-08 11:28:44 +03:00
Agis Zisimatos 21e81aed53 Fix connection of INITN and DONE 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-06 19:16:15 +03:00
Agis Zisimatos 625d39c64e Add missing pull-up resistor 
Reference: https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/EH/FPGA-TN-02038-1-6-ECP5-and-ECP5-5G-Hardware-Checklist.ashx?document_id=50482

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 19:54:51 +03:00
Agis Zisimatos 94313541b0 Clean up the FPGA schematic from comments 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 19:54:51 +03:00
Agis Zisimatos bdd3c06adf Add decoupling capacitors in FPGA schematic 
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/22

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 19:54:51 +03:00
Agis Zisimatos be0d0789f9 Add FPGA_INIT to MCU, fixes #13 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 11:27:50 +03:00
Agis Zisimatos c3122ab59c Add oscillator in FPGA 
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/10

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 11:06:18 +03:00
Agis Zisimatos fb9e050bc9 Add test points for GPIOs 
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/12

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 11:06:18 +03:00
Agis Zisimatos 8b5c631826 Add MSPI as default boot mode and NOR flash 
Fixes # https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/9

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 11:06:18 +03:00
Agis Zisimatos 0e86bb6f49 Add LED indicators for DONE and INITN 
Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/8

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 11:06:18 +03:00
Agis Zisimatos 84e1cc8608 Implement FPGA JTAG 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 11:01:35 +03:00
Agis Zisimatos e749327cc2 Place I/Q and SPI of FPGA 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-04-05 11:01:35 +03:00
Agis Zisimatos fef6cc6ec3 Add pull-down resistor in load switch ON pin 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-03-29 19:48:29 +03:00
Agis Zisimatos 95c29a28e7 Add current limit resistor value 
Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-03-29 19:05:22 +03:00
Agis Zisimatos 74dad42969 Fixes in FPGA power schematic 
- Add ferrite bead part number
- Fixes ERC error in PG of 1.1V pin
- Fixes https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/16

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-03-29 18:20:43 +03:00
Ilias Daradimos 055c01d8fa Move GND power flag to top sheet 
Update symbols

Signed-off-by: Ilias Daradimos <ilias@libre.space>
 2022-03-22 13:23:56 +02:00
Ilias Daradimos b8ad60e557 Reanotate sheets 
Update symbol and port direction

Signed-off-by: Ilias Daradimos <ilias@libre.space>
 2022-03-22 12:29:50 +02:00
Agis Zisimatos 9d3e6155ef Add PSU for FPGA 
Releted to https://gitlab.com/librespacefoundation/sidloc/sidloc-transceiver/-/issues/15

Signed-off-by: Agis Zisimatos <agzisim@gmail.com>
 2022-03-22 11:19:58 +02:00
Papadeas Pierros 046229765a Add interfaces between modules (closes #1) 
Signed-off-by: Papadeas Pierros <pierros@papadeas.gr>
 2022-03-16 20:03:26 +02:00