Specify SAI1/5 pll8k and pll11k clks in order to enable dynamic
reparenting of SAI master clock to the appropriate pll as function of
audio stream rate.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Specify SAI1/5 pll8k and pll11k clks in order to enable dynamic
reparenting of SAI master clock to the appropriate pll as function of
audio stream rate.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
This makes it possible to enable earlycon for debugging by just passing
an empty "earlycon" argument on the kernel command-line.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Ye Li <ye.li@nxp.com>
The property is called "stdout-path" not "stdout-patch"
Fixes: 3af3a86574d1 ("MLK-18645 arm64: dts: imx8mm: Add DTS for iMX8MM DDR4 validation board")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
The property is called "stdout-path" not "stdout-patch"
Fixes: c5454672bc06 ("MLK-18205-3 ARM64: dts: freescale: add i.MX8MM dtb")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
The imx_sc_thermal driver has strict thermal zone and sensor
id relationship with device tree settings, simple removing
DRC thermal zone node will introduce incorrect sensor id
settings for other thermal zones, so adding status for driver
to ignore those thermal zones with status equal "disabled".
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Leonard Crestez <leonard.crestez@nxp.com>
Replace the M4_MU# by the LSIO MU in the RPMSG usage.
Otherwise, M4 can't enter into LPM if the M4_MU# is
used in RPMSG.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Commit (dfe39e3 MLK-18673 ARM64: dts: freescale:
imx8dx: disable DRC thermal zone) removes DRC thermal
zone but did NOT fix the thermal zone number and
index, it causes thermal driver probe fail, this
patch corrects them.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Add root and inmate dts. The core [0-1] for root, core[2-3] for inmate.
Disabled gpc busfreq. Not support low power features for dual Linux case.
The 2nd Linux use SDHC1 and UART2, let 1st Linux configure pin and clock
for the two devices. The memory used by 2nd Linux are reserved in
the 1st Linux dts.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit fd8736bdb1df332e98547a9f5b99126fcdd15e31)
There is a interrupt-parent property in root node, no need
to set it again in subnode.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 899f4e6b4c0f2e372079db979a0a802cd6167bcd)
DTRC interrupts will not be used for switching the banks, as the CTXLD
will be used for that, however these are useful for tracing and
debugging green screen issues when DTRC is used.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Fix incorrect reg address for ESCPI2/ECSPI3
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(cherry picked from commit cf15610449eb581adb8c2f7f1bb420191b4ee617)
Enable pwm4 control on status led on imx8mm evk base board
use hartbeat trigger to blink led
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 65b2de72509084a577e37b2758061612a3c7d639)
Enable gpio led status on imx8mm evk cpu board
set ON as default state
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit e63553bbab70c06454272e37867c15a807759702)
Add device nodes for pwm support on imx8mm SoC
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 25b240c986083e83d827795255f554f3f896f9c2)
Add property "cap-power-off-card" to fix the module loadable issue.
Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Add Cypress wifi bcm4339 support with fmac driver for below platforms:
- imx6q/dl/qp-sabresd
- imx6sl/sll-evk
- imx6sx-sdb
Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Enabling DRC thermal zone could impact DDR PLL clock quality
under certain conditions, disable it for now.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
and modify interlaced
- Reserve 24M memory for vpu decoder stream buffers in dts, and 8M
for each instance
- Modify interlaced by using ctx->pSeqinfo->uProgressive to judge
interlaced or progressive
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
Add the DTS file for iMX8MM DDR4 validation board to support basic
modules like: I2C, UART, ENET, SD/eMMC, Flexspi and USB
Signed-off-by: Ye Li <ye.li@nxp.com>
The sw2iso count should cover ARM LDO ramp-up time,
the MAX ARM LDO ramp-up time may be up to more than
100us, this patch sets sw2iso to 0xf (~384us) which
is the default value.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
To support lowest power mode for suspend, if no wakeup source
from non-secure partition is enabled, IRQSTEER can be powered
off when suspend, so non-secure linux OS needs to pass WU
irqchip wakeup source info to ATF, as MU is always enabled
as wakeup source, and it is a system level resource, so no
need to have it in WU domain.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Update dom node with name and reg, the two property
will be parsed by xen to create the mapping between
domain name and partition id.
With the mapping, xen could power off the resources
owned by the partition when destroy/reboot/shutdown
the domain.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Without using xen tools to create nodes, we need write the nodes in
dts to let kernel boots up correctly.
Even no using bootloader to boot VM, the nodes added will not
be passthrough to VM, and xen tool will create them automatically.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Add ADC support for imx8qxp b0 validation board, just enable ADC_IN0
and ADC_IN1, to support these two adc external analog input, need do
the following hardware rework: change register R335 and R338 from A
side to B side.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
When ldb works in dual LVDS channel mode, it consumes two MIPI/LVDS combo
subsystems, one primary and the other auxiliary. Each subsystem is powered
by it's own power domain. So, the dual channel mode needs two power domains.
The pd_mipi_dsi_0/1_dual_lvds power domains may supply two power domains to
the ldb1/2 nodes respectively. Thus, let's hook them to the ldb1/2 nodes
when ldb1/2 works in dual channel mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 12dd916ad6bd4f10bf41e27e4392787b4a3af0e5)
When ldb works in dual LVDS channel mode, it consumes two MIPI/LVDS combo
subsystems, one primary and the other auxiliary. Each subsystem is powered
by it's own power domain. So, the dual channel mode needs two power domains.
This patch adds pd_mipi_dsi_0/1_dual_lvds power domains support so that
the ldb1/2 nodes may use them to support dual channel mode. Note that
the pd_mipi_dsi_0/1_aux_lvds are the parent power domains of the
pd_mipi_dsi_0/1_dual_lvds power domains respectively.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 86c85ca8cf5b81d4e97e54955ea46e50fdb76b9f)
The power domain devicetree binding documentation tells us that only
one phandle should be supplied to the power-domains property and if
multiple power domains are needed, then the power domains should be
chained as one parent power domain and multiple subsidiary power domains.
Thus, let's remove the unused power domain from the ldb nodes which
are originally expected to powerup the auxiliary MIPI/LVDS combo
subsystems.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit ebbd5aef7005c3128de215715448ac883ebc22e1)
The JDI TX26D202VM0BWA WUXGA LVDS panel works in LVDS
dual channel mode. It can connect with the i.MX8qxp
MEK board via J1(for LVDS0) and J3(for LVDS1) jacks.
Either LVDS0 or LVDS1 can be the primary channel.
The panel uses PWM signal supplied by i.MX8qxp to
control the backlight. This patch adds the panel
support on the i.MX8qxp MEK platform.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit b0b8542cdde19586c0311907a388d22fed4688b4)
This patch adds LVDS0/1 PWM backlight support on the i.MX8qxp MEK platform.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 48ebf3f5154862cfd21026a7830f08106791905a)
This patch adds pwm_mipi_lvds0/1 nodes support for i.MX8dx/dxp/qxp.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 9e326d6997fb5fb7144775a14ec707e91d2cb6b3)
The video tearing appeared only when the application used 2 buffers.
That's because, sometimes, the context loader could be armed after the
DB event came in the frame trace. That made a buffer submitted in frame
N end up on screen in frame N+2 because the context loader waits for the
next DB event. Since vblank events are sent at the end of the frame, by
the time the buffer lands on screen, the application will reuse it while
it's being displayed, hence the tearing effect.
This patch moves the CTXLD trigger moment all the way to the end of the
frame trace, just before DB event arrives. This will leave the
application plenty of time to submit new buffers.
In the event that the trigger moment is missed (application submits a
buffer right at the end of a frame trace), then we're not signalling the
next VBLANK event to application. This way, application will know that
the buffer is still needed and will not submit a new one.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This was removed by upstream commit 5eaeaccdae
("ARM: dts: imx7d-sdb: Pass 'enable-gpios' and 'power-supply' properties")
That commit claims that GPIO1_IO01 is not a PWM because it's connected
to a pin labelled "PWREN" of J14 connector. However that pin does behave
as a pwm despite the name.
The exact same pattern happens with imx6ul-evk which has an LCD8000-43T
display on J901.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Upstream modified imx7s.dtsi pwm to have #pwm-cells = <3> so now our
out-of-tree boards need to be modified to use 3 cells.
See commit 9be48d2d98 ("ARM: dts: imx7: use 3 PWM cells")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Review-by: Liu Ying <victor.liu@nxp.com>
Two different regulators are defined with the same name and label but
distinct properties.
The first definition was added with the first board dts and the second
was added when upstream added flexcan support.
Looking at schematics it is indeed gpio2 14 connected to the STB pin of
the CAN transceiver so remove the first definition. This also makes it
consisent with imx_4.9.y.
The second definition entirely overrides the first so this already
worked and this patch results in no DTB change, just a cleanup.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
In upstream the flexcan2 regulator was added with its own pinctrl group
and the EPDC_DATA14 pin is claimed even if the can controller is marked
as disabled.
Mark the regulator itself with status = "disabled" so it won't claim the
pin.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Robert Chiras <robert.chiras@nxp.com>
This reverts commit e10bb39556.
The mxsfb driver uses old bindings so we need to provide those
Acked-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
This reverts commit d8236af530.
The mxsfb driver uses old bindings so we need to provide those.
The LCD timings were already upstreamed but then an upstream commit
removed them in favor of adding a DRM path. Making mxsfb work requires
reverting this upstream commit
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Robert Chiras <robert.chiras@nxp.com>
Somehow missed when rebaseing to 4.14
Signed-off-by: Marius Vlad <marius-cristian.vlad@nxp.com>
Acked-by: Prabhu Sundararaj <prabhu.sundararaj@nxp.com>
The MIPI-DSI and LVDS PHY power domains are managed by their bridge
drivers, there is no need to have power domains for the phys also.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
enable gpu device in imx8mq-evk board,
increase GPU memory size from 32M to 128M,
enable GPU flat mappping for full DDR range.
add IMX8MQ_CLK_GPU_AHB_DIV into gpu clock list.
Signed-of-by: Chenyan Feng <ella.feng@nxp.com>
This was skipped during the rebase but now that GPU is enabled we can
also enable it on 8mq.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Update ov5640 camera nodes in fsl-imx8mq-evk.dts
to match for B4 revision, the two cameras are on separate i2c buses.
Create fsl-imx8mq-evk-b3.dts to be used with old B3 revision,
here include the B4 dtb, but override the ov5640 camera nodes,
to use different i2c addresses on the same i2c bus.
Rev B4 tested with HDMI 1920x1080 and fsl-imx8mq-evk.dtb.
Rev B3 tested with HDMI 1920x1080 and fsl-imx8mq-evk-b3.dtb.
Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
Reviewed-by: Robert Chiras <robert.chiras@nxp.com>, Robby Cai <robby.cai@nxp.com>
Setting a72 clock to 1300mhz and reading back the value from clk reveals
the rate is actually 1296mhz:
root@imx8mmevk:~# cpufreq-set -c 4 -f 1300000
root@imx8mmevk:~# cat /sys/kernel/debug/clk/clk_summary |grep a72
a72_div 0 0 1296000000 0 0
This causes some cpufreq tests to fail. Fix by setting OPP to 1296000.
Fixes: 2b6d66acdd71 ("MLK-18331 ARM64: dts: freescale: imx8qm: update cpufreq set points")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Anson Huang <anson.huang@nxp.com>
This patch introduces two DT source files to add IT6263 dual
channel mode support. Either LVDS0 acts as the primary channel
or LVDS1 does.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
i.MX8dx/dxp/qxp use two LDBs(one primary, one auxiliary) to support
dual channel mode. This patch adds DT properties in the LDB nodes
so that HWs needed by dual channel mode can be supplied.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
There's probability there's no interrupt from CSI for the resolution
of 2592x1944 at 15 fps due to timing problem.
Need refine hs_settle value to fix this.
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Add nodes for clock disp_axi and disp_apb for access to avoid hang issue.
On i.MX8MM, use the register in CSI to do MIPI PHY reset, so add these
clocks for MIPI CSI driver as well.
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Change the micfil clock rate to 196MHz. With lower
clock rate, performance is poor when recording more
than two channels.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
The display pipeline provided by IMX8MM soc is: LCDIF --> MIPI DSI.
This patch re-organize the LCDIF and MIPI DSI device nodes to be
suitable for DRM/KMS drivers. Besides, a new device node 'dispmix_gpr'
which is required by LCDIF and MIPI DSI is added.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
PCIe ep rc validation system is one remote processors
communications.
Add the reserved region in pcie node, and use this region as
ddr test region in pcie ep rc validation system.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Add dtsi and board configurations for DXP/DX 8QXP derivatives.
Separate out the arm2 board individual details for transparency
of board and device specifics.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Add dtsi and ARM2 board configurations for QP/DM 8QM derivatives.
Separate out ARM2 specific details from device details.
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Since IP version 3.01 (845s) SAI has support for 1:1 bclk:mclk ratio.
Given this the specific DSD512 pinctrl option can be removed and SAI mclk
frequency decreased.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
600000000 (-22)" and "clk: couldn't set vpu_enc_clk clk rate to
600000000 (-22), current rate: 0" when boot up. 100%
vpu clock is not settable, remove the assigned-clock-rates from the dts
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
When adding a new config option one should always run:
$ make savedefconfig
Reported-by: Jana Build <jana.build@nxp.com>
Tested-by: Raluca Oncioiu <raluca.oncioiu@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Support ASRC P2P with ESAI to show the multichannel capibility.
And make this setting align with other platform like imx6
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
In imx6qdl-sabresd.dtsi imx_4.9.y defines ov564x_mipi@3c with
compatible="ovti,ov564x_mipi". Upstream added camera@3c with
compatible="ovti,ov5640" on the same bus and this results in i2c errors
on boot:
i2c i2c-1: Failed to register i2c client ov564x_mipi at 0x3c (-16)
i2c i2c-1: of_i2c: Failure registering /soc/aips-bus@02100000/i2c@021a4000/ov564x_mipi@3c
i2c i2c-1: Failed to create I2C device for /soc/aips-bus@02100000/i2c@021a4000/ov564x_mipi@3c
Fix by removing upstream definition.
The other camera camera added by upstream, &ov5642: camera@3c on &i2c0
was already removed/overwritten with our definition during porting.
Fixes: 2b48156760e5 ("MLK-11508-5: dts: Add imx v4l2 capture driver")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Suspend fails on sabreauto because the i2c mux is set to the default
state before suspending sensors:
dpm_run_callback(): isl29023_suspend+0x0/0x3c returns -11
PM: Device 2-0044 failed to suspend: error -11
PM: Some devices failed to suspend, or early wake event detected
Fix this by moving sensons to i2cmux/i2c@1 just like the rest of I2C3
devices. This is a porting issue, in imx_4.9.y there is no dynamic
muxing for i2c3.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Upstream added new separate pinctrl groups:
* pinctrl_i2c3mux for MX6QDL_PAD_EIM_A24__GPIO5_IO04
* pinctrl_max7310 for MX6QDL_PAD_SD2_DAT0__GPIO1_IO15
During imx_4.9.y porting these were both added to pinctrl_hog instead
and this now causes a pin conflict. Drop this part and keep them in
per-device pin groups.
Fixes: 2b48156760e5 ("MLK-11508-5: dts: Add imx v4l2 capture driver")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Upstream added i2c-mux-gpio to imx6qdl-sabreauto and CONFIG_I2C_MUX_GPIO
to imx_v6_v7_defconfig. We need to copy this to imx_v7_defconfig or
several devices won't probe.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Before the kernel starts, optee uses M4 SRAM to allocate its
suspend function. When imx7ulp_pm_map_io() executes, the psci
driver and psci_ops.cpu_suspend are not initialized yet. This
causes the memset to always wipe the optee suspend code in the
M4 SRAM.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
The dpu driver may properly handle display clock parent selection now.
Thus, let's remove the assigned-clock and assigned-clock-parent
device tree properties from the dpu device tree node.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The dpu driver may properly handle display clock parent selection now.
Thus, let's remove the assigned-clocks and assigned-clock-parents
device tree properties from the dpu device tree nodes.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
After the WAIT mode is enabled on imx8mm, the previous latency setting
seems can NOT meet the system the latency requirement. audio playback is
impacted by cpuidle. So increasing the latency setting as large as possible
to eliminate the impact of system performance. The latency value is not very
accurate, need to be updated after we have enough performance test result.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Optimize the pciea disable pin to drive NTB0104 device:
(NTB0104 requires at least 2 mA per data sheet)
- push-pull output
- pull disabled
- high drive strength
And the patch also change the lvds gpio to lsio gpio.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
pcie aux clock is mandatory required by pcie power management.
add the aux clock into imx8mm pcie dts node explicitly.
pcie ctrl clock would be turned on, when pcie root clock
is enabled.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
i.MX8MQ uses same GPT as i.MX7D, add i.MX7D compatible
string for GPT driver, and disable it by default.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Change the hdmi dig_pll clock rate to 675MHz,
hdmi core clock is source from dig_pll.
And HDMI CEC required core clock should integer MHz(675/5=135MHz).
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Add the pcie support for imx8mm and verify
it on imx8mm evk board when internal pll is
used as ref clock.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
The vendor tree does imx7 PGC management through regulator notifiers
while upstream implemented the same features using power domains. These
two drivers have entirely different interfaces with higher-level IP
blocks.
Resolve this conflict by moving the old code to drivers/soc and
supporting both power-domain and regulator interfaces. This effectively
merges the two drivers and is similar to how imx6sx implements both
power domains and a regulator notifier for pcie specifically.
Supporting both interfaces allows consumes to switch one-by-one, for
example by having PCI work with a power-domains reference while usb hsic
still uses the regulator enable/disable interface.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
The power domain code shares the same node and will not probe if irqchip
probes first and marks the node with OF_POPULATED.
Clearing the OF_POPULATED flag is also done in imx_gpc_init for imx6 and
imx_gpcv2_irqchip_init implemented by upstream.
In imx_4.9.y this was solved in a different way by adding a second pgc
node, see commit fab513930e78 ("MLK-14280: gpc: gpc driver not probed").
Solving the problem by clearing OF_POPULATED allows using the upstream
PGC driver without hacks.
Having two irqchip implementations with same name seems to work fine
with the mach-imx variant taking precedence.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Add micfil DAI node in dtsi and pdm sound card in dts.
We also moved ak5558 nodes into separate dts since
ak5558 uses sai5 which share some pins with micfil.
Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>
(cherry picked from commit 8451c6886b0175b7e1391293aa9fb461395f8485)
Enable AK4497 with mode 0. For ak4497 the same SAI interface as
for AK4458 is used, so a separate ak4497 dts is needed.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Added no_clk_reset property for 8M dts files, since DSI doesn't need
it's clocks stopped during suspend.
Also, added power on delay for 8QM and 8QXP for a better suspend/resume
stability.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
In order to enlarge the CMA easily, change the rpmsg
reserved memory region from 0xb800_0000 to 0x9000_0000.
And refine the layout of the reserved memory.
- RPMSG buffers are allocated from CMA dynamically, and have to
be accessed by M4 side. But M4 can only access the 1.5Gbytes
DDR memory from 0x8000_0000. So, the finial reserved memory
layout is just like the one below.
Thus, the largest size of the DDR memory left for CMA, is about
1212Mbytes in theory, since 32Mbytes alignment is required by
CMA allocation.
reserved-memory layout
0x8800_0000 ~ 0x8FFF_FFFF M4 + RTOS(128M)
0x9000_0000 ~ 0x903F_FFFF RPMSG Vring(4M)
0x9440_0000 ~ 0xDFFF_FFFF(MAX) CMA(1212M)(MAX)
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Regarding to the latest layout of the reserved memory
on imx8qxp, correct the rpmsg address on arm2 board too.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
When wifi driver switch to QCA CLD from ATH10K, there have one known issue:
- QCA CLD driver only support ONE instance.
So it has to disable pcie0 port.
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Since uart1 and uart3 has cts/rts lines connection, add cts/rts
support for uart1 and uart3
Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
On i.mx7ULP, poweroff kernel by sending rpmsg message to M4, and
M4 poweroff CA7. Then M4 can power on CA7 again by type 'V' command
in its console or press POWERON key once M4 support POWERON.
Note: CA7 should enter VLLS mode firstly before poweroff by M4.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Enable usbotg1 and disable usbotg2, both are USB 2.0 and dual role
capable, but the typec port for usbotg2 is primary for power, and
the dead battery is not ready, so disable the typec2 and usbotg2.
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
This fixes a pinctrl error in the guest, fixing these warnings:
imx8qm-pinctrl passthrough:iomuxc: pin_config_set op failed for pin 60
imx-lpi2c 157247000.i2c: Error applying setting, reverse things back
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Remove CSI0/1 GPIO related clocks to make sure all GPIOs
clocks are always ON.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
The reserved memory for dsp is defined in dts file, however, the dsp
driver has also defined the address and size of this reserved memory,
which is repeated and inflexible.
So by cancelling the definition in dsp driver and use system API to
get the information of reserved memory from dts dynamically to fix
this problem.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
In order to enlarge the CMA easily, change the rpmsg
reserved memory region from 0xb800_0000 to 0x9000_0000.
And refine the layout of the reserved memory.
- RPMSG buffers are allocated from CMA dynamically, and have to
be accessed by M4 side. But M4 can only access the 1.5Gbytes
DDR memory from 0x8000_0000. So, the finial reserved memory
layout is just like the one below.
Thus, the largest size of the DDR memory left for CMA, is about
1212Mbytes in theory, since 32Mbytes alignment is required by
CMA allocation.
reserved-memory layout
0x8000_0000 ~ 0x83FF_FFFF A core + Linux Kernel(64M)
0x8400_0000 ~ 0x85FF_FFFF VPU encoder boot(32M)
0x8600_0000 ~ 0x87FF_FFFF VPU decoder boot(32M)
0x8800_0000 ~ 0x8FFF_FFFF M4 + RTOS(128M)
0x9000_0000 ~ 0x903F_FFFF RPMSG Vring(4M)
0x9040_0000 ~ 0x913F_FFFF VPU decoder rpc(16M)
0x9140_0000 ~ 0x923F_FFFF VPU encoder rpc(16M)
0x9240_0000 ~ 0x943F_FFFF DSP(32M)
0x9440_0000 ~ 0xDFFF_FFFF(MAX) CMA(1212M)(MAX)
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Add some necessary configs for qualcomm wifi QCA6174/QCA9377 qcacld-2.0
CLD driver and remove the ath10k configs.
(Run "make savedefconfig" to change the defconfig)
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Add all uart ports on evk board, and enable uart1 port for
Murata 1PJ bluetooth support.
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
In the latest scfw design, the power domain of device should be explicit
enabled in kernel, otherwise there will be kernel dump.
For example, when using audio device to playback, the DMA channel's power
domain should be eanbled, but to avoid to call scfw API in driver, we need
to refine the tree of power domain, define the DMA channel's power domain
as audio device's parent.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
This was always wrong but causes failures recently after dom0 switched
to using mu1 and claiming it's interrupt
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Correct JPEG power domain tree to make sure kernel can
boot up successfully with XRDC enforcement enabled.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com>
Correct USB power domain tree to make sure kernel can
boot up successfully with XRDC enforcement enabled.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com>
All GPIOs clock will be kept ON in SCFW by default, here
remove all GPIOs management to make sure they are always
ON.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Peng Fan <peng.fan@nxp.com>
Controlling GPIO clocks in iMX8 is dependent on power domain,
and an unused GPIO's power domain is disabled during startup.
This makes it difficult for the GPIO driver to manage clocks for such
GPIOs. This causes failures during system suspend/resume when
GPIO registers are saved/restored.
These LPCG clocks will be always be in an enabled state, similar
to earlier iMX processors.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
scfw xrdc enforcing, and add sync for v4l2 driver and firmware
Add MU for vpu encoder and decoder power in dts for scfw xrdc enforcing,
and add sync for v4l2 driver and firmware
Signed-off-by: Huang Chaofan <chaofan.huang@nxp.com>
In the latest scfw design, the power domain of device should be explicit
enabled in kernel, otherwise there will be kernel dump.
For example, when using audio device to playback, the DMA channel's power
domain should be eanbled, but to avoid to call scfw API in driver, we need
to refine the tree of power domain, define the DMA channel's power domain
as audio device's parent.
And same requirement for DSP, the MU and DSP_RAM is required by DSP driver.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
HSIO MSIC/GPIO are powered by the pd_hsio_gpio domain.
Use the pd_hsio_gpio as the parent pd of the imx8 hsio to
make sure that the pd_hsio_gpio domain would be tuend on
when enable HSIO module.
BTW, PHY calibration of the PHYX2_1/PHYX1 is relied on the
results of the PHYX2_0.
So, all the HSIO PDs should be turned on when use PCIe
or SATA.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Add ROHM BD71837 PMIC support for i.MX8MM EVK board.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Enable BD71837 PMIC by default.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Add i.MX8MM cpu-idle support, level #1 is wfi,
level #2 is ARM power gated.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
commit b62dd733a100 ("MLK-18127 ARM: dts: imx7ulp-evk: few correction
for usdhc1") add property "no-1-8-v" for the usdhc1 which limit the
wifi. The sd slot on base board share this usdhc1, so the usdhc1
in imx7ulp-evk-sd1.dts also inherit this property.
delete the "no-1-8-v" property, then the sd slot can support SD3.0
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Added the PMU node in the imx7ulp.dtsi, and enable
it by default.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
The correct default should be 0x04000021. In which we have the open
drain input option for field [25:26] with a pull up resistor and low
drive strength. This will allow the end point device to drive low the
wake and clkreq signals when necessary and don't have the PCIe
driving back to the endpoint device.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
The MIPI DSI config the DPI as 480 * 854, so correct the touch
display-coords property, to aligned with MIPI DSI.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
In order to avoid the name problem going forward with
integration with Qcom, Qcom has their own dsp and hifi
is competitor, so the hifi name should not be used in
our code.
So use the name of dsp instead of hifi to fix this
problem.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
pd_dc1 is a power domain node, marking it as xen,passthrough
meaning disabled. Alought when enabing xen passthrough
the second DC to DomU, we no need this power domain,
but Dom0 linux will disable unused clks and trigger
error message, "populate_gate_pd: failed to get pd".
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Leonard Crestez <leonard.crestez@nxp.com>
1. Divide ov5640_v3.c into two parts, one for parallel csi driver
and the other for mipi csi driver
2. Add parallel and mipi support in one dtb file. User can select
one of them without changing the dtb file
Reviewed-by: Sandor.yu <sandor.yu@nxp.com>
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
fix audio bus mode hang issue on imx6sl. The root cause of
this issue is that busfreq mode passed to TEE side is wrong,
it will lead to ccm setting is wrong in TEE.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Anson huang <anson.huang@nxp.com>
On QXP B0 board, prg1 can alternative connect to
dpr_channel1 and channel2. And if enable PRG0_SEL:BLIT0,
prg1 will connect to channel2, so it could
support 2-plane format tile to linear convert.
Signed-off-by: yuchou gan <yuchou.gan@nxp.com>
7ULP uses the same mmdc profiling block as i.mx6q. Added the
"fsl,imx6q-mmdc" compatible string to enable the mmdc profiling
feature.
Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Passthrough EDMA0 Channel 14/15 and lpuart1 to DomU.
Delete the original edma0 node and introduce the other 5 nodes
to which contains two channels each node.
Currently the nodes are included in fsl-imx8qm-xen.dtsi.
The modem-reset node to support bluetooth is not introduced in DomU
dts, because gpio support has not been done.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This fixes graphics on imx6sx by aligning closer to upstream instead of
adding new features to old bindings.
Upstream adds a 4th power domain for PCI but this is is wrong: the PCI
block is in the DISPMIX domain and only PCIE_PHY is in the PCIE_PHY
power domain.
Manual is not very clear on this but in section 10.4.1.4.1 there is this
statement: "The DISPLAY domain contains GIS, CSI, PXP, LCDIF, PCIe,
DCIC, and LDB. It is supplied by internal regulator."
Placing pcie in a 4th power domain makes lspci hang when display is
turned off.
In upstream the dispmix domain is not actually touched on 6sx so it's
always on, this is why pci seems to work.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
Upstream suspend/resume already works on this board because it includes
imx6ul-14x14-evk which has these properties set. In our internal branch
the imx6ul and imx6ull DT files are distinct so this needs to be fixed
separately.
Equivalent to commit e6f4292ae0 ("ARM: dts: imx6ul-14x14-evk: Add
ksz8081 phy properties")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Remove the ldb clocks from the ldb node. Those clocks were added
upstream and they are needed for the DRM imx-ldb driver. Since we are
using the fbdev ldb driver for imx6qp, those clocks are not compatible
with our fbdev driver.
Fixes: 78241a88958a ("ARM: dts: add dts file for imx6qp")
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Support using PSCI to handle Power stuff on imx7d.
i.MX7 LPSR mode not implemented now.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
A specific node for OCRAM mapping in optee as been added in
the device tree. These dedicated optee device trees can be
removed.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
This node will be used by the OCRAM driver in optee to:
* Get the OCRAM start address for power management in optee.
* Add an entry that will overwrite ocrams nodes and dynamically reduce
the OCRAM available for mmio-sram in Linux.
That way we do not touch the legacy Linux boot and remove the dedicated
optee device tree.
Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This change affects all i.MX 6 with PL310 L2 Cache controller.
When Linux runs in Non-secure World the PL310 has already
been initialized by the ARM secure World running OP-TEE os.
However, in order to have a proper Linux Initialization all the
L2 cache ways have been locked by the secure world.
This patch unlock all the ways during pl310 initialization.
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Low power idle exit latency is much longer than declared, in the
milisecond range.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
The current code for deciding which CPU runs the complete lpi flow is
too complicated. Since all enter/exit code now runs under the same lock
we can just use a single non-atomic counter of cpus inside lpi.
Another variable is used to make num_online_cpus() available to ASM code
but idle code can treat it as a constant.
Unlike on imx_4.9.y num_online_cpus is fetched every time idle is
entered becuase hotplug notifiers are gone.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
The GPC will wake us on peripheral interrupts but not IPIs. So check
them manually by reading the GIC's GICD_SPENDSGIR* registers and
aborting idle if something is pending.
We do this only for the last cpu and after taking the required locks.
We know that at this stage the other cpu is in WFI itself or waiting for
the imx_pen_lock and can't trigger any additional IPIs. This means that
the check is not racy.
This fixes occasional lost IPIs causing tasks to get stuck in the
TASK_WAKING 'W' state for long periods. This eventually manifested as
rcu stalls.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
This makes the code much easier to reason about. In particular it o
makes sure the imx7d cpuidle driver respects the requirements for
cpu_cluster_pm_enter/exit:
* cpu_cluster_pm_enter must be called after cpu_pm_enter has been called
on all cpus in the power domain, and before cpu_pm_exit has been called
on any cpu in the power domain.
* cpu_cluster_pm_exit must be called after cpu_pm_enter has been called
on all cpus in the power domain, and before cpu_pm_exit has been called
on any cpu in the power domain.
This fixes interrupts sometimes getting "stuck" because of improper
save/restore of GIC DIST registers.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
GPC will stop ARM clock if both CPUs are in idle and CPU_CLK_ON_LPM is
set in GPC_LPCR_A7_BSC. Make sure that doesn't happen when cpu1 enters
state2 and cpu0 enters state0 because the default arm WFI state is not
marked with CPUIDLE_FLAG_TIMER_STOP and it can result in arch_sys_timer
being stopped unexpectedly.
It is possible to reproduce incorrect behavior by explicitly disabling
other idle states for cpu0/cpu1 and timing how much sleep calls take on
cpu0. Ocassionaly something like "sleep 1" will take 3-4 seconds to
complete.
Make sure that both CPUs are in the same idle state before entering
WAIT.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
For standby mode, RBC workaround is NOT necessary as ARM platform
is NOT powered down;
Correct GIC register offset(0x1000) for disabling distributor.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Enable memory power down for i.MX7D TO1.1 to save power, TO1.0
has issue of entering DSM by mistake, so it is disabled as a
solution, now that this issue is fixed on TO1.1, enable it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Same as low power idle, during GPC shutting down ARM core,
interrupts must be hold until the process done, apply RBC
workaround and disable GIC during GPC powering down ARM
core.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
i.MX7D TO1.1 only supports DDR3 running at max frequency of 400MHz,
update busfreq driver accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Enable DDR auto self-refresh for i.MX7D, when doing DDR
frequency scale or suspend/resume, DDR self-refresh will
be disabled, this is incorrect for saving power, enable it
for all these scenarios.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
For low power idle with ARM power gated, per hardware requirement,
there must be no interrupt coming during the power down
process of ARM core, so RBC counter is enabled to hold interrupts
and GIC must be disabled at the moment;
The hardware design team recommends ~240us is required during ARM
core power down, so we update the RBC counter value to 8(~240us);
Update GPC SCU and CPU power up/down timing according to design
team's recommendation.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Design team recommend to put SCU/C0/C1 in same power up slot
to avoid reset timing issue of debug mode, adjust the power
up slot and timing per their requirement.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
When only single core online for i.MX7D, the secondary core wfi
flag should be set to make sure low power idle can be entered when
last core enters wfi. Otherwise, DDR/CCM/ANATOP will NOT enter
low power mode as the secondary core wfi flag is always clear;
Make sure the last power up slot do the ack for single core case.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Since upstream removed cpu hotplug notifiers skip this part.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Viorel Suman