In order to avoid the name problem going forward with
integration with Qcom, Qcom has their own dsp and hifi
is competitor, so the hifi name should not be used in
our code.
So use the name of dsp instead of hifi to fix this
problem.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
i.MX8QXP B0 silicon config enet IO voltage as 2.5V setting in default,
but MEK and ARM2 board only support 1.8V IO. So change the IO voltage
as 1.8V setting.
Set the MAC RGMII timing as TX no delay and RX delay mode as the default
setting for MEK and ARM2 board.
Since i.MX8QXP B0 silicon ENET IO timing change, to reach better timing
and avoid CRC error, MEK base board and ARM2 cpu board should remove the
driver device for the secord enet port.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Add missing sosc_bus_clk/firc_bus_clk/spll_bus_clk clocks which will be used
by other devices later.
All these clocks use the same divider as ddr_div, so ulp_div_table is used.
Besides that, all these clocks need to be controlled by M4, so
CLK_DIVIDER_READ_ONLY is also specified.
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
'CKIL' clock name is derived from MX6 SoC series which is invalid for
MX7ULP (can't find it from RM). Changing it to the correct 'ROSC'
which is defined in RM.
The exist 'OSC' name is also changed accordingly which should be SOSC
(System OSC).
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
The CCGR RAWNAND is shared by apbh-dma and gpmi clocks, so must use
imx_clk_gate2_shared2 to produce two clocks. Otherwise, apbh-dma clock
won't be enabled individually.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Add uSDHC clock MUX to allow uSDHC driver to select
parent, currently only support PLL0 and PLL1 as
uSDHC clock's parent.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Haibo Chen <haibo.chen@nxp.com>
Add CLKO2 for i.MX8MQ
Set parent for MIPI CSI1/2 CORE/PHY_REF/ESC
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
The Video PLL2 has a output enable bit to do clk gate,
So we need to register this gate to save power.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Add missing clocks for MIPI-DSI SS: RX_ESC and TX_ESC
Also added the posibility to select clock parents for MIPI-DSI versus
LVDS.
The SCFW was changed, so now the LVDS pixel and phy clocks need to
specify their parrents.
Also, the TX_ESC and RX_ESC clocks from MIPI-DSI need to specify their
parrents in DTS files.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
On i.MX8MQ, the dram core clock can be sourced from dram_pll or
the dram_alt clock, when sourced from the dram_alt, it has a fix
divider(1/4). When the DDRC core clock is lower than 800MHz, we
can swith the core clock to dram_alt source.
The dram apb clock's mux option 2 should be sys1_pll_40m, so fixed it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
DC clocks can choose their clock source between PLL1, PLL2 and
bypass input.
This patch introduces a multiplexer in the dc clock topology to
allow this choice and introduces one set of parents that will be used
for both display0 and display1 clocks.
Clock paths tested:
1. PLL2(dc0_pll1_clk)->DC0_DISP1(dc0_disp1_clk)->LVDS
2. BYP(dc0_bypass0_clk)->DC0_DISP1(dc0_disp1_clk)->LVDS
(BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0)
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Reviewed by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
Add focaltech new touch panel ft5246 support.
Set the ft5426 as default panel for dts. If want to use the old panel, then
it needs to boot with imx7ulp-evk-ft5416.dtb file.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit:963fea909ef5e42294cb2e656e5e3870a2171c01)
Define three root clocks for DCSS module:
.IMX8MQ_CLK_DISP_AXI_ROOT
.IMX8MQ_CLK_DISP_APB_ROOT
.IMX8MQ_CLK_DISP_RTRM_ROOT
These root clocks share one clock gate along with
'IMX8MQ_CLK_DISP_ROOT' clock. So change its type
to be shared gate clock too.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
IMX7d does not contain an M0 Core and this particular
clock doesn't seem connected to anything else.
Remove this entry from the CCM driver.
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Add wdog nodes in dtsi.
Enable wdog1 for imx8mq evk board.
Enable imx wdt in defconfig.
Correct clock, offset 0x4550 is actually for wdog3.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
imx8mq iomux header file uart part select_input config are
wrong that cause most of uart pin not work.
Add DCE and DTE string to distinguish the pin is for uart
which function, and clear all select_input for output pin.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
add audio ipg clock, sai ipg clock and correct some wrong
place in clock tree.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Add mipi csi local interrupter clock
Rename image subsystem power domain name.
Rename mipi csi LIS clock name.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
During 4.14 rebase squashed MLK-15124-01 and MLK-15124-02 because they
do not build separately.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
- use one standalone hsio node to share the region to
pciea, pcieb and sata.
- axi master slave and dbi clks and pipe_clk are required
- enable pcieb
change the pd of the pcieb, otherwise, clk is failed to enable
- add the cpu addr offset
Bit[31:24]
pciea 60 - 6f ---> 40 - 4f
pcieb 70 - 7f ---> 80 - 8f
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
Ensure that both PLL and IPG clocks are enabled and set by
the HDMI irqsteer device tree entry.
Fix some HDMI clock names.
The HDMI irqsteer incorrectly assumed that the HDMI bus clock will
be enabled automatically by the SCFW when HDMI SS is powered up.
Fix HDMI clocks so that the HDMI IPG clock is enabled when required.
Also fix all the LPCG addresses by HDMI clocks.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
