* origin/spi/qspi:
spi: spi-fsl-qspi: Introduce variable to fix different invalid master Id
dt-bindings: spi: spi-fsl-qspi: Add bindings of ls1088a and ls1012a
spi: spi-fsl-qspi: dynamically alloc AHB memory for QSPI
* origin/pcie/mobiveil: (14 commits)
misc: pci_endpoint_test: Add the layerscape PCIe GEN4 EP device support
PCI: mobiveil: Add workaround for unsupported request error
PCI: mobiveil: Add PCIe Gen4 EP driver for NXP Layerscape SoCs
dt-bindings: Add DT binding for PCIE GEN4 EP of the layerscape
PCI: mobiveil: Add the EP driver support
...
* origin/pcie/dwc: (22 commits)
LF-128 PCI: imx: turn off the clocks and regulators when link is down
PCI: imx: add the imx pcie ep verification solution
MLK-22995: pci: controller: dwc: pci-imx6: fix regulator warning complains on i.mx6sx-sdb
PCI: dwc: fix the msi failure after pm operations
Revert "MLK-11484-3 PCI: designware: Refine setup_rc and add msi data restore"
...
* origin/dts/qoriq: (105 commits)
arm64: dts: fsl: ls1028a: Disable eno3 and make swp5 the Felix CPU port
arm64: dts: fsl: ls1028a: Specify that the Felix port 4 runs at 2.5Gbps
arm64: dts: fsl: Drop "compatible" string from Felix switch
arm64: dts: fsl: Specify phy-mode for CPU ports
arm64: dts: ls1028a: Add DP DT nodes
...
* origin/display/nwl-dsi: (14 commits)
drm/bridge: nwl-dsi Correct the DSI init sequence
drm/bridge: nwl-dsi: Fix find_panel_or_bridge
drm/bridge: nwl-dsi: Add support for 8QM and 8QXP
drm/bridge: nwl-dsi: Add support for component framework
phy: imx8-mipi-dphy: Add support for 8QM and 8QXP
...
* origin/display/mxsfb: (14 commits)
drm/mxsfb: Add support for live pixel format change
drm/mxsfb: Add support for horizontal stride
drm/mxsfb: Clear OUTSTANDING_REQS bits
drm/mxsfb: Improve the axi clock usage
drm/mxsfb: Update mxsfb to support LCD reset
...
* origin/capture/pi:
LF-101: staging: media: imx: fix XR24 format R and B are opposite issue
staging: media: imx: add video ops for imx8 parallel subdev
staging: media: imx: add parallel capture interface driver for imx8qxp
media: dt-bindings: add bindings for i.MX8QXP parallel interface
imx busfreq: Add API header file
* origin/capture/media-dev:
media: staging: imx: add media device driver support for IMX8
media: dt-bindings: add bindings for i.MX8QXP/QM virtual media device
* origin/capture/jpeg: (9 commits)
MLK-22835: mxc-jpeg: jpeg decoder stuck due to race condition
mxc-jpeg: Fix warning at build, for EXPORT_SYMBOL on static variable
media: mxc-jpeg: jpeg: Replace stracpy with strscpy
mxc-jpeg: Build mxc-jpeg as module, by default
mxc-jpeg: Add support for multi power domain
...
* origin/audio/fm: (8 commits)
MLK-11429-21: ASoC: fsl: port si476x machine driver from imx_3.10.y
MLK-11305 radio-si476x: support set V4L2_CID_AUDIO_MUTE CTRL
MLK-22355: mfd: si476x: Use system_freezable_wq instead of system_wq
MLK-10055-2: mfd: si476x-i2c: sound is registered when no FM module attached
MLK-10038-1: mfd: si476x-i2c: Add support of si476x-rev4.0 board
...
commit 7165ef890a upstream.
The introduction of 768ec4c012 ("ath10k: update HOST capability QMI
message") served the purpose of supporting the new and extended HOST
capability QMI message.
But while the new message adds a slew of optional members it changes the
data type of the "daemon_support" member, which means that older
versions of the firmware will fail to decode the incoming request
message.
There is no way to detect this breakage from Linux and there's no way to
recover from sending the wrong message (i.e. we can't just try one
format and then fallback to the other), so a quirk is introduced in
DeviceTree to indicate to the driver that the firmware requires the 8bit
version of this message.
Cc: stable@vger.kernel.org
Fixes: 768ec4c012 ("ath10k: update HOST capability qmi message")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Add new pmic pca9450 driver for i.mx8mn-evk board.
Signed-off-by: John Lee <john.lee@nxp.com>
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit 2189979539bb9817d3d8bf0f5489f906d86e673f)
Some Layerscape paltforms (such as LS1088A, LS2088A, etc) require update HW
default cache type configuration to fix DWC3 init failure when applying
property dma-coherent.
Note that the cache type configuration is actually native feature of DWC3,
not additional desgin coming from SoC, so add this support here.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
This is a rework of the following i.MX BSP commit
(rel_imx_4.19.35_1.1.0_rc2):
9b63038a58cc ("MLK-21453: crypto: caam - fix Mentor's port, merge conflict resolutions")
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Acked-by: Leonard Crestez <leonard.crestez@nxp.com>
LS1028A has a clock domain PXLCLK0 used for provide pixel clocks to Display
output interface. Add a YAML schema for this.
Signed-off-by: Wen He <wen.he_1@nxp.com>
Signed-off-by: Michael Walle <michael@walle.cc>
By default, QorIQ SoC's RCPM register block is Big Endian. But
there are some exceptions, such as LS1088A and LS2088A, are
Little Endian. So add this optional property to help identify
them.
Actually LS2021A and other Layerscapes won't totally follow Chassis
2.1, so separate them from powerpc SoC.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Add the documentation for the Device Tree binding of the layerscape
PCIe GEN4 controller with EP mode.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer/pme interrupts with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.
Signed-off-by: Po Liu <po.liu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Add the PCIe compatible string for LS1028A
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
When chip support the aer/pme interrupts with none MSI/MSI-X/INTx mode,
maybe there is interrupt line for aer pme etc. Search the interrupt
number in the fdt file. Then fixup the dev->irq with it.
Signed-off-by: Po Liu <po.liu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Add the support for a CT36X based touchscreens using
the CT36X controller and i2c touchscreen interface.
Signed-off-by: Alejandro Lozano <alejandro.lozano@nxp.com>
Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
Signed-off-by: Alejandro Sierra <alejandro.sierra@nxp.com>
(Vipul: Fixed merge conflicts)
TODO: checkpatch warnings
Signed-off-by: Vipul Kumar <vipul_kumar@mentor.com>
Add DT bindings documentation for the upcoming S32V234 clk driver. Add
s32v234-clock.h header, which is referred in MC_CGM documentation.
Signed-off-by: Stoica Cosmin-Stefan <cosmin.stoica@nxp.com>
Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
The mipi pll clock comes from the MIPI PHY PLL output, so
it should not be a fixed clock.
MIPI PHY PLL is in the MIPI DSI space, and it is used as
the bit clock for transfering the pixel data out and its
output clock is configured according to the display mode.
So it should be used only for MIPI DSI and not be exported
out for other usages.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
MX8QM and MX8QXP LPCG Clocks are mostly the same except they may reside
in different subsystems across CPUs and also vary a bit on the availability.
Same as SCU clock, we want to move the clock definition into device tree
which can fully decouple the dependency of Clock ID definition from device
tree and make us be able to write a fully generic lpcg clock driver.
And we can also use the existence of clock nodes in device tree to address
the device and clock availability differences across different SoCs.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
There's a few limitations on the original one cell clock binding
(#clock-cells = <1>) that we have to define some SW clock IDs for device
tree to reference. This may cause troubles if we want to use common
clock IDs for multi platforms support when the clock of those platforms
are mostly the same.
e.g. Current clock IDs name are defined with SS prefix.
However the device may reside in different SS across CPUs, that means the
SS prefix may not valid anymore for a new SoC. Furthermore, the device
availability of those clocks may also vary a bit.
For such situation, we want to eliminate the using of SW Clock IDs and
change to use a more close to HW one instead.
For SCU clocks usage, only two params required: Resource id + Clock Type.
Both parameters are platform independent. So we could use two cells binding
to pass those parameters,
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
The clocking information is missing from flexcan device tree bindings.
This information is needed to be able to use flexcan. Document the same.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Add compatible for LX2160A SoC,QDS and RDB board
Add lx2160a compatible for clockgen and dcfg
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
This is a rework of the following i.MX BSP commit
(rel_imx_4.19.35_1.1.0_rc2):
0adf02011a49 ("MLK-18082: defconfig: Add caam to 7ulp conf")
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
This is a rework of the following i.MX BSP commit
(rel_imx_4.19.35_1.1.0_rc2):
3ac6edcd92d4 ("MLK-11360-01 crypto: caam_snvs: add snvs clock management")
caam_snvs driver involves snvs HP registers access that needs to
enable snvs clock source. The patch add the clock management.
Signed-off-by: Andy Duan <fugang.duan@nxp.com>
Signed-off-by: Dan Douglass <dan.douglass@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Add power domains for each dma channel so that edma channel could
know the power state of every dma channel anytime and clear easily
unexpected interrupt which triggered before the last partition reset.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: S.j. Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 0b6da46b7bdb2284e24757d48466268b9feb5b7c)
Since the imx8qm/qxp hsio only supports up to 32bit
dma capability.
Add the 32bit dma limitation into dma binding document.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Since there are multi edmav3 instances on i.mx8, every edma channel name
is better unique.But so far, all edma channel name is 'edma-channel(id)-
tx',thus some edma channels which share the same channel id but different
edma instance will show the same channel name in kernel and this is not
friendly to debug in kernel.
Now the edma channel name(interrupt-names property) is define in dts
as below:
"edmaX-chanX-Xx"
| | |---> receive/transmit, r or t
| |---> channel id, the max number is 32
|---> edma controller instance, 0, 1, 2,..etc
and get below correct name with 'cat /proc/interrupts':
43: 0 0 0 0 GICv3 466 Level edma0-chan8-rx
44: 0 0 0 0 GICv3 467 Level edma0-chan9-tx
45: 79 0 0 0 GICv3 468 Level edma0-chan10-rx
46: 311 0 0 0 GICv3 469 Level edma0-chan11-tx
47: 0 0 0 0 GICv3 470 Level edma0-chan12-rx
48: 0 0 0 0 GICv3 471 Level edma0-chan13-tx
49: 0 0 0 0 GICv3 472 Level edma0-chan14-rx
50: 0 0 0 0 GICv3 473 Level edma0-chan15-tx
51: 0 0 0 0 GICv3 406 Level edma2-chan0-tx
52: 0 0 0 0 GICv3 407 Level edma2-chan1-tx
53: 0 0 0 0 GICv3 408 Level edma2-chan2-tx
54: 0 0 0 0 GICv3 409 Level edma2-chan3-tx
55: 0 0 0 0 GICv3 410 Level edma2-chan4-tx
56: 0 0 0 0 GICv3 411 Level edma2-chan5-tx
57: 0 0 0 0 GICv3 442 Level edma2-chan6-rx, edma2-chan7-tx
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit af8e197a92c9c024ec4fbfcf543d744e81748773)
There is Audio dual fifo cause that fill fifo one by one and
loop back after every minor loop:
-- fill the first 32bit width fifo
-- fill the next 32bit width fifo
-- +MLOFF signed offset after the above two FIFOs filled
-- loop back to the first step to handle the next minor loop.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
(cherry picked from commit 5aa5e9663bb3a834444b75ea086bef8c37ecb636)
For dual fifo case, fsl-edma-v3 need add another cell. It's not friendly
for user and it's possible other cells maybe added to other use cases,
so combine two cells into one now, and for some special use cases such as
dual fifo property can directly be passed by one bit of cell3 rather than
another cell.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
(cherry picked from commit 3ecd1b3382e2c746728842fb2c084fbb030eb5de)
update fsl_edma_v3 document for #dma-cell is changed
one more cell is added, which is for local/remote access.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 65543fb7fefbdb7df4cb60931a88f61507c5073f)
update sdma script for multi fifo SAI on i.mx8MQ. Besides,Add
new cell for sw_done/sw_done_selector, because PDM need enable
software done feature in sdma script(same multi fifo script).
The new fourth cell defined as below:
Bit31: sw_done
Bit15~bit0: selector
For example: 0x80000000 means sw_done enabled for done0 sector which
is for PDM on i.mx8mm.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Add optional property node 'arm,malidp-arqos-value' for the Mali DP500.
This property describe the ARQoS levels of DP500's QoS signaling.
Signed-off-by: Wen He <wen.he_1@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
The DTRC module triggers an interrupt when each bank finished processing. So,
they are needed if video compressed formats are to be played.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The JDI TX26D202VM0BWA LCD panel is a 10.1" panel
with a 1920x1200 (WUXGA) resolution.
The panel has dual LVDS channels.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The DSI-HDMI converter, ADV7535, driver uses four i2c memory maps: MAIN,
DSI-CEC, EDID and PACKET.
While the MAIN address is hard-coded in the ROM chip, the other three
can be programmed into the MAIN memory map.
Currently, the three memory maps addresses, that can be programmed, are
hard-coded into the code.
In order to avoid conflicts with other i2c clients on the bus, update
the driver to use configurable addresses specified in DTS file.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Add a new property "adi,dsi-channel" to allow the user specify the DSI
channel to be used when communicating with DSI peripheral.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Added "adi,adv7535" to the adv7511 drm bridge and adi,adv7511.txt doc,
since the driver can also support the ADV7535 chipset (upgrade of ADV7533).
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Add a new property 'pref-rate' support which can be used to
assign a different clock frequency for the DPHY PLL reference
clock in the dtb file. And if this property does not exist,
the default clock frequency for the reference clock will be
used. And according to the spec, the DPHY PLL reference clk
frequency should be in [6MHz, 300MHz] range.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
ITE Tech. Inc. (abbreviated as ITE) is a fabless IC design house from Taiwan.
Website: www.ite.com.tw
Signed-off-by: Liu Ying <victor.liu@nxp.com>
[ Aisheng: change to YAML format ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Add new optional property 'max-memory-bandwidth', to limit the maximum
bandwidth used by the MXSFB_DRM driver.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Tested-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Rob Herring <robh@kernel.org>
i.MX8qxp LDB dual channel mode uses two LDB channels from two LDB
instances, while all other LDB variants in other SoCs use two LDB
channels from one LDB instance. This patch adds documentation
for the special case of i.MX8qxp LDB dual channel mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Not only i.MX8qm LDB requires pixel and bypass clocks, but also
i.MX8qxp LDB does. This patch corrects pixel and bypass clock
description by explicitly saying that i.MX8qxp LDB requires
the clocks.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds device tree binding support for i.MXqxp LDB,
including compatible string and additional properties.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds device tree binding support for i.MXqm LDB,
including compatible string and additional properties.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Pixel combiner found in i.MX8 SoCs may combine two display
streams(one master and the other slave) to drive a high
pixel rate display. This patch adds DT property descriptions
in imx-drm device tree documentation for pixel combiner.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The Display Prefetch Resolve(DPR) is a processor of fetching display data
before the display pipeline which needs data to drive pixels in the active
display region. The data is transformed, or resolved from a variety of
tiled buffer formats into linear format. The DPR transaction sequences are
issued with a high level of DRAM efficiency. This patch adds device tree
binding doc support for i.MX8qm/qxp DPR.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The Pretch Resolve Gasket(PRG) is a digital core function as a gasket
interface between RTRAM controller and DPU. The main function of PRG
is to convert the AXI interface to RTRAM interface and remapping the
ARADDR to a RTRAM address. This patch adds device tree binding doc
support for i.MX8qm/qxp PRG.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds device tree binding for the Display Processing Unit(DPU),
as found in i.MX8qxp SoC.
The DPU is comprised of two main components that include a blit engine
for 2D graphics accelertations and a display controller for display
output processing, as well as a command sequencer.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
There is already one quirk for usb3 xhci flag XHCI_MISSING_CAS, for
those platform with OF we can use usb3-resume-missing-cas to enable
this quirk to work around usb3 resume from system sleep.
Signed-off-by: Li Jun <jun.li@nxp.com>
Acked-by: Peter Chen <peter.chen@nxp.com>
(cherry picked from commit ba58ff8d3aaf00223911522c1a47a7afe6f70776)
Some typec super speed active channel switch can be controled via
a GPIO, this binding can be used to specify the switch node by
a GPIO and the remote endpoint of its consumre.
Signed-off-by: Li Jun <jun.li@nxp.com>
When DWC3 is set to host mode by programming register DWC3_GCTL, VBUS
(or its control signal) will turn on immediately on related Root Hub
ports. Then the VBUS will be de-asserted for a little while during xhci
reset (conducted by xhci driver) for a little while and back to normal.
This VBUS glitch might cause some USB devices emuration fail if kernel
boot with them connected. One SW workaround which can fix this is to
program all PORTSC[PP] to 0 to turn off VBUS immediately after setting
host mode in DWC3 driver(per signal measurement result, it will be too
late to do it in xhci-plat.c or xhci.c).
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Some chipidea hardware needs to disable low power mode for controller
due to IC issue or hardware issue, add one quirk for it.
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Upstream version is an initial version, it can't be used directly.
We will use downstream version for v5.4 instead.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
cherry-pick below patch from imx_3.14.y
ENGR00330403-3: ASoC: fsl: port si476x machine driver from imx_3.10.y
Port si476x machine dirver for i.MX series SoC and binding doc from imx_3.10.y
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
specify the spdif in imx8mm for the ipg clock is higher that
it can support 192kHz
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
Introduce a SoC data struct which contains the differences between
the different SoCs this driver supports. This makes it easy to support
more differences without having to introduce a new switch/case each
time.
And in imx8qm, the spdif has two interrupt numbers and the burst size
should be 2 for EDMA limitation to support dual FIFO.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
On imx8qm mek, the cs42888 is connected with i2c in cm41 domain,
but wm8960 is connected with i2c1, which is not in m4 domain.
So we only need to eable rpmsg for cs42888.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 9d2368aef40e4d107e4deee1a2c7e191c1afe644)
support more codecs, codec is specified by compatible string
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 7c92a75fcf83ec0aa3fe6773e4cb5f5e88a1ff09)
Add two new message command I2S_TX_POINTER and I2S_RX_POINTER,
which are used to get the hw pointer in m4 side. For in low
power audio mode, m4 won't send notification every period, the
notification only be sent when hw pointer reach end of buffer,
so we need these command to get the position of hw pointer,
user can use it to calculate the timestamp.
Restructure send message and recv message together for i2s_rpmsg,
that every send message has a recv message. so the
i2s_send_message can store the recv message indepedently. one
reason is that the receive message is async withe send message.
The low power audio is disabled in default, user need to enabled
it by add "fsl,enable-lpa" in dts.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 753e7b819609ad4791e32069a124d4411c720947)
Add machine driver, which is using the dummy codec.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Acked-by: Robin Gong <yibin.gong@nxp.com>
[ Aisheng: clean for a new base ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Add the cpu dai driver, as the rpmsg_send api can't be used in
atomic context, so using the workqueue instead of calling
rpmsg_send() directly.
The detail communication stack is defined in header file.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Acked-by: Robin Gong <yibin.gong@nxp.com>
[ Aisheng: split out imx-pcm.h changes ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
In order to support 44kHz and 48kHz sample rate together, we need to
reconfigure the parent clock of mclk.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Since commit 3f5780eb4520 ("MLK-16538-2: hdmi api: Relocate hdmi api
soure code") change the api. And hdmi video driver provide a new api
for hdmi audio. Machine driver need to be updated accrodingly
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
The machine driver will call the API which is provided by
the cadence to configure the audio features.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
[ Aisheng: clean for a new base ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
In order to avoid the name problem going forward with
integration with Qcom, Qcom has their own dsp and hifi
is competitor, so the hifi name should not be used in
our code.
So use the name of dsp instead of hifi to fix this
problem.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
IOMUXC_GPR2 register is not used for imx8, there is a new register
designed for this usage in imx8, so it also need the ipg clock.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Implement codec driver for mqs. mqs is a very simple IP. which support:
Word length: 16bit.
DAI format: Left-Justified, slave mode.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 9da6bdd2072b850e9bb910512123eff7d80a0e2f)
According to AK5558 MCLK frequence must not exceed 36.864 MHz.
Limit maximum supported rate as function of max MCLK frequency,
sample bits and number of slots.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 236796cad225daa39d5b77d763a1d964dd4de4c9)
The existing implementation calculates mclk rate as function
of audio sample rate multiplied to multiplier taken from Table 5.
However this is not accurate for Manual Setting Mode - tables 3 & 4 from
AK4458 RM defines rate (LRCK/FS) and frame width (MCLK/16fs..1152fs) ranges
as parameters to calculate mclk frequency. Aside of this - adjust
bclk:mclk ratio from machine driver as function of "compatible" id.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
(cherry picked from commit 527b8b7032dcb75c14bb2790330ab96743d83b16)
Use a specific compatible string for 850D in order to limit DSD MCLK
frequency for platforms newer than 850D.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
This glues SAI interface with AK4497 DAC codec on i.MX boards.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
[ Aisheng: Makefile clean for a new base ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Add machine driver for i.MX boards that have AK5558 ADC attached to SAI.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
[ Aisheng: clean for a new base ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Add machine driver for i.MX boards that have AK4458 DAC attached to SAI.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
[ Aisheng: clean for a new base ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
This a simple machine driver for wm8524.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
[ Aisheng: clean for a new base ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
cherry-pick below patch from v3.14.y:
ENGR00307635-5 ASoC: imx-wm8962: Add non-SSI cpu dai support
The current imx-wm8962 machine driver is designed for SSI as CPU DAI only
while as its name we should make the driver more generic to any other CPU
DAI on i.MX serires -- ESAI, SAI for example.
So this patch makes the driver more general so as to support those non-SSI
cases.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
(cherry picked from commit b6fca438dde1b4c0bbdee31729871d601f287dc9)
[ Aisheng: split dts changes ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
cherry-pick below patch from v3.14.y:
ENGR00277715-3 ASoC: fsl: Add WM8962 jack detecting support
There're two GPIOs connected to the headphone jack and microphone jack,
thus add the states detection.
Reviewed-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <b42378@freescale.com>
cherry-pick below patch from imx_3.14.y
ENGR00330403-1: ASoC: imx-cs42888: port cs42888 machine driver from imx_3.10.y
Port the cs42888 machine driver from imx_3.10.y and do update according to
new esai driver and asrc driver.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 7ed3aac83630a38eb397ed92f815a28e07198748)
Implement machine driver for mqs, which use the sai as cpu dai.
sai work on master mode.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit cac9eb41debc6444d753dc936cdf76874260b9e4)
EASRC (Enhanced ASRC) is a new IP module found on i.MX8 MN. It is
different from old ASRC module.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Viorel Suman <viorel.suman@nxp.com>
There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu" compatible
to support it.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Add device tree bindings documentation and useful definitions for SIUL2 pin
controller, which is found on the S32V234 SoC.
Signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com>
Signed-off-by: Ghennadi Procopciuc <Ghennadi.Procopciuc@nxp.com>
Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com>
It's pretty common that on some reference design or validation boards,
one pin could be used by two devices on board, and the pin route is
controlled by a GPIO. So to assert the pin for given device, not only
the pinmux controller in SoC needs to be set up properly but also the
GPIO needs to be pulled up/down.
The patch adds support of a device tree property "pinctrl-assert-gpios"
under client device node. It plays pretty much like a board level pin
multiplexer, and steers the pin route by controlling the GPIOs. When
client device has the property represent in its node, pinctrl device
tree mapping function will firstly pull up/down the GPIOs to assert the
pins for the device at board level.
[shawn.guo: cherry-pick commit e5a718edab82 from imx_3.10.y]
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Add rpmsg virtual gpio driver support.
i.MX7ULP GPIO PTA and PTB resource are managed by M4 core, setup one
simple protocol with M4 core based on RPMSG virtual IO to let A core
access such GPIOs that is what the driver do.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Dong Aisheng