This patch abstracts fetch unit concept for all the fetch units
we have - fetchdecode, fetcheco, fetchlayer and fetchwarp.
They have some similar features and operations which are suitable
to be abstracted. A lot of boilerplate code is removed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
In order to avoid the name problem going forward with
integration with Qcom, Qcom has their own dsp and hifi
is competitor, so the hifi name should not be used in
our code.
So use the name of dsp instead of hifi to fix this
problem.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
This patch adds prg_put_auxiliary() helper support so that users may
set a particular PRG not serve as an auxiliary one.
Signed-off-by: Yuchou Gan <yuchou.gan@nxp.com>
The architecture of dsp framework has been changed, the role of
dsp driver is transferring messages between dsp framework and user space
application, so change dsp driver to support this function.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
The drm_parse_ycbcr420_deep_color_info() is called only for HDMI 2.0,
however the DC masks were incorrectly set. These were set according
to HDMI 1.4 specification.
This patch will set the deep color depth masks to the HDMI 2.x specs
(see Table 10-6 in HDMI 2.x specs for field descriptions).
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit e3a1cac6fdd88f4391180d89d5881748214a1b4f)
Since the drm_bridge_attach function now supports chained bridges, there
is no need for nwl_dsi_add_bridge and nwl_dsi_del_bridge functions, so
remove them.
Now, we can pass the existent bridge to drm_bridge_attach.
This fixes a bug created during kernel 4.14 rebase process.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
This reverts commit c961b277abd69175e1b1ad733ed6b2b911a61211.
This patched worked on 4.14.18 but on 4.14.34 it now causes a deadlock
because upstream changed phy locking:
commit 6bccf8962b ("net: phy: Restore phy_resume() locking assumption"):
6bccf8962b
Instead of fixing locking just revert this patch, a different fix was
already upsteamed for ksz8081 suspend/resume on 6ul-14x14-evk:
commit e6f4292ae0 ("ARM: dts: imx6ul-14x14-evk: Add ksz8081 phy properties"):
e6f4292ae0
commit 79e498a9c7 ("net: phy: micrel: Restore led_mode and clk_sel on resume"):
79e498a9c7
After reverting this patch suspend/resume still works on imx6ul and
imx6ull evk boards.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Define a new struct 'dma_metadata' to hold the config parameters
for DEC400D. This struct data should be passed in from the fb's
first gem_obj's 'dma_buf' field.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Fetchdecode may work together with vscaler to do bob deinterlacing.
This patch adds the deinterlacing support for DPU DRM plane by using them.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds dpu_has_prefetch_fixup() helper support.
Users may use it to tell if a DPU has fixups for prefetch
engines in silicon or not.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds the first subsidiary layer0(out of layer0 to layer7)
support for the fetchwarp2 fetch unit to be the backend of DRM plane.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Fetchwarp is a type of dpu fetch unit with the additional
warping function. Each fetchwarp contains 8 subsidiary layers.
Fetchwarp2 can work with fetcheco2 to fetch planar YUV pixel
formats. Also, it may fetch RGB pixel formats. This patch
adds basic fetchwarp2 fetch unit support in the dpu common driver
so that it may fetch frames in RGB pixel formats. YUV pixel formats
and warping function could be supported later.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds the first subsidiary layer0(out of layer0 to layer7)
support for the fetchlayer0/1 fetch units to be the backend of DRM plane.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds some prefetch engine helpers support
in the dpu common driver so that callers may deal with
the prefetch engines of the fetch units the callers
are interested in.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Fetchlayer is a type of dpu fetch unit. Each fetchlayer
contains 8 subsidiary layers. Fetchlayer cannot work with
fetcheco to fetch planar YUV pixel formats. However, it may
fetch RGB pixel formats. This patch adds basic fetchlayer0/1
fetch units support in the dpu common driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
i.MX8QXP B0 silicon config enet IO voltage as 2.5V setting in default,
but MEK and ARM2 board only support 1.8V IO. So change the IO voltage
as 1.8V setting.
Set the MAC RGMII timing as TX no delay and RX delay mode as the default
setting for MEK and ARM2 board.
Since i.MX8QXP B0 silicon ENET IO timing change, to reach better timing
and avoid CRC error, MEK base board and ARM2 cpu board should remove the
driver device for the secord enet port.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
This patch adds prg_set_blit() helper support so that users may
set a particular PRG to be a part of a blit channel.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We don't have correct support for fb x/y source offset for tile formats.
The buffer address calculation is wrong when the offset is non-zero.
Also, finer offset needs a fix in silicon(TKT344978). So, let's do not
support the offset currently. We may add it back after we figure out
how the updated silicon supports the offset.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
According to ANSI-CTA-861-G specification:
* EOTF is 8 bit, not 16;
* metadata type is 8 bit, not 16;
* There's no "Minimum Content Light Level"
This patch will change the HDR metadata structures to reflect that. Also, this
will fix problems seen on some TVs that were rejecting HDR metadata because
it's size was too big (more than 26 bytes).
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
CC: Sandor Yu <sandor.yu@nxp.com>
NXP i.MX7ULP EVK boards all sensors connect with M4 core, A core
has to conmunicate with sensors by virtual io bus like rpmsg bus.
The driver implement the virtual sensor input driver to configure
sensors active/idle/delay actions and report the sensors' event to
user space.
Supply below sysfs for user to enable/disable detector and counter,
set poll delay:
/sys/class/misc/step_counter/enable
/sys/class/misc/step_detector/enable
/sys/class/misc/step_counter/poll_delay
Reviewed-by: Elven Wang <elven.wang@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Add feature of setting slot index via devicetree alias, to hard code the
mmc/sd root device.
The patch requires additional alias_id fix or it won't work.
Note: minor device number keep independent with this device alias.
Refer to the commit 35928d6c6a76 ("mmc: Allow setting slot index via
devicetree alias").
Acked-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
The DPR works in manual mode for the first frame and we need to
switch it to auto mode so that auto shadow load mechanism works.
The designers require us to switch the DPR manual mode to auto mode
directly for display controllers instead of using the DPR control
done irq handler, because the irq will not come in some cases(which
leads to shadow load failure). Finer switch operations on DPR
register bits are needed for SW_SHADOW_LOAD_SEL, SHADOW_LOAD_EN,
RUN_EN and REPEAT_EN. Also, for overlay planes, we need to wait for
a frame additionally in the "on-the-fly" cases to make sure the
switch is successful. In all, this patch should be able to address
frame dropping and screen tearing issue(due to the shadow load
failure) when users play video on overlay planes.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Use the bus format that was established by CRTC in
crtc->mode.private_flags.
This will be available during enable phase.
The DSI host will be configured via interface_color_coding
and pixel_format (DPI-2 interface ports).
Previously the interface_color_coding was hardcoded to 24-bit.
Set the DSI pixel format before it is necessary in
nwl_dsi_get_bit_clock, during imx_nwl_dsi_enable.
Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
The resources for a plane group are shared by the two display streams
of one DPU. Thus, the two Framegen(fg) instances of one DPU should be
in the plane group resource. The resource users may find the fg instance
onto which the resources are built via the stream id. This patch corrects
the number of fg instances in a plane group resource from one to two.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This adds the infrastructure needed to quirk displays
using edid and to mark them a non-desktop.
A non-desktop display is one which shouldn't normally be included
as a part of a desktop environment.
This is meant to cover head mounted devices like HTC Vive.
v2: Change description from non-standard to non-desktop, add docs
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Marius Vlad <marius-cristian.vlad@nxp.com>
(Ported 66660d4cf2 from git://people.freedesktop.org/~airlied/linux)
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as infoframe
to panel which support HDR.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
EA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Hardware may have HDR capability on certain plane
engines. Enabling the same in drm plane structure
so that this can be communicated to user space.
Each drm driver should set this flag to true for planes
which support HDR.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Since other USB 2.0 host may need it, like USB2 for XHCI. We move
this design to HCD core.
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
This patch fixes playback for movies with unaligned widths/heights and
adds cropping functionality for tiled formats. Untiled formats will not
have this feature as cropping is a DTRC function.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Add missing sosc_bus_clk/firc_bus_clk/spll_bus_clk clocks which will be used
by other devices later.
All these clocks use the same divider as ddr_div, so ulp_div_table is used.
Besides that, all these clocks need to be controlled by M4, so
CLK_DIVIDER_READ_ONLY is also specified.
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and
denominator value in register are start from 0.
This can be used to support frac dividers like below:
Divider output clock = Divider input clock x [(frac +1) / (div +1)]
where frac/div in register is:
000b - Divide by 1.
001b - Divide by 2.
010b - Divide by 3.
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
For dividers with zero indicating clock is disabled, instead of giving a
warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not
set" in exist code, we'd like to introduce enable/disable function for it.
e.g.
000b - Clock disabled
001b - Divide by 1
010b - Divide by 2
...
Set rate when the clk is disabled will cache the rate request and only
when the clk is enabled will the driver actually program the hardware to
have the requested divider value. Similarly, when the clk is disabled we'll
write a 0 there, but when the clk is enabled we'll restore whatever rate
(divider) was chosen last.
It does mean that recalc rate will be sort of odd, because when the clk is
off it will return 0, and when the clk is on it will return the right rate.
So to make things work, we'll need to return the cached rate in recalc rate
when the clk is off and read the hardware when the clk is on.
NOTE for the default off divider, the recalc rate will still return 0 as
there's still no proper preset rate. Enable such divider will give user
a reminder error message.
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
'CKIL' clock name is derived from MX6 SoC series which is invalid for
MX7ULP (can't find it from RM). Changing it to the correct 'ROSC'
which is defined in RM.
The exist 'OSC' name is also changed accordingly which should be SOSC
(System OSC).
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Add handling code to support tiled and compressed pixel source
layout. The tiled only layout will bypass DEC400D and be resolved
by DPR, since DEC400D is only responsible for decompression.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Add a new fb modifier for Vivante compressed and tiled
pixle layout which can be decompressed by DEC400D module
in DCSS.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
In order to support multi-fifo sdma script, the audio driver need to send
the fifo number to dma driver through dma_slave_config, and the cpu_dai
driver should config fifo_num for the audio platform driver, then platform
driver can config fifo_num to dma.
So add new variable fifo_num for struct snd_dmaengine_dai_dma_data.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Robin Gong<yibin.gong@nxp.com>
In order to support multi-fifo sdma script, the audio driver need to send
the fifo number to dma driver through dma_slave_config, so add src_fifo_num
and dst_fifo_num two new variable for struct dma_slave_config.
src_fifo_num: bit 0-7 is the fifo number, bit:8-11 is the fifo offset;
dst_fifo_num: same as src_fifo_num
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Robin Gong<yibin.gong@nxp.com>
This patch effectively enables DTRC module in DCSS to decode tiled
formats from VPU:
* uncompressed G1;
* uncompressed G2;
* compressed G2;
Compressed G2 formats need to pass on the decompression table offsets,
by using the 'dtrc_dec_ofs' property. This is a 64 bit value like below:
64--------48----------32---------16---------0
|<- chroma table ofs ->|<- luma table ofs ->|
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The DPU spec tells us that we need to wait for all pending frames to
be completed when a display stream is disabled. It turns out
that the hardcoded 60-microsecond timeout value is not enough for
some low refresh rate video modes, e.g., 1920x1080@24, which makes
the display stream be disabled incorrectly(leave the hardware an
incorrect machine status). The SoC design indicates that there are
two pending frames to complete in the worst case. This patch waits
for at most three frame duration(which is enough for sure) so that
the hardware may flush out all the pending frames. In case the clock
subsystem provides us a pixel clock with wrong rate and causes the
timeout value be unreasonably long, we truncate it to wait for at
most three seconds.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
"
commit cfdb9821531da523fd1f01536eb67c8b8451477f
Author: Oliver Brown <oliver.brown@nxp.com>
Date: Tue Jan 2 07:46:06 2018 -0600
dc: Add controls for display controller resets.
"
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Currently the clock parent actually is failed to be restored in power
domain driver due to the set_parent will bail out early as the clk core
already cached the same old parent.
Implement a CLK_SET_PARENT_NOCACHE flag in clk core and register all
SC mux clocks with this flag to make sure the clk core won't bypass
the SC clock parent setting.
[ Aisheng: "Add commit message" ]
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
In order to avoid license problem of Cadence header files, these
license files has been wrappered into a library and new interface
has been abstracted to replace the interface of Cadence header
files.
So update the mxc_hifi4.h file to provide new interface for
user space to use.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
On i.MX7ULP B0 chip, SNVS is located on M4 domain,
all RTC related functions need to use RPMSG channel
to communicate with M4 to proceed hardware operation.
The RTC RPMSG channel index is 6.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
This patch makes the necessary changes so that, for downscaling ratios
more than 3:1 and up to 7:1 (for video) and 5:1 (for graphics), the
WRSCL/RDSRC path will be used. This way the DRAM bandwidth will be lower
and spread evenly across the frame time.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The CCGR RAWNAND is shared by apbh-dma and gpmi clocks, so must use
imx_clk_gate2_shared2 to produce two clocks. Otherwise, apbh-dma clock
won't be enabled individually.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Add uSDHC clock MUX to allow uSDHC driver to select
parent, currently only support PLL0 and PLL1 as
uSDHC clock's parent.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Haibo Chen <haibo.chen@nxp.com>
When scaling up/down, DCSS has limits that cannot be exceeded. This
patch adds checks before the plane is updated and rejects those planes
that exceed the up/down scale limits.
Currently, the limit is 3:1 for downscaling and 1:3 for upscaling for
both video and graphics channels.
When support for WR_SCL/RD_SRC will be added, these limits will increase
to the following values:
* video: 7:1 downscale, 1:7 upscale
* graphics: 5:1 downscale, 1:5 upscale
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
To workaround the errata TKT320950, DPR/PRG need to evade the first dumb frame
which is generated by DPU. The way we achieve that is to bypass TCON(but set
the TCON sync signals and KA_CHUCK strobe signal up) before enabling the DPU
display controller, and then enable the display controller, wait for the frame
index starting to move and finally switch TCON to operation mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
When we use prefetch, we use DPR and PRG to do frame input cropping.
Thus, the stride of fetcheco is the stride of cropped frame, which means
the value of the stride is cropped_width * bytes_per_pixel. Since the
pixel format has to be NV12 or NV21 when we use prefetch, we assume the
cropped_width stands for how many UV we have in bytes for one line, while
bytes_per_pixel should be 8bits for every U or V component. Also, to
address TKT339017, when we use prefetch engine for fetcheco, we need to
round the stride up to the fetcheco burst size, i.e., burst length
multiplies 8 bytes. According to TKT343664, the buffer base address has
to align to burst size, so we'll pick an appropriate burst size value in
fetcheco_source_stride().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
When we use prefetch, we use DPR and PRG to do frame input cropping. Thus,
the stride of fetchdecode is the stride of cropped frame, which means the
value of the stride is cropped_width * bytes_per_pixel. Also, to address
TKT339017, when we use prefetch engine for fetchdecode, we need to round
the frame stride up to the fetchdecode burst size, i.e., burst length
multiplies 8 bytes. According to TKT343664, the buffer base address has
to align to burst size, so we'll pick an appropriate burst size value in
fetchdecode_source_stride().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds helper fetcheco_set_burstlength() so that
the burst length of fetcheco can be set to appropriate value.
When we don't use prefetch engine, the burst length is set to
the maximal value - 16. When we use prefetch engine, the burst
length should make the buffer base address align to burst size
but not greater than 16. This alignment operation can address
the issue recorded by TKT343664.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds helper fetchdecode_set_burstlength() so that
the burst length of fetchdecode can be set to appropriate value.
When we don't use prefetch engine, the burst length is set to
the maximal value - 16. When we use prefetch engine, the burst
length should make the buffer base address align to burst size
but not greater than 16. This alignment operation can address
the issue recorded by TKT343664.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds some helpers to set/get fetcheco off pin.
We need to pin fetcheco off when the primary plane is disabled and the
relevant fetcheco is feed by prefetch engine.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We will support DPR interrupts via DPU core driver.
In order to distinguish bewteen the inner DPU interrupts and the DPR
interrupts, let's rename some software stuffs which are related to
DPU interrupts so that they may show they are DPU inner explicitly.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The Display Prefetch Resolve(DPR) is a processor of fetching display data
before the display pipeline which needs data to drive pixels in the active
display region. The data is transformed, or resolved from a variety of
tiled buffer formats into linear format. The DPR transaction sequences are
issued with a high level of DRAM efficiency. This patch adds the base
driver support for i.MX8qm/qxp DPR.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The Pretch Resolve Gasket(PRG) is a digital core function as a gasket
interface between RTRAM controller and DPU. The main function of PRG
is to convert the AXI interface to RTRAM interface and remapping the
ARADDR to a RTRAM address. This patch adds the base driver support
for i.MX8qm/qxp PRG.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Amphion VPU has a tiled layout using 8x128 pixel vertical strips,
where each strip contains 1x16 groups of 8x8 pixels in a row-major layout.
Signed-off-by: Song Bing <bing.song@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Config NOC to limit bandwidth to 4GB for both VPU
and CPU to avoid lcdif flickering only when lcdif is enabled.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 8ab89ebeb94a423792bf588bdf2354c5960d8f13)
Currently the generic power domain suspend code pm_genpd_suspend_noirq
will try to power off a domain used by devices in genpd_sync_poweroff
if its status is not GPD_STATE_ACTIVE.
However, for power domains supporting multiple low power states, it may
already enter an intermediate low power state by runtime PM before system
suspend and the status is already GPD_STATE_POWER_OFF which results in
then the power domain stay at an intermediate low power state during
system suspend.
Let's give the power domain a chance to switch to the deepest state in
case it's already off but in an intermediate low power state.
Due to power domain is alway off, so no need to check device wakeup
case anymore.
Reviewed-by: Frank Li <frank.li@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
This patch adds 'use_global_alpha' property to the primary plane, so that
one can choose whether to use global alpha instead of per-pixel alpha,
when the framebuffer has per-pixel alpha.
Framebuffers that do not have per-pixel alpha will always use global
alpha.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Adds TEE_IOCTL_PARAM_ATTR_META with can be used to indicate meta
parameters when communicating with user space. These meta parameters can
be used by supplicant support multiple parallel requests at a time.
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Modified from: From: https://github.com/linaro-swg/linux.git
Conflicts:
drivers/tee/tee_core.c
(cherry picked from commit 66d81fcf145fdc55322c0a11764c76a43d90ecad)
Adds a kernel internal TEE client interface to be used by other drivers.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
From: https://github.com/linaro-swg/linux.git
(cherry picked from commit 860c46087c99c24073cc722b12c0017bb0ce0a79)
This change allows userland to create a tee_shm object that refers
to a dmabuf reference.
Userland provides a dmabuf file descriptor as buffer reference.
The created tee_shm object exported as a brand new dmabuf reference
used to provide a clean fd to userland. Userland shall closed this new
fd to release the tee_shm object resources. The initial dmabuf resources
are tracked independently through original dmabuf file descriptor.
Once the buffer is registered and until it is released, TEE driver
keeps a refcount on the registered dmabuf structure.
This change only support dmabuf references that relates to physically
contiguous memory buffers.
New tee_shm flag to identify tee_shm objects built from a registered
dmabuf: TEE_SHM_EXT_DMA_BUF. Such tee_shm structures are flagged both
TEE_SHM_DMA_BUF and TEE_SHM_EXT_DMA_BUF.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
From: https://github.com/linaro-swg/linux.git
(cherry picked from commit 41e21e5c405530590dc2dd10b2a8dbe64589840f)
Add CLKO2 for i.MX8MQ
Set parent for MIPI CSI1/2 CORE/PHY_REF/ESC
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Currently, the Northwest Logic MIPI-DSI controller host specific code
resides under drm/bridge, but is not a real drm_bridge. It creates a
drm_bridge and adds itself to the drm_encoder that handles this file,
but this is wrong, since it does not implement the drm_bridge_funcs.
The correct way to implement a drm_bridge is to add the drm_bridge and
let other components (another bridge or a drm_encoder) to attach to this
bridge.
Since we are doing this, a new compatible strings can be used for this
driver: "nwl,mipi-dsi".
Since this was used by nwl_dsi-imx.c, update that driver to use this
bridge correctly.
This is needed in order to add support for MIPI-DSI on 8MQ. The IMX_NWL
driver will either add a DSI encoder to DRM, or a DSI bridge.
The encoder will be used by imx-drm-core driver, while the bridge
will be used by MXSFB driver (which creates a simple display pipe).
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Add header file for the i.MX8mq IOMUXC GPR register offsets definitions.
Also, include definition for the GPR_MIPI_MUX_SEL from GPR13, needed by
MIPI-DSI driver.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
DTG needs to be completely stopped before changing the display
resolution through modesetting. If DTG is not stopped, any change in
resolution could result in unpredictable results, like split screen,
etc.
This patch fixes that by introducing a completion signaling mechanism so
that we can signal the DRM CRTC when DCSS core is done stopping DTG.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The Video PLL2 has a output enable bit to do clk gate,
So we need to register this gate to save power.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
drm_mode_create_lease
Creates a lease for a list of drm mode objects, returning an
fd for the new drm_master and a 64-bit identifier for the lessee
drm_mode_list_lesees
List the identifiers of the lessees for a master file
drm_mode_get_lease
List the leased objects for a master file
drm_mode_revoke_lease
Erase the set of objects managed by a lease.
This should suffice to at least create and query leases.
Changes for v2 as suggested by Daniel Vetter <daniel.vetter@ffwll.ch>:
* query ioctls only query the master associated with
the provided file.
* 'mask_lease' value has been removed
* change ioctl has been removed.
Changes for v3 suggested in part by Dave Airlie <airlied@gmail.com>
* Add revoke ioctl.
Changes for v4 suggested by Dave Airlie <airlied@gmail.com>
* Expand on the comment about the magic use of &drm_lease_idr_object
* Pad lease ioctl structures to align on 64-bit boundaries
Changes for v5 suggested by Dave Airlie <airlied@gmail.com>
* Check for non-negative object_id in create_lease to avoid debug
output from the kernel.
Changes for v6 provided by Dave Airlie <airlied@gmail.com>
* For non-universal planes add primary/cursor planes to lease
If we aren't exposing universal planes to this userspace client,
and it requests a lease on a crtc, we should implicitly export the
primary and cursor planes for the crtc.
If the lessee doesn't request universal planes, it will just see
the crtc, but if it does request them it will then see the plane
objects as well.
This also moves the object look ups earlier as a side effect, so
we'd exit the ioctl quicker for non-existant objects.
* Restrict leases to crtc/connector/planes.
This only allows leasing for objects we wish to allow.
Changes for v7 provided by Dave Airlie <airlied@gmail.com>
* Check pad args are 0
* Check create flags and object count are valid.
* Check return from fd allocation
* Refactor lease idr setup and add some simple validation
* Use idr_mutex uniformly (Keith)
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 62884cd386)
Attempts to modify un-leased objects are rejected with an error.
Information returned about unleased objects is modified to make them
appear unusable and/or disconnected.
Changes for v2 as suggested by Daniel Vetter <daniel.vetter@ffwll.ch>:
* With the change in the __drm_mode_object_find API to pass the
file_priv along, we can now centralize most of the lease-based
access checks in that function.
* A few places skip that API and require in-line checks.
Changes for v3 provided by Dave Airlie <airlied@redhat.com>
* remove support for leasing encoders.
* add support for leasing planes.
Changes for v4
* Only call drm_lease_held if DRIVER_MODESET.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 7de440db20)
This provides new data structures to hold "lease" information about
drm mode setting objects, and provides for creating new drm_masters
which have access to a subset of the available drm resources.
An 'owner' is a drm_master which is not leasing the objects from
another drm_master, and hence 'owns' them.
A 'lessee' is a drm_master which is leasing objects from some other
drm_master. Each lessee holds the set of objects which it is leasing
from the lessor.
A 'lessor' is a drm_master which is leasing objects to another
drm_master. This is the same as the owner in the current code.
The set of objects any drm_master 'controls' is limited to the set of
objects it leases (for lessees) or all objects (for owners).
Objects not controlled by a drm_master cannot be modified through the
various state manipulating ioctls, and any state reported back to user
space will be edited to make them appear idle and/or unusable. For
instance, connectors always report 'disconnected', while encoders
report no possible crtcs or clones.
The full list of lessees leasing objects from an owner (either
directly, or indirectly through another lessee), can be searched from
an idr in the drm_master of the owner.
Changes for v2 as suggested by Daniel Vetter <daniel.vetter@ffwll.ch>:
* Sub-leasing has been disabled.
* BUG_ON for lock checking replaced with lockdep_assert_held
* 'change' ioctl has been removed.
* Leased objects can always be controlled by the lessor; the
'mask_lease' flag has been removed
* Checking for leased status has been simplified, replacing
the drm_lease_check function with drm_lease_held.
Changes in v3, some suggested by Dave Airlie <airlied@gmail.com>
* Add revocation. This allows leases to be effectively revoked by
removing all of the objects they have access to. The lease itself
hangs around as it's hanging off a file.
* Free the leases IDR when the master is destroyed
* _drm_lease_held should look at lessees, not lessor
* Allow non-master files to check for lease status
Changes in v4, suggested by Dave Airlie <airlied@gmail.com>
* Formatting and whitespace changes
Changes in v5 (airlied)
* check DRIVER_MODESET before lease destroy call
* check DRIVER_MODESET for lease revoke (Chris)
* Use idr_mutex uniformly for all lease elements of struct drm_master. (Keith)
Signed-off-by: Keith Packard <keithp@keithp.com>
(cherry picked from commit 2ed077e467)
This will allow __drm_mode_object_file to be extended to perform
access control checks based on the file in use.
v2: Also fix up vboxvideo driver in staging
[airlied: merging early as this is an API change]
Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 418da17214)
Separate out lease debugging from the core.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit e7646f84ad)
Add missing clocks for MIPI-DSI SS: RX_ESC and TX_ESC
Also added the posibility to select clock parents for MIPI-DSI versus
LVDS.
The SCFW was changed, so now the LVDS pixel and phy clocks need to
specify their parrents.
Also, the TX_ESC and RX_ESC clocks from MIPI-DSI need to specify their
parrents in DTS files.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Add support for the NorthWest Logit MIPI-DSI controller found in mx8
platforms: i.MX8qm, i.MX8qxp and i.MX8mq.
The NWL MIPI-DSI driver is implemented as a DRM bridge.
The MIPI-DSI encoder will contain the platform specific changes and will
use this bridge.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
This patch adds base suport for i.MX8M's Display Controller
subsystem(DCSS). It has built-in DPR, Scaler and HDR10 modules. Also, it
features a video Decompression and Tile to Raster Conversion (DTRC) unit,
as well as a graphics pixel decompression infrastracture (DEC400D).
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
This patch improves DPU KMS by the following means:
1) Wait for shadow registers being loaded in ->atomic_flush()
to make sure there is no intermediate register values being
loaded when doing atomic update.
2) Improve CRTC enablement/disablement sequences/configurations
according to spec.
3) Remove the FGDM__PRIM framegen display mode from ->mode_set_nofb()
and always use FGDM__SEC_ON_TOP mode so that we may prepare
for introducing a safety stream solution in the future.
4) Better vblank on/off and vblank event handling, though there
should be no essential improvements.
5) Some fixes for adding correct CRTC/plane/connector states
in the full atomic state in dpu_drm_atomic_check().
6) Remove CRTC and plane states from the full atomic state where
possible to improve atomic update performance.
7) Introduce a plane group mutex to protect plane source mask and
vproc source mask. This is a little bit superfluous due to
the protection provided by the atomic helper, but just one of
the DPU core itself.
The changes are in a bundle to avoid any unexpected drawbacks
of introducing them at a smaller granularity.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
On i.MX8MQ, the new revision SoC does NOT update the
revision info in ANATOP_DIGPROG register, to support
dynamic SOC id/revision detection, only reading info
from ANATOP_DIGPROG is not working now, change to read
SOC id/revision from ATF which is in secure world.
The ATF will read the ANATOP_DIGPROG as well as ROM
version to decide the SOC revision.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Support M4/A53 work together
1. add imx_src_is_m4_enabled
2. introduce a new dts dedicated for m4
3. add more pwm nodes
4. Since clk initialization is at very early stage, add m4 enabled check
in the beginning of clk code.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Add busfreq driver support on i.MX8MQ. The busfreq driver is
mainly used for dynamic DDR frequency change for power saving
feature. When there is no peripheral or DMA device has direct
access to DDR memory, we can lower the DDR frequency to save
power. Currently, we support frequency setpoint for LPDDR4:
(1): 3200mts, the DDRC core clock is sourced from 800MHz
dram_pll, the DDRC apb clock is 200MHz.
(2): 400mts, the DDRC core clock is source from sys1_pll_400m,
the DDRC apb clock is is sourced from sys1_pll_40m.
(3): 100mts, the DDRC core clock is sourced from sys1_pll_100m,
the DDRC apb clock is sourced from sys1_pll_40m.
In our busfreq driver, we have three mode supported:
* high bus mode <-----> 3200mts;
* audio bus mode <-----> 400mts;
* low bus mode <-----> 100mts;
The actual DDR frequency is done in ARM trusted firmware by calling
the SMCC SiP service call.
BuildInfo:
- IMX-MKIMAGE: 05d3d4a7d7, ATF: 724cc2b890
- SPL/Uboot: f72c10d2db;
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
On i.MX8MQ, the dram core clock can be sourced from dram_pll or
the dram_alt clock, when sourced from the dram_alt, it has a fix
divider(1/4). When the DDRC core clock is lower than 800MHz, we
can swith the core clock to dram_alt source.
The dram apb clock's mux option 2 should be sys1_pll_40m, so fixed it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
This watchdog driver is a virtual driver in Linux and call ATF interface
where call SCFW eventually. In SCFW, it's done by SCU timer tick instead
of hardware watchdog.This is why we have to call ATF because such system
resource owned by secure patition.Currently, booard reset happen if not
ping this software watchdog in time in linux side, may change to partition
reboot once SCFW support this feature in the future.
BuildInfo:
- SCFW 93c142a9, IMX-MKIMAGE 2522fd70, ATF f2547fb
- U-Boot 2017.03-00097-gd7599cf
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
- Init multi-core mu power and clk.
- enable the multi-core rpmsg support
BuildInfo:
- SCFW a6fd9a48, IMX-MKIMAGE 0, ATF 0
- U-Boot 2017.03-imx_v2017.03_4.9.11_imx8_alpha+g258936c
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Tested-by: Andy Duan <fugang.duan@nxp.com>
Add rpmsg virtual gpio driver support.
i.MX7ULP GPIO PTA and PTB resource are managed by M4 core, setup one
simple protocol with M4 core based on RPMSG virtual IO to let A core
access such GPIOs that is what the driver do.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
add reset command declaration into mxc_hifi4.h file,
this command is used to reset hifi4 codec when seeking
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
DC clocks can choose their clock source between PLL1, PLL2 and
bypass input.
This patch introduces a multiplexer in the dc clock topology to
allow this choice and introduces one set of parents that will be used
for both display0 and display1 clocks.
Clock paths tested:
1. PLL2(dc0_pll1_clk)->DC0_DISP1(dc0_disp1_clk)->LVDS
2. BYP(dc0_bypass0_clk)->DC0_DISP1(dc0_disp1_clk)->LVDS
(BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0)
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
Reviewed by: Ranjani Vaidyanathan <Ranjani.vaidyanathan@nxp.com>
update the mxc_hifi4.h header file to support multi-codec
decoding or encoding together for hifi4 dsp.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
Reviewed-by: Mihai Serban <mihai.serban@nxp.com>
strobe-dll-delay-target is the delay cell add on the strobe line.
Strobe line the the uSDHC loopback read clock which is use in HS400
mode. Different strobe-dll-delay-target may need to set for different
board/SoC. If this delay cell is not set to an appropriate value,
we may see some read operation meet CRC error after HS400 mode select
which already pass the tuning.
This patch add the strobe-dll-delay-target setting in driver, so that
user can easily config this delay cell in dts file.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
In pxp lib, the unit of stride parameter is pixel and stride
is not equal with width parameter of out buffer in some cases.
In order to use latest pxp lib in old version rootfs, PXP_DEVICE_LEGACY
macro is used to distinguish pxp drvier version. Because the
new pxp driver define a new variable and pxp lib can know this
through PXP_DEVICE_LEGACY, and determine if use it.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 91da74e81c)
Add focaltech new touch panel ft5246 support.
Set the ft5426 as default panel for dts. If want to use the old panel, then
it needs to boot with imx7ulp-evk-ft5416.dtb file.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
(cherry picked from commit:963fea909ef5e42294cb2e656e5e3870a2171c01)
For system controller RTC, as it belongs SC_R_SYSTEM,
and SC_R_SYSTEM is assigned in ARM-Trusted-Firmware,
so here needs to use SIP to trap into ATF to do set
time, or system controller firmware will return
error since linux kernel does NOT own this system
resource.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
A component master may have both OF based and non-OF based components to be
bound with. This patch adds a helper drm_of_component_probe_with_match()
similar to drm_of_component_probe() so that the new helper may get an
additional provided match pointer(contains match entries for non-OF based
components) to support this case.
Tested-by: Meng Mingming <mingming.meng@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
No one is using the list in the dpu plane group, so let's remove it and
the mutex lock which protects the list.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Until mmc has blk-mq support fully implemented and tested, add a parameter
use_blk_mq, set to true if config option MMC_MQ_DEFAULT is selected, which
it is by default.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit c3d53d0da6)
Currently the host can be claimed by a task. Change this so that the host
can be claimed by a context that may or may not be a task. This provides
for the host to be claimed by a block driver queue to support blk-mq, while
maintaining compatibility with the existing use of mmc_claim_host().
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 6c0cedd1ef)
Adjust for small imx changes in debugfs
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Add core support for handling CQE requests, including starting, completing
and recovering.
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
(cherry picked from commit 72a5af554d)
Add SIP cpu-freq support, the CPU hardware frequency
scale will be performed by ARM Trusted Firmware,
and add cpu-freq suspend support, MAX frequency will
be used during suspend.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Define three root clocks for DCSS module:
.IMX8MQ_CLK_DISP_AXI_ROOT
.IMX8MQ_CLK_DISP_APB_ROOT
.IMX8MQ_CLK_DISP_RTRM_ROOT
These root clocks share one clock gate along with
'IMX8MQ_CLK_DISP_ROOT' clock. So change its type
to be shared gate clock too.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Add interface to get typec port type and default power role from
dt. To validate a correct setting is specified, add TYPEC_PORT_TYPE_UNKNOWN
and TYPEC_ROLE_UNKNOWN for typec_port_type and typec_role enum.
Reviewed-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
During 4.14 rebase renamed to typec_port_types_dt to avoid conflict with
sysfs values.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
As the fsl_hifi4.c uses the function from uboot/cmd/elf.c,
so need to add the copyright of elf.c, and change licence to
Dual BSD/GPL.
And mxc_hifi4.h is used by user space, so change license to BSD.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
On i.mx8mscale, there are two sdma instances here, and common dma
frameowrk will get channel dynamicly from any available channel whatever
it's from the first sdma device or the second sdma device. But actually,
some IP like SAI only work in sdma2 not sdma1. To make sure get sdma
channel from the right sdma device, add index to match.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
This patch adds support for 64bit platforms, on top of existing 32bit
support. Among some noticeable differences that occurred for the MIPI DSI
Northwest controller: 4 lane support is added and power management differs.
MIPI DSI Northwest driver changes are added from Fancy Fang's commit
df47fccaf6 "MLK-15322-8 video: fbdev: imx_northwest_dsi: enable Northwest
mipi dsi driver".
Signed-off-by: Cristina Ciocan <cristina-mihaela.ciocan@nxp.com>
This patch adds helper fetchdecode_need_fetcheco() so that users may
check if a fetchdecode needs to use fetcheco for a specific pixel format.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds helper fetchdecode_get_fetcheco() so that users may
get the relevant fetcheco via fetchdecode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds more sources for fetchdecode.
The new sources are fetchdecode0, fetchdecode1 and fetchwarp2,
which are valid only on DPU v2.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds helpers dpu_vproc_has/get_fetcheco_cap() support
so that the users may check if a video processing mask has fetcheco
capability or get the fetcheco capability from the mask.
We currently only support fetcheco0 and fetcheco1.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The bit to enable/disable source buffer is embedded in the register
LAYERPORPERTY0. However, the other bits of the register may have
other functionalities. So, using fetchdecode_layerproperty() to
enable/disable source buffer isn't appropriate. This patch uses
new functions to enable/disable fetchdecode source buffer so that
the function names could be a bit specific about what they are doing.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch is to refine the imx8 soc revision support. The imx8qm and
imx8qxp will go through the SCU API to get the silicon ID and REVISION.
imx8mq will go through the anatop interface to get the ID/REV.
Since the silicon ID/REV need be set as early as possible, thus refine it
by using the early_initcall for the early initialization. For the SCU API
interface, this need be called after the MU interface initialized.
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Add compat ioctl for 32 bit application
This is re-commit: only reserve hantro driver change
remove mxc_ion change
Signed-off-by: Zhou Peng-B04994 <eagle.zhou@nxp.com>
This patch adds scalers support in dpu plane group. A module parameter,
i.e., display_plane_video_proc, is introduced to enable or disable video
processing capability of display plane, since some video processing units
are shared with capture controllers. By default, it is enabled.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The output of FetchDecode can be the input of HScaler and/or VScaler.
If both of the two scalers are wanted, the two scalers can be connected
with each other by themselves as an united scaler unit. This patch adds
basic scaling capability support for FetchDecode. Three helpers are
introduced - fetchdecode_get_vproc_mask() and fetchdecode_get_h/vscaler().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds basic HScaler and VScaler support in the DPU core driver.
The two scaler units can be used in the display controller, blit engine
or capture controller. Currently, we only support the display controller.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
There are several DPU units which have the same clock enable control bits
in their Dynamic registers, e.g., HScaler, VScaler, Rop, Fliter and Matrix,
etc. So, let's remove the prefix 'lb_' from the enumerator name of
lb_pixengcfg_clk_t so that it can be a little bit generic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The member name 'NEUTRAL' of enum lb_mode_t is a little bit too generic,
since others DPU units have neutral modes as well, e.g., HScaler, VScaler,
Rop, CLuT and Matrix, etc. So, let's add the prefix 'LB_' to member names
of enum lb_mode_t so that they can be specific to LayerBlends.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
1. add cases to receive error value from hifi4 firmware and
return this error to hifi4 driver's caller.
2. add cases to receive input over indicator variable from
hifi4 dirver's caller and pass this value to hifi4 firmware
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
IMX7d does not contain an M0 Core and this particular
clock doesn't seem connected to anything else.
Remove this entry from the CCM driver.
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
The DPU fetch units(backing DRM planes) are shared by two displays(a.k.a,
CRTCs). Since the shadow trigger/load mechanism of each display(CRTC)
is independent from each other, on-the-fly/hot migration of plane source
is likely to cause resouce conflict issue when the shadow registers are
loaded. This patch changes the way we assign fetch units for each DRM
planes so that we may avoid the migrations from happening. Thanks to
the DRM atomic check nature, cold migrations still can be supported.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Add generic power domain driver support on i.mx8mq. The power
domain on/off operations need to use the SIP service call to
trap into secure monitor to handle it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
SmartEEE feature is enabled in default, add interface for user to disable
the feature for IEEE1588 high accurate convergence.
The phy support 1.8v RGMII VDDIO voltage, add interface for user to enable
VDDIO 1.8v support.
When phy/RJ45 power supply is not stable, LED_ACT may be busy on blinding,
add sw workaround to fix the issue.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Reviewed-by: Pandy Gao <pandy.gao@nxp.com>
Add wdog nodes in dtsi.
Enable wdog1 for imx8mq evk board.
Enable imx wdt in defconfig.
Correct clock, offset 0x4550 is actually for wdog3.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
imx8mq iomux header file uart part select_input config are
wrong that cause most of uart pin not work.
Add DCE and DTE string to distinguish the pin is for uart
which function, and clear all select_input for output pin.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
add audio ipg clock, sai ipg clock and correct some wrong
place in clock tree.
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Add mipi csi local interrupter clock
Rename image subsystem power domain name.
Rename mipi csi LIS clock name.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
During 4.14 rebase squashed MLK-15124-01 and MLK-15124-02 because they
do not build separately.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
- use one standalone hsio node to share the region to
pciea, pcieb and sata.
- axi master slave and dbi clks and pipe_clk are required
- enable pcieb
change the pd of the pcieb, otherwise, clk is failed to enable
- add the cpu addr offset
Bit[31:24]
pciea 60 - 6f ---> 40 - 4f
pcieb 70 - 7f ---> 80 - 8f
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
This patch adds Mixel LVDS combo PHY support(MIPI DSI and LVDS combo).
This LVDS PHY supports one LVDS channel in single mode and two channels in
dual mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
DPU is the display processing unit embedded in i.MX8qm and i.MX8qxp.
It was originally designed by Fujitsu.
The first revision has capture controller, display controller and blit engine.
The second revision is a lite one and has display controller and blit engine.
This patch adds a base driver for DPU, which provides a thin register wrapper,
interrurpt support and client platform device register for the upper layer to
use. Currently, the driver only supports the display controller at the pixel
processing level and only the fetchdecodes are supported/tested as the fetch
units.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds 30bit RGB101010 LVDS pixel formats support for
the SPWG and JEIDA LVDS mapping standards. Each pixel is transferred
on 5 lanes with 7bit respectively.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
According to commit b073ed4e21 ("ASoC: soc-pcm: DPCM cares BE format"),
Current DPCM only care FE channel, but it will set unsupported channel to
drivers.
So add dpcm_merged_chan, which is used to merge the BE's codec
channels configuration to FE if it exist in snd_soc_dai_link. And
dpcm_runtime_base_chan function is to get the channel configuration of BE,
which likes the dpcm_runtime_base_format function.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
(cherry picked from commit 19ff1095d4)
Ensure that both PLL and IPG clocks are enabled and set by
the HDMI irqsteer device tree entry.
Fix some HDMI clock names.
The HDMI irqsteer incorrectly assumed that the HDMI bus clock will
be enabled automatically by the SCFW when HDMI SS is powered up.
Fix HDMI clocks so that the HDMI IPG clock is enabled when required.
Also fix all the LPCG addresses by HDMI clocks.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
When 'CONFIG_MXC_PXP_CLIENT_DEVICE' disabled, the
'register_pxp_device' and 'unregister_pxp_device'
may cause multiple definitions compiling error.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The latest pxp_dma.h file change PXP_PIX_FMT_RGB32 to PXP_PIX_FMT_XRGB32 format,
but the userspace still use PXP_PIX_FMT_RGB32, so add back it and keep the same
with PXP_PIX_FMT_XRGB32 format.
Signed-off-by: Guoniu.Zhou <guoniu.zhou@nxp.com>
Liu Ying