This flag should be before the operation-specific REQ_NOUNMAP bit.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Sagi Grimberg <sagi@grimberg.me>
Reviewed-by: Hannes Reinecke <hare@suse.com>
Reviewed-by: Johannes Thumshirn <jthumshirn@suse.de>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
(cherry picked from commit 8977f56384)
These two functions are only called from inside the block layer so
unexport them.
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Bart Van Assche <bart.vanassche@wdc.com>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
(cherry picked from commit 83d016ac86)
According to LCDIF specification, the input pixel data
width and the output pixel data width can be different,
and this conversion is done by LCDIF automatically. So
config the output data width according to the requested
bus format from the encoder, instead to be same with the
input pixel data width.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit bfd27f6d71d86a7f2fc8314f082565db3682b925)
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit 8bc09ad559237c136f88d93bd696fe10dc4658db)
By default, imx8qm b0 silicon set the IO voltage to 2.5v, but the arm2
board is designed as 1.8v voltage for enet IO, so force the IO voltage
to 1.8 by setting COMP_CTL_GPIO_1V8_3V3 pins like:
For ENET0: SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB
For ENET1: SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA
The pin setting:
1.8V/3.3V : bit4=0, bit[30]=1, bit[2:0]=000
2.5V : bit4=1, bit[30]=1, bit[2:0]=010
For 2.5v IO timing test, HW board need to do some rework:
- Force PHY work at 2.5v mode
- Supply 1.8v voltage to VDD_ENETx
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Enabled the FlexSPI Octal DDR read for QXP, since all parameters for
this mode cannot be read from SFDP table, set the related parameters in
spi_nor_init_params.
Signed-off-by: Han Xu <han.xu@nxp.com>
Some MICRON related macros in spi-nor domain were ST, actually. We
need to add the REAL micron defination in header/source files for
mt35xu512aba Micron Octal Nor chip.
Signed-off-by: Han Xu <han.xu@nxp.com>
Enhanced spi-nor framework to support octal read mode
Signed-off-by: Han Xu <han.xu@nxp.com>
Acked-by: Frank Li <frank.li@nxp.com>
(cherry picked from commit 95d0d54019ec291bf5430090dccb6dd66ea87de7)
According to the LCDIF specification, the Legacy Mode does not
support cropping function in the horizontal direction, so add
Pigeon Mode which can support this kind of function. And when
enable this mode, the legacy horizontal timings configuration
should use stride value but not the active width, and related
pigeon configuration should use the active width but not the
stride value.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit e6da9542693dd585972897f62748a101f5726a74)
Remove unused ROMCP clks and related as LPCG
no longer exists
Signed-off-by: Teo Hall <teo.hall@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 1c15332dffe7e41f0b9d367b96dd426798ec8b06)
In the L1.1 ASPM implementation, the CLK_REQ# should be
configured as open drain, pull up and input mode.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
In the L1.1 ASPM implementation, the CLK_REQ# should be
configured as open drain, pull up and input mode.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Add SAI1 PDM pin definitions for imx8mm SoC.
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
(cherry picked from commit 1ada53b6b48dc6e7360b75403bd0796b4bf52cf9)
On i.MX8MM, it has an dram_alt clock source that can be used when
DDRC clock rate is lower than 667MHz, so add this clock.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 303867c769e3c0758b9ee8fcf31d8cc3c632a80d)
Add LCDIF PLL resource and clocks, and power domain for it.
Add Pixel link clocks and set it from bypass path.
Muxes were added so that the slices can choose the bypass input
(lcd_pxl_bypass_div and elcdif_pll_div).
clk summary example:
lcd_pxl_bypass_div 2 2 24000000
lcd_pxl_sel 1 1 24000000
lcd_pxl_div 1 1 24000000
lcd_pxl_clk 1 1 24000000
elcdif_pll_div 1 1 792000000
elcdif_pll 2 2 792000000
lcd_sel 1 1 792000000
lcd_div 1 1 79200000
lcd_clk 1 1 79200000
Signed-off-by: Adriana Reus <adriana.reus@nxp.com>
DCSS needs PM QoS in order to keep interrupt latency low. Otherwise,
page flipping will not work smooth enough because CTXLD will not be
triggered in time.
Currently, PM QoS is requested all the time but that does not allow the
CPUs to go idle. Hence, this leads to increased power consumption.
This patch will change how PM QoS is requested by doing it only when
VBLANK is enabled/disabled. The VBLANK interrupt is enabled just before
a commit takes place and disabled after one second after last commit.
This will allow DCSS to function properly and, also, allow CPUs to go
idle whenever there's no buffer submitted.
Exception to this is when DTRC is used (when DCSS is passed tiled
buffers). In this case, PM QoS will always be active, even if no buffer
is submitted, because DTRC banks need to be switched in CTXLD ISR, so
that DCSS does not underrun. DTRC does not have the REPEAT feature, as
the rest of DCSS does.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Implement different sync method, replace previous signal with ioctl
Related functions were added
(cherry-pick from : adc4bc267e5c3a33ca802de83e2693638a7be8e8)
Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
In order to replace the M4_MU# by the LSIO MU in the
RPMSG usage.
Define the PD and LPCG address of the LSIO MU for iMX8.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
This patch adds a DCSS tracing mechanism that introduces as low latency
as possible, so that it does not affect timings. Instead of text, 64 bit
tags will be logged, together with the system time in nanoseconds. Based
on these, post-processing can be done on any PC to compute deltas,
delays, missed buffers, etc.
Example usage:
echo 1 > /sys/module/imx_dcss_core/parameters/tracing
gplay-1.0 movie.mpg
echo 0 > /sys/module/imx_dcss_core/parameters/tracing
To dump the trace:
cat /sys/kernel/debug/imx-dcss/dump_trace_log > trace.txt
With the help of a scripting language (awk), the trace can then be
post-processed and analyzed on the PC.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The device 43428 is a new SDIO device ID but shares the same WLAN core
with device 43430a1. It is a 1x1 802.11b/g/n 2.4GHz HT20,
256-QAM/Turbo QAM WLAN chip.
Signed-off-by: Wright Feng <wright.feng@cypress.com>
Signed-off-by: Chi-hsien Lin <chi-hsien.lin@cypress.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
CYW43012 is a 1x1 802.11a/b/g/n Dual-Band HT20, 256-QAM/Turbo QAM. It
is an Ultra Low Power WLAN+BT combo chip.
Signed-off-by: Chi-Hsien Lin <chi-hsien.lin@cypress.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
To support lowest power mode for suspend, if no wakeup source
from non-secure partition is enabled, IRQSTEER can be powered
off when suspend, otherwise, IRQSTEER needs to be powered on
to support wakeup, so need to pass WU domain wakeup source
info to ATF, then ATF will decide if to power off IRQSTEER
when system suspend.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Let Dom0 use hvc to trap to xen to communicate with SCU.
xen could reuse the MU used by Dom0 before. By reusing
the MU in Dom0, xen has power to control resources owned
by DomU.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
This patch adds the MIPI PWM_DIV and PWM_CLK clock definitions.
The PWM_DIV clock is the parent clock of PWM_CLK clock.
The PWM_CLK will be used as the 'per' clock by the PWM driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit a32d7b4bcca3da7bd154eaf46cf04852279d2c87)
The video tearing appeared only when the application used 2 buffers.
That's because, sometimes, the context loader could be armed after the
DB event came in the frame trace. That made a buffer submitted in frame
N end up on screen in frame N+2 because the context loader waits for the
next DB event. Since vblank events are sent at the end of the frame, by
the time the buffer lands on screen, the application will reuse it while
it's being displayed, hence the tearing effect.
This patch moves the CTXLD trigger moment all the way to the end of the
frame trace, just before DB event arrives. This will leave the
application plenty of time to submit new buffers.
In the event that the trigger moment is missed (application submits a
buffer right at the end of a frame trace), then we're not signalling the
next VBLANK event to application. This way, application will know that
the buffer is still needed and will not submit a new one.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
External differential clock phy_27m can be set to all
plls, rename from VIDEO2_PHY_27M to CLK_PHY_27M to avoid
confusion as clock source is the same option for all plls
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit e4ac6dff8fa2eda6f5c2ed35cfea3550c59916da)
i.MX8dx/dxp/qxp use two LDBs(one primary, one auxiliary) to support
dual channel mode. This patch adds the dual channel mode support
for i.MX8dx/dxp/qxp. Note that the drivers contain specific sequence
needed by this mode - LDB VSYNC polarity and channel selection settings
should be configured into the register a bit earlier in ->atomic_mode_set
instead of in ->enable, and DC subsystem pixel link enablement is moved
from the DPU driver to the LDB driver to make sure it happens later
than LDB clocks enablement in ->enable.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Add an function to get the LCDIF controller supported bus
formats according to the pixel format bpp. And change the
bus format sanity check in the plane's atomic check to see
if the bus format required by the peripheral attached to
LCDIF can be supported by LCDIF.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
This is the abstracted bridge driver for Samsung MIPI DSIM
controller. This driver only foucses on the DSIM controller
itself configurations and never care about any config about
the platforms. So it can be shared by different platforms
without any modifications.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The LCDIF core driver is responsible to provide controller
registers configuration and create the platform devices for
the child port nodes. And the platform devices later will
attach to the corresponding DRM/KMS drivers via name match.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
- Sync with scu firmware commit 576011819ce3 (SCF-81: Added API to
control MIPI CSI calibration.) and commit 095a0d7dbc0b (SCF-85: Add
direct control of ENET IPG stop control)
- Add ipg stop misc controls for CONN ENET.
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
The framegen driver should get PLL clock, bypass clock and display
selection/mux clock via device tree if available. It may use bypass
clock when a TMDS encoder is connected with the framegen, otherwise,
PLL clock is used. This way, the assigned-clocks and assigned-clock-parents
device tree properties can be removed from the dpu device tree node.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Add new cell for sw_done/sw_done_selector, because PDM need enable
software done feature in sdma script.
The new fourth cell defined as below:
Bit31: sw_done
Bit15~bit0: selector
For example: 0x80000000 means sw_done enabled for done0 sector which
is for PDM on i.mx8mm.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
We use PRG x/y offset to do in-micro-tile cropping for new DPR/PRG IPs.
When tile resolving is enabled by using the new IPs, the design team
indicates that DPU fetch unit base address and DPU/PRG stride need to be
calculated in the below steps:
1) prg_Baddr = dpr_Baddr
2) tmp_dpu_Baddr = prg_Baddr + prg_x_offset * bytes_per_pixel
3) tmp_burst_size = 1 << (ffs(tmp_dpu_Baddr) - 1)
tmp_burst_size = round_up(tmp_burst_size, 8)
burst_size = min(tmp_burst_size, 128)
4) tmp_dpu_stride = dpu_width * bytes_per_pixel
5) dpu_stride =
round_up(tmp_dpu_stride + round_up(tmp_dpu_Baddr % 8, 8), burst_size)
6) dpu_Baddr = tmp_dpu_Baddr + prg_y_offset * dpu_stride
7) prg_stride = dpu_stride
The legacy DPR/PRG IPs and linear formats driver logic should not be
essentially touched.
This patch implements the above calculation method in the drivers
so that all valid in-micro-tile x/y cropping arguments can be supported.
Without this, at least, some cropping cases with odd x value would fail.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
[Patch] Pulling the following commits and some general changes
from custom v3.10 kernel for supporting qcacld2.0 on kernel v4.9.11.
1. cfg80211: Using new wiphy flag WIPHY_FLAG_DFS_OFFLOAD
When flag WIPHY_FLAG_DFS_OFFLOAD is defined, the driver would handle
all the DFS related operations. Therefore the kernel needs to ignore
the DFS state that it uses to block the userspace calls to the driver
through cfg80211 APIs. Also it should treat the userspace calls to
start radar detection as a no-op.
Please note that changes in util.c is not picked up explicitly.
Kernel v4.9.11 uses wrapper cfg80211_get_chans_dfs_required which takes
care of this change.
Change-Id: I9dd2076945581ca67e54dfc96dd3dbc526c6f0a2
IRs-Fixed: 202686
2. New db.txt from git/sforshee/wireless-regdb.git
CONFIG_CFG80211_INTERNAL_REGDB is enabled in build. This causes
kernel warn messages as db.txt is empty. A new db.txt is added
from:
git://git.kernel.org/pub/scm/linux/kernel/git/sforshee/wireless-regdb.git
IRs-Fixed: 202686
3. Picked up the declaration and definition of the function
cfg80211_is_gratuitous_arp_unsolicited_na
Change-Id: I1e4083a2327c121073226aa6b75bb6b5b97cec00
CRs-fixed: 1079453
Signed-off-by: Nakul Kachhwaha <nkachh@codeaurora.org>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
It turns out that local alpha value of the secondary input is set to
0xFF by the hardware if the secondary input is from scaler(hscaler or
vscaler). This makes the layer on this secondary input accidentally
cover the layer with higher z-order(if it exists), even though the
layer with lower z-order doesn't supply local alpha. This patch zeros
the secondary local alpha value to prevent the issue from happening.
Users are unlikely to expect local alpha to be correctly scaled, so
it looks fine to simply zero the alpha. If we find the unlikely case,
the KMS driver may later explicitly do atomic check to invalidate the case.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch abstracts fetch unit concept for all the fetch units
we have - fetchdecode, fetcheco, fetchlayer and fetchwarp.
They have some similar features and operations which are suitable
to be abstracted. A lot of boilerplate code is removed.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
In order to avoid the name problem going forward with
integration with Qcom, Qcom has their own dsp and hifi
is competitor, so the hifi name should not be used in
our code.
So use the name of dsp instead of hifi to fix this
problem.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
This patch adds prg_put_auxiliary() helper support so that users may
set a particular PRG not serve as an auxiliary one.
Signed-off-by: Yuchou Gan <yuchou.gan@nxp.com>
The architecture of dsp framework has been changed, the role of
dsp driver is transferring messages between dsp framework and user space
application, so change dsp driver to support this function.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
The drm_parse_ycbcr420_deep_color_info() is called only for HDMI 2.0,
however the DC masks were incorrectly set. These were set according
to HDMI 1.4 specification.
This patch will set the deep color depth masks to the HDMI 2.x specs
(see Table 10-6 in HDMI 2.x specs for field descriptions).
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
(cherry picked from commit e3a1cac6fdd88f4391180d89d5881748214a1b4f)
Since the drm_bridge_attach function now supports chained bridges, there
is no need for nwl_dsi_add_bridge and nwl_dsi_del_bridge functions, so
remove them.
Now, we can pass the existent bridge to drm_bridge_attach.
This fixes a bug created during kernel 4.14 rebase process.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
This reverts commit c961b277abd69175e1b1ad733ed6b2b911a61211.
This patched worked on 4.14.18 but on 4.14.34 it now causes a deadlock
because upstream changed phy locking:
commit 6bccf8962b ("net: phy: Restore phy_resume() locking assumption"):
6bccf8962b
Instead of fixing locking just revert this patch, a different fix was
already upsteamed for ksz8081 suspend/resume on 6ul-14x14-evk:
commit e6f4292ae0 ("ARM: dts: imx6ul-14x14-evk: Add ksz8081 phy properties"):
e6f4292ae0
commit 79e498a9c7 ("net: phy: micrel: Restore led_mode and clk_sel on resume"):
79e498a9c7
After reverting this patch suspend/resume still works on imx6ul and
imx6ull evk boards.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Fugang Duan <fugang.duan@nxp.com>
Define a new struct 'dma_metadata' to hold the config parameters
for DEC400D. This struct data should be passed in from the fb's
first gem_obj's 'dma_buf' field.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Fetchdecode may work together with vscaler to do bob deinterlacing.
This patch adds the deinterlacing support for DPU DRM plane by using them.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds dpu_has_prefetch_fixup() helper support.
Users may use it to tell if a DPU has fixups for prefetch
engines in silicon or not.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds the first subsidiary layer0(out of layer0 to layer7)
support for the fetchwarp2 fetch unit to be the backend of DRM plane.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Fetchwarp is a type of dpu fetch unit with the additional
warping function. Each fetchwarp contains 8 subsidiary layers.
Fetchwarp2 can work with fetcheco2 to fetch planar YUV pixel
formats. Also, it may fetch RGB pixel formats. This patch
adds basic fetchwarp2 fetch unit support in the dpu common driver
so that it may fetch frames in RGB pixel formats. YUV pixel formats
and warping function could be supported later.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds the first subsidiary layer0(out of layer0 to layer7)
support for the fetchlayer0/1 fetch units to be the backend of DRM plane.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds some prefetch engine helpers support
in the dpu common driver so that callers may deal with
the prefetch engines of the fetch units the callers
are interested in.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Fetchlayer is a type of dpu fetch unit. Each fetchlayer
contains 8 subsidiary layers. Fetchlayer cannot work with
fetcheco to fetch planar YUV pixel formats. However, it may
fetch RGB pixel formats. This patch adds basic fetchlayer0/1
fetch units support in the dpu common driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
i.MX8QXP B0 silicon config enet IO voltage as 2.5V setting in default,
but MEK and ARM2 board only support 1.8V IO. So change the IO voltage
as 1.8V setting.
Set the MAC RGMII timing as TX no delay and RX delay mode as the default
setting for MEK and ARM2 board.
Since i.MX8QXP B0 silicon ENET IO timing change, to reach better timing
and avoid CRC error, MEK base board and ARM2 cpu board should remove the
driver device for the secord enet port.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
This patch adds prg_set_blit() helper support so that users may
set a particular PRG to be a part of a blit channel.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We don't have correct support for fb x/y source offset for tile formats.
The buffer address calculation is wrong when the offset is non-zero.
Also, finer offset needs a fix in silicon(TKT344978). So, let's do not
support the offset currently. We may add it back after we figure out
how the updated silicon supports the offset.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
According to ANSI-CTA-861-G specification:
* EOTF is 8 bit, not 16;
* metadata type is 8 bit, not 16;
* There's no "Minimum Content Light Level"
This patch will change the HDR metadata structures to reflect that. Also, this
will fix problems seen on some TVs that were rejecting HDR metadata because
it's size was too big (more than 26 bytes).
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
CC: Sandor Yu <sandor.yu@nxp.com>
NXP i.MX7ULP EVK boards all sensors connect with M4 core, A core
has to conmunicate with sensors by virtual io bus like rpmsg bus.
The driver implement the virtual sensor input driver to configure
sensors active/idle/delay actions and report the sensors' event to
user space.
Supply below sysfs for user to enable/disable detector and counter,
set poll delay:
/sys/class/misc/step_counter/enable
/sys/class/misc/step_detector/enable
/sys/class/misc/step_counter/poll_delay
Reviewed-by: Elven Wang <elven.wang@nxp.com>
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Add feature of setting slot index via devicetree alias, to hard code the
mmc/sd root device.
The patch requires additional alias_id fix or it won't work.
Note: minor device number keep independent with this device alias.
Refer to the commit 35928d6c6a76 ("mmc: Allow setting slot index via
devicetree alias").
Acked-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
The DPR works in manual mode for the first frame and we need to
switch it to auto mode so that auto shadow load mechanism works.
The designers require us to switch the DPR manual mode to auto mode
directly for display controllers instead of using the DPR control
done irq handler, because the irq will not come in some cases(which
leads to shadow load failure). Finer switch operations on DPR
register bits are needed for SW_SHADOW_LOAD_SEL, SHADOW_LOAD_EN,
RUN_EN and REPEAT_EN. Also, for overlay planes, we need to wait for
a frame additionally in the "on-the-fly" cases to make sure the
switch is successful. In all, this patch should be able to address
frame dropping and screen tearing issue(due to the shadow load
failure) when users play video on overlay planes.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Use the bus format that was established by CRTC in
crtc->mode.private_flags.
This will be available during enable phase.
The DSI host will be configured via interface_color_coding
and pixel_format (DPI-2 interface ports).
Previously the interface_color_coding was hardcoded to 24-bit.
Set the DSI pixel format before it is necessary in
nwl_dsi_get_bit_clock, during imx_nwl_dsi_enable.
Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com>
The resources for a plane group are shared by the two display streams
of one DPU. Thus, the two Framegen(fg) instances of one DPU should be
in the plane group resource. The resource users may find the fg instance
onto which the resources are built via the stream id. This patch corrects
the number of fg instances in a plane group resource from one to two.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This adds the infrastructure needed to quirk displays
using edid and to mark them a non-desktop.
A non-desktop display is one which shouldn't normally be included
as a part of a desktop environment.
This is meant to cover head mounted devices like HTC Vive.
v2: Change description from non-standard to non-desktop, add docs
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Marius Vlad <marius-cristian.vlad@nxp.com>
(Ported 66660d4cf2 from git://people.freedesktop.org/~airlied/linux)
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as infoframe
to panel which support HDR.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
EA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Hardware may have HDR capability on certain plane
engines. Enabling the same in drm plane structure
so that this can be communicated to user space.
Each drm driver should set this flag to true for planes
which support HDR.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Since other USB 2.0 host may need it, like USB2 for XHCI. We move
this design to HCD core.
Acked-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Peter Chen <peter.chen@nxp.com>
This patch fixes playback for movies with unaligned widths/heights and
adds cropping functionality for tiled formats. Untiled formats will not
have this feature as cropping is a DTRC function.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Add missing sosc_bus_clk/firc_bus_clk/spll_bus_clk clocks which will be used
by other devices later.
All these clocks use the same divider as ddr_div, so ulp_div_table is used.
Besides that, all these clocks need to be controlled by M4, so
CLK_DIVIDER_READ_ONLY is also specified.
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Adding CLK_FRAC_DIVIDER_ZERO_BASED flag to indicate the numerator and
denominator value in register are start from 0.
This can be used to support frac dividers like below:
Divider output clock = Divider input clock x [(frac +1) / (div +1)]
where frac/div in register is:
000b - Divide by 1.
001b - Divide by 2.
010b - Divide by 3.
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
For dividers with zero indicating clock is disabled, instead of giving a
warning each time like "clkx: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not
set" in exist code, we'd like to introduce enable/disable function for it.
e.g.
000b - Clock disabled
001b - Divide by 1
010b - Divide by 2
...
Set rate when the clk is disabled will cache the rate request and only
when the clk is enabled will the driver actually program the hardware to
have the requested divider value. Similarly, when the clk is disabled we'll
write a 0 there, but when the clk is enabled we'll restore whatever rate
(divider) was chosen last.
It does mean that recalc rate will be sort of odd, because when the clk is
off it will return 0, and when the clk is on it will return the right rate.
So to make things work, we'll need to return the cached rate in recalc rate
when the clk is off and read the hardware when the clk is on.
NOTE for the default off divider, the recalc rate will still return 0 as
there's still no proper preset rate. Enable such divider will give user
a reminder error message.
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
'CKIL' clock name is derived from MX6 SoC series which is invalid for
MX7ULP (can't find it from RM). Changing it to the correct 'ROSC'
which is defined in RM.
The exist 'OSC' name is also changed accordingly which should be SOSC
(System OSC).
Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Add handling code to support tiled and compressed pixel source
layout. The tiled only layout will bypass DEC400D and be resolved
by DPR, since DEC400D is only responsible for decompression.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Add a new fb modifier for Vivante compressed and tiled
pixle layout which can be decompressed by DEC400D module
in DCSS.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
In order to support multi-fifo sdma script, the audio driver need to send
the fifo number to dma driver through dma_slave_config, and the cpu_dai
driver should config fifo_num for the audio platform driver, then platform
driver can config fifo_num to dma.
So add new variable fifo_num for struct snd_dmaengine_dai_dma_data.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Robin Gong<yibin.gong@nxp.com>
In order to support multi-fifo sdma script, the audio driver need to send
the fifo number to dma driver through dma_slave_config, so add src_fifo_num
and dst_fifo_num two new variable for struct dma_slave_config.
src_fifo_num: bit 0-7 is the fifo number, bit:8-11 is the fifo offset;
dst_fifo_num: same as src_fifo_num
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Robin Gong<yibin.gong@nxp.com>
This patch effectively enables DTRC module in DCSS to decode tiled
formats from VPU:
* uncompressed G1;
* uncompressed G2;
* compressed G2;
Compressed G2 formats need to pass on the decompression table offsets,
by using the 'dtrc_dec_ofs' property. This is a 64 bit value like below:
64--------48----------32---------16---------0
|<- chroma table ofs ->|<- luma table ofs ->|
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The DPU spec tells us that we need to wait for all pending frames to
be completed when a display stream is disabled. It turns out
that the hardcoded 60-microsecond timeout value is not enough for
some low refresh rate video modes, e.g., 1920x1080@24, which makes
the display stream be disabled incorrectly(leave the hardware an
incorrect machine status). The SoC design indicates that there are
two pending frames to complete in the worst case. This patch waits
for at most three frame duration(which is enough for sure) so that
the hardware may flush out all the pending frames. In case the clock
subsystem provides us a pixel clock with wrong rate and causes the
timeout value be unreasonably long, we truncate it to wait for at
most three seconds.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
"
commit cfdb9821531da523fd1f01536eb67c8b8451477f
Author: Oliver Brown <oliver.brown@nxp.com>
Date: Tue Jan 2 07:46:06 2018 -0600
dc: Add controls for display controller resets.
"
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Currently the clock parent actually is failed to be restored in power
domain driver due to the set_parent will bail out early as the clk core
already cached the same old parent.
Implement a CLK_SET_PARENT_NOCACHE flag in clk core and register all
SC mux clocks with this flag to make sure the clk core won't bypass
the SC clock parent setting.
[ Aisheng: "Add commit message" ]
Reviewed-by: Anson Huang <anson.huang@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
In order to avoid license problem of Cadence header files, these
license files has been wrappered into a library and new interface
has been abstracted to replace the interface of Cadence header
files.
So update the mxc_hifi4.h file to provide new interface for
user space to use.
Signed-off-by: Weiguang Kong <weiguang.kong@nxp.com>
On i.MX7ULP B0 chip, SNVS is located on M4 domain,
all RTC related functions need to use RPMSG channel
to communicate with M4 to proceed hardware operation.
The RTC RPMSG channel index is 6.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
This patch makes the necessary changes so that, for downscaling ratios
more than 3:1 and up to 7:1 (for video) and 5:1 (for graphics), the
WRSCL/RDSRC path will be used. This way the DRAM bandwidth will be lower
and spread evenly across the frame time.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The CCGR RAWNAND is shared by apbh-dma and gpmi clocks, so must use
imx_clk_gate2_shared2 to produce two clocks. Otherwise, apbh-dma clock
won't be enabled individually.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Add uSDHC clock MUX to allow uSDHC driver to select
parent, currently only support PLL0 and PLL1 as
uSDHC clock's parent.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Haibo Chen <haibo.chen@nxp.com>
When scaling up/down, DCSS has limits that cannot be exceeded. This
patch adds checks before the plane is updated and rejects those planes
that exceed the up/down scale limits.
Currently, the limit is 3:1 for downscaling and 1:3 for upscaling for
both video and graphics channels.
When support for WR_SCL/RD_SRC will be added, these limits will increase
to the following values:
* video: 7:1 downscale, 1:7 upscale
* graphics: 5:1 downscale, 1:5 upscale
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
To workaround the errata TKT320950, DPR/PRG need to evade the first dumb frame
which is generated by DPU. The way we achieve that is to bypass TCON(but set
the TCON sync signals and KA_CHUCK strobe signal up) before enabling the DPU
display controller, and then enable the display controller, wait for the frame
index starting to move and finally switch TCON to operation mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
When we use prefetch, we use DPR and PRG to do frame input cropping.
Thus, the stride of fetcheco is the stride of cropped frame, which means
the value of the stride is cropped_width * bytes_per_pixel. Since the
pixel format has to be NV12 or NV21 when we use prefetch, we assume the
cropped_width stands for how many UV we have in bytes for one line, while
bytes_per_pixel should be 8bits for every U or V component. Also, to
address TKT339017, when we use prefetch engine for fetcheco, we need to
round the stride up to the fetcheco burst size, i.e., burst length
multiplies 8 bytes. According to TKT343664, the buffer base address has
to align to burst size, so we'll pick an appropriate burst size value in
fetcheco_source_stride().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
When we use prefetch, we use DPR and PRG to do frame input cropping. Thus,
the stride of fetchdecode is the stride of cropped frame, which means the
value of the stride is cropped_width * bytes_per_pixel. Also, to address
TKT339017, when we use prefetch engine for fetchdecode, we need to round
the frame stride up to the fetchdecode burst size, i.e., burst length
multiplies 8 bytes. According to TKT343664, the buffer base address has
to align to burst size, so we'll pick an appropriate burst size value in
fetchdecode_source_stride().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds helper fetcheco_set_burstlength() so that
the burst length of fetcheco can be set to appropriate value.
When we don't use prefetch engine, the burst length is set to
the maximal value - 16. When we use prefetch engine, the burst
length should make the buffer base address align to burst size
but not greater than 16. This alignment operation can address
the issue recorded by TKT343664.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds helper fetchdecode_set_burstlength() so that
the burst length of fetchdecode can be set to appropriate value.
When we don't use prefetch engine, the burst length is set to
the maximal value - 16. When we use prefetch engine, the burst
length should make the buffer base address align to burst size
but not greater than 16. This alignment operation can address
the issue recorded by TKT343664.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds some helpers to set/get fetcheco off pin.
We need to pin fetcheco off when the primary plane is disabled and the
relevant fetcheco is feed by prefetch engine.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
We will support DPR interrupts via DPU core driver.
In order to distinguish bewteen the inner DPU interrupts and the DPR
interrupts, let's rename some software stuffs which are related to
DPU interrupts so that they may show they are DPU inner explicitly.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The Display Prefetch Resolve(DPR) is a processor of fetching display data
before the display pipeline which needs data to drive pixels in the active
display region. The data is transformed, or resolved from a variety of
tiled buffer formats into linear format. The DPR transaction sequences are
issued with a high level of DRAM efficiency. This patch adds the base
driver support for i.MX8qm/qxp DPR.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The Pretch Resolve Gasket(PRG) is a digital core function as a gasket
interface between RTRAM controller and DPU. The main function of PRG
is to convert the AXI interface to RTRAM interface and remapping the
ARADDR to a RTRAM address. This patch adds the base driver support
for i.MX8qm/qxp PRG.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Amphion VPU has a tiled layout using 8x128 pixel vertical strips,
where each strip contains 1x16 groups of 8x8 pixels in a row-major layout.
Signed-off-by: Song Bing <bing.song@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Config NOC to limit bandwidth to 4GB for both VPU
and CPU to avoid lcdif flickering only when lcdif is enabled.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 8ab89ebeb94a423792bf588bdf2354c5960d8f13)
Currently the generic power domain suspend code pm_genpd_suspend_noirq
will try to power off a domain used by devices in genpd_sync_poweroff
if its status is not GPD_STATE_ACTIVE.
However, for power domains supporting multiple low power states, it may
already enter an intermediate low power state by runtime PM before system
suspend and the status is already GPD_STATE_POWER_OFF which results in
then the power domain stay at an intermediate low power state during
system suspend.
Let's give the power domain a chance to switch to the deepest state in
case it's already off but in an intermediate low power state.
Due to power domain is alway off, so no need to check device wakeup
case anymore.
Reviewed-by: Frank Li <frank.li@nxp.com>
Reviewed-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
This patch adds 'use_global_alpha' property to the primary plane, so that
one can choose whether to use global alpha instead of per-pixel alpha,
when the framebuffer has per-pixel alpha.
Framebuffers that do not have per-pixel alpha will always use global
alpha.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Adds TEE_IOCTL_PARAM_ATTR_META with can be used to indicate meta
parameters when communicating with user space. These meta parameters can
be used by supplicant support multiple parallel requests at a time.
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Modified from: From: https://github.com/linaro-swg/linux.git
Conflicts:
drivers/tee/tee_core.c
(cherry picked from commit 66d81fcf145fdc55322c0a11764c76a43d90ecad)
Adds a kernel internal TEE client interface to be used by other drivers.
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
From: https://github.com/linaro-swg/linux.git
(cherry picked from commit 860c46087c99c24073cc722b12c0017bb0ce0a79)
This change allows userland to create a tee_shm object that refers
to a dmabuf reference.
Userland provides a dmabuf file descriptor as buffer reference.
The created tee_shm object exported as a brand new dmabuf reference
used to provide a clean fd to userland. Userland shall closed this new
fd to release the tee_shm object resources. The initial dmabuf resources
are tracked independently through original dmabuf file descriptor.
Once the buffer is registered and until it is released, TEE driver
keeps a refcount on the registered dmabuf structure.
This change only support dmabuf references that relates to physically
contiguous memory buffers.
New tee_shm flag to identify tee_shm objects built from a registered
dmabuf: TEE_SHM_EXT_DMA_BUF. Such tee_shm structures are flagged both
TEE_SHM_DMA_BUF and TEE_SHM_EXT_DMA_BUF.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
From: https://github.com/linaro-swg/linux.git
(cherry picked from commit 41e21e5c405530590dc2dd10b2a8dbe64589840f)
Add CLKO2 for i.MX8MQ
Set parent for MIPI CSI1/2 CORE/PHY_REF/ESC
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Currently, the Northwest Logic MIPI-DSI controller host specific code
resides under drm/bridge, but is not a real drm_bridge. It creates a
drm_bridge and adds itself to the drm_encoder that handles this file,
but this is wrong, since it does not implement the drm_bridge_funcs.
The correct way to implement a drm_bridge is to add the drm_bridge and
let other components (another bridge or a drm_encoder) to attach to this
bridge.
Since we are doing this, a new compatible strings can be used for this
driver: "nwl,mipi-dsi".
Since this was used by nwl_dsi-imx.c, update that driver to use this
bridge correctly.
This is needed in order to add support for MIPI-DSI on 8MQ. The IMX_NWL
driver will either add a DSI encoder to DRM, or a DSI bridge.
The encoder will be used by imx-drm-core driver, while the bridge
will be used by MXSFB driver (which creates a simple display pipe).
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Add header file for the i.MX8mq IOMUXC GPR register offsets definitions.
Also, include definition for the GPR_MIPI_MUX_SEL from GPR13, needed by
MIPI-DSI driver.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
DTG needs to be completely stopped before changing the display
resolution through modesetting. If DTG is not stopped, any change in
resolution could result in unpredictable results, like split screen,
etc.
This patch fixes that by introducing a completion signaling mechanism so
that we can signal the DRM CRTC when DCSS core is done stopping DTG.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
The Video PLL2 has a output enable bit to do clk gate,
So we need to register this gate to save power.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
drm_mode_create_lease
Creates a lease for a list of drm mode objects, returning an
fd for the new drm_master and a 64-bit identifier for the lessee
drm_mode_list_lesees
List the identifiers of the lessees for a master file
drm_mode_get_lease
List the leased objects for a master file
drm_mode_revoke_lease
Erase the set of objects managed by a lease.
This should suffice to at least create and query leases.
Changes for v2 as suggested by Daniel Vetter <daniel.vetter@ffwll.ch>:
* query ioctls only query the master associated with
the provided file.
* 'mask_lease' value has been removed
* change ioctl has been removed.
Changes for v3 suggested in part by Dave Airlie <airlied@gmail.com>
* Add revoke ioctl.
Changes for v4 suggested by Dave Airlie <airlied@gmail.com>
* Expand on the comment about the magic use of &drm_lease_idr_object
* Pad lease ioctl structures to align on 64-bit boundaries
Changes for v5 suggested by Dave Airlie <airlied@gmail.com>
* Check for non-negative object_id in create_lease to avoid debug
output from the kernel.
Changes for v6 provided by Dave Airlie <airlied@gmail.com>
* For non-universal planes add primary/cursor planes to lease
If we aren't exposing universal planes to this userspace client,
and it requests a lease on a crtc, we should implicitly export the
primary and cursor planes for the crtc.
If the lessee doesn't request universal planes, it will just see
the crtc, but if it does request them it will then see the plane
objects as well.
This also moves the object look ups earlier as a side effect, so
we'd exit the ioctl quicker for non-existant objects.
* Restrict leases to crtc/connector/planes.
This only allows leasing for objects we wish to allow.
Changes for v7 provided by Dave Airlie <airlied@gmail.com>
* Check pad args are 0
* Check create flags and object count are valid.
* Check return from fd allocation
* Refactor lease idr setup and add some simple validation
* Use idr_mutex uniformly (Keith)
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 62884cd386)
Attempts to modify un-leased objects are rejected with an error.
Information returned about unleased objects is modified to make them
appear unusable and/or disconnected.
Changes for v2 as suggested by Daniel Vetter <daniel.vetter@ffwll.ch>:
* With the change in the __drm_mode_object_find API to pass the
file_priv along, we can now centralize most of the lease-based
access checks in that function.
* A few places skip that API and require in-line checks.
Changes for v3 provided by Dave Airlie <airlied@redhat.com>
* remove support for leasing encoders.
* add support for leasing planes.
Changes for v4
* Only call drm_lease_held if DRIVER_MODESET.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 7de440db20)
This provides new data structures to hold "lease" information about
drm mode setting objects, and provides for creating new drm_masters
which have access to a subset of the available drm resources.
An 'owner' is a drm_master which is not leasing the objects from
another drm_master, and hence 'owns' them.
A 'lessee' is a drm_master which is leasing objects from some other
drm_master. Each lessee holds the set of objects which it is leasing
from the lessor.
A 'lessor' is a drm_master which is leasing objects to another
drm_master. This is the same as the owner in the current code.
The set of objects any drm_master 'controls' is limited to the set of
objects it leases (for lessees) or all objects (for owners).
Objects not controlled by a drm_master cannot be modified through the
various state manipulating ioctls, and any state reported back to user
space will be edited to make them appear idle and/or unusable. For
instance, connectors always report 'disconnected', while encoders
report no possible crtcs or clones.
The full list of lessees leasing objects from an owner (either
directly, or indirectly through another lessee), can be searched from
an idr in the drm_master of the owner.
Changes for v2 as suggested by Daniel Vetter <daniel.vetter@ffwll.ch>:
* Sub-leasing has been disabled.
* BUG_ON for lock checking replaced with lockdep_assert_held
* 'change' ioctl has been removed.
* Leased objects can always be controlled by the lessor; the
'mask_lease' flag has been removed
* Checking for leased status has been simplified, replacing
the drm_lease_check function with drm_lease_held.
Changes in v3, some suggested by Dave Airlie <airlied@gmail.com>
* Add revocation. This allows leases to be effectively revoked by
removing all of the objects they have access to. The lease itself
hangs around as it's hanging off a file.
* Free the leases IDR when the master is destroyed
* _drm_lease_held should look at lessees, not lessor
* Allow non-master files to check for lease status
Changes in v4, suggested by Dave Airlie <airlied@gmail.com>
* Formatting and whitespace changes
Changes in v5 (airlied)
* check DRIVER_MODESET before lease destroy call
* check DRIVER_MODESET for lease revoke (Chris)
* Use idr_mutex uniformly for all lease elements of struct drm_master. (Keith)
Signed-off-by: Keith Packard <keithp@keithp.com>
(cherry picked from commit 2ed077e467)
This will allow __drm_mode_object_file to be extended to perform
access control checks based on the file in use.
v2: Also fix up vboxvideo driver in staging
[airlied: merging early as this is an API change]
Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit 418da17214)
Separate out lease debugging from the core.
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit e7646f84ad)
Add missing clocks for MIPI-DSI SS: RX_ESC and TX_ESC
Also added the posibility to select clock parents for MIPI-DSI versus
LVDS.
The SCFW was changed, so now the LVDS pixel and phy clocks need to
specify their parrents.
Also, the TX_ESC and RX_ESC clocks from MIPI-DSI need to specify their
parrents in DTS files.
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Oliver Brown <oliver.brown@nxp.com>
Christoph Hellwig